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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: dblfetch.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: This is one step beyond the simplest instruction fetch,
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// prefetch.v. dblfetch.v uses memory pipelining to fetch two
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// instruction words in one cycle, figuring that the unpipelined CPU can't
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// go through both at once, but yet recycles itself fast enough for the
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// next instruction that would follow. It is designed to be a touch
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// faster than the single instruction prefetch, although not as fast as
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// the prefetch and cache found elsewhere.
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//
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// There are some gotcha's in this logic, however. For example, it's
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// illegal to switch devices mid-transaction, since the second device
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// might have different timing. I.e. the first device might take 8
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// clocks to create an ACK, and the second device might take 2 clocks, the
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// acks might therefore come on top of each other, or even out of order.
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// But ... in order to keep logic down, we keep track of the PC in the
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// o_wb_addr register. Hence, this register gets changed on any i_new_pc.
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// The i_pc value associated with i_new_pc will only be valid for one
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// clock, hence we can't wait to change. To keep from violating the WB
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// rule, therefore, we *must* immediately stop requesting any transaction,
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// and then terminate the bus request as soon as possible.
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//
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// This has consequences in terms of logic used, leaving this routine
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// anything but simple--even though the number of wires affected by
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// this is small (o_wb_cyc, o_wb_stb, and last_ack).
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module dblfetch(i_clk, i_rst, i_new_pc, i_clear_cache,
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i_stall_n, i_pc, o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data,
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o_illegal);
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parameter ADDRESS_WIDTH=32, AUX_WIDTH = 1;
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localparam AW=ADDRESS_WIDTH;
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input i_clk, i_rst, i_new_pc, i_clear_cache,
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i_stall_n;
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input [(AW-1):0] i_pc;
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output reg [31:0] o_i;
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output reg [(AW-1):0] o_pc;
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output wire o_v;
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// Wishbone outputs
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output wire [31:0] o_wb_data;
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// And return inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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// And ... the result if we got an error
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output reg o_illegal;
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assign o_wb_we = 1'b0;
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assign o_wb_data = 32'h0000;
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reg last_ack, last_stb, invalid_bus_cycle;
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reg [31:0] cache [0:1];
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reg cache_read_addr, cache_write_addr;
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reg [1:0] cache_valid;
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initial o_wb_cyc = 1'b0;
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initial o_wb_stb = 1'b0;
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always @(posedge i_clk)
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if ((i_rst)||(i_wb_err))
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begin
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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// last_stb <= 1'b0;
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// last_ack <= 1'b0;
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end else if (o_wb_cyc)
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begin
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if ((o_wb_stb)&&(!i_wb_stall))
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begin
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// last_stb <= 1'b1;
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o_wb_stb <= !last_stb;
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end
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// if (i_wb_ack)
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// last_ack <= 1'b1;
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if ((i_new_pc)||(invalid_bus_cycle))
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o_wb_stb <= 1'b0;
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if ((i_wb_ack)&&(
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// Relase the bus on the second ack
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(last_ack)
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// Or on the first ACK, if we've been told
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// we have an invalid bus cycle
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||((o_wb_stb)&&(i_wb_stall)&&(last_stb)&&(
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(i_new_pc)||(invalid_bus_cycle)))
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))
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begin
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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end
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if ((!last_stb)&&(i_wb_stall)&&((i_new_pc)||(invalid_bus_cycle)))
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// Also release the bus with no acks, if we
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// haven't made any requests
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begin
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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end
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end else if ((invalid_bus_cycle)
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||((o_v)&&(i_stall_n)&&(cache_read_addr))) // Initiate a bus cycle
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begin
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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// last_stb <= 1'b0;
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// last_ack <= 1'b0;
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end
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initial last_stb = 1'b0;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(o_wb_stb)&&(!i_wb_stall))
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last_stb <= 1'b1;
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else if (!o_wb_cyc)
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last_stb <= 1'b0;
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initial last_ack = 1'b0;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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last_ack <= 1'b1;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(i_wb_stall)&&(
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(i_new_pc)||(invalid_bus_cycle)))
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last_ack <= 1'b1;
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else if ((o_wb_cyc)&&(o_wb_stb)&&(!i_wb_stall)&&(!last_stb)&&(
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(i_new_pc)||(invalid_bus_cycle)))
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last_ack <= 1'b1;
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else if (!o_wb_cyc)
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last_ack <= 1'b0;
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initial invalid_bus_cycle = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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invalid_bus_cycle <= 1'b0;
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else if ((i_new_pc)||(i_clear_cache))
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invalid_bus_cycle <= 1'b1;
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else if (!o_wb_cyc)
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invalid_bus_cycle <= 1'b0;
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initial o_wb_addr = {(AW){1'b1}};
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always @(posedge i_clk)
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if (i_new_pc)
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o_wb_addr <= i_pc;
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else if ((o_wb_stb)&&(!i_wb_stall)&&(!invalid_bus_cycle))
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o_wb_addr <= o_wb_addr + 1'b1;
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initial cache_write_addr = 1'b0;
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always @(posedge i_clk)
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if (!o_wb_cyc)
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cache_write_addr <= 1'b0;
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else if ((o_wb_cyc)&&(i_wb_ack))
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cache_write_addr <= cache_write_addr + 1'b1;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_ack))
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cache[cache_write_addr] <= i_wb_data;
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initial cache_read_addr = 1'b0;
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always @(posedge i_clk)
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if ((i_new_pc)||(invalid_bus_cycle)
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||((o_v)&&(cache_read_addr)&&(i_stall_n)))
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cache_read_addr <= 1'b0;
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else if ((o_v)&&(i_stall_n))
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cache_read_addr <= 1'b1;
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always @(posedge i_clk)
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if ((i_new_pc)||(invalid_bus_cycle))
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cache_valid <= 2'b00;
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else begin
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if ((o_v)&&(i_stall_n))
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cache_valid[cache_read_addr] <= 1'b0;
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if ((o_wb_cyc)&&(i_wb_ack))
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cache_valid[cache_write_addr] <= 1'b1;
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end
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initial o_i = {(32){1'b1}};
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always @(posedge i_clk)
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if ((i_stall_n)&&(o_wb_cyc)&&(i_wb_ack))
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o_i <= i_wb_data;
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else
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o_i <= cache[cache_read_addr];
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initial o_pc = 0;
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always @(posedge i_clk)
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if (i_new_pc)
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o_pc <= i_pc;
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else if ((o_v)&&(i_stall_n))
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o_pc <= o_pc + 1'b1;
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assign o_v = cache_valid[cache_read_addr];
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initial o_illegal = 1'b0;
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always @(posedge i_clk)
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if ((o_wb_cyc)&&(i_wb_err))
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o_illegal <= 1'b1;
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else if ((!o_wb_cyc)&&((i_new_pc)||(invalid_bus_cycle)))
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o_illegal <= 1'b0;
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endmodule
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