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dgisselq |
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename: div.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: Provide an Integer divide capability to the Zip CPU.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// `include "cpudefs.v"
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//
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module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator,
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o_busy, o_valid, o_err, o_quotient, o_flags);
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parameter BW=32, LGBW = 5;
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input i_clk, i_rst;
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// Input parameters
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input i_wr, i_signed;
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input [(BW-1):0] i_numerator, i_denominator;
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// Output parameters
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output reg o_busy, o_valid, o_err;
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output reg [(BW-1):0] o_quotient;
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output wire [3:0] o_flags;
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reg [(2*BW-2):0] r_divisor;
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reg [(BW-1):0] r_dividend;
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wire [(BW):0] diff; // , xdiff[(BW-1):0];
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assign diff = r_dividend - r_divisor[(BW-1):0];
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// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
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reg r_sign, pre_sign, r_z, r_c;
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reg [(LGBW):0] r_bit;
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always @(posedge i_clk)
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if (i_rst)
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begin
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o_busy <= 1'b0;
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end else if (i_wr)
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begin
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o_busy <= 1'b1;
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end else if ((o_busy)&&((r_bit == 6'h0)||(o_err)))
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o_busy <= 1'b0;
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// else busy is zero and stays at zero
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always @(posedge i_clk)
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if ((i_rst)||(i_wr))
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o_valid <= 1'b0;
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else if (o_busy)
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begin
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if ((r_bit == 6'h0)||(o_err))
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o_valid <= (o_err)||(~r_sign);
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end else if (r_sign)
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begin
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// if (o_err), o_valid is already one.
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// if not, o_valid has not yet become one.
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o_valid <= (~o_err); // 1'b1;
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end else
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o_valid <= 1'b0;
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always @(posedge i_clk)
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if((i_rst)||(o_valid))
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o_err <= 1'b0;
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else if (o_busy)
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o_err <= (r_divisor == 0);
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always @(posedge i_clk)
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if (i_wr)
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begin
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o_quotient <= 0;
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// r_bit <= { 1'b1, {(LGBW){1'b0}} };
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r_bit <= { 1'b0, {(LGBW){1'b1}} };
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r_divisor <= { i_denominator, {(BW-1){1'b0}} };
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r_dividend <= i_numerator;
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r_sign <= 1'b0;
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pre_sign <= i_signed;
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r_z <= 1'b1;
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end else if (pre_sign)
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begin
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// r_bit <= r_bit - 1;
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r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));;
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if (r_dividend[BW-1])
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r_dividend <= -r_dividend;
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if (r_divisor[(2*BW-2)])
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r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
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pre_sign <= 1'b0;
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end else if (o_busy)
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begin
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r_bit <= r_bit + {(LGBW+1){1'b1}}; // r_bit = r_bit - 1;
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r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
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if (|r_divisor[(2*BW-2):(BW)])
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begin
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end else if (diff[BW])
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begin
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end else begin
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r_dividend <= diff[(BW-1):0];
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o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
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r_z <= 1'b0;
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end
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end else if (r_sign)
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begin
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r_sign <= 1'b0;
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o_quotient <= -o_quotient;
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end
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// Set Carry on an exact divide
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wire w_n;
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always @(posedge i_clk)
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r_c <= (o_busy)&&((diff == 0)||(r_dividend == 0));
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assign w_n = o_quotient[(BW-1)];
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assign o_flags = { 1'b0, w_n, r_c, r_z };
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endmodule
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