OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Blame information for rev 82

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 69 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    idecode.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This RTL file specifies how instructions are to be decoded
8
//              into their underlying meanings.  This is specifically a version
9
//      designed to support a "Next Generation", or "Version 2" instruction
10
//      set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
11
//      in cpudefs.v.
12
//
13
//      I expect to (eventually) retire the old instruction set, at which point
14
//      this will become the default instruction set decoder.
15
//
16
//
17
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
//
41
//
42
`define CPU_CC_REG      4'he
43
`define CPU_PC_REG      4'hf
44
//
45
`include "cpudefs.v"
46
//
47
//
48
//
49
module  idecode(i_clk, i_rst, i_ce, i_stalled,
50
                i_instruction, i_gie, i_pc, i_pf_valid,
51
                        i_illegal,
52
                o_phase, o_illegal,
53
                o_pc, o_gie,
54
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
55
                o_cond, o_wF,
56
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
57
                o_wR, o_rA, o_rB,
58 71 dgisselq
                o_early_branch, o_branch_pc,
59
                o_pipe
60 69 dgisselq
                );
61
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
62
                        IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
63
        input                   i_clk, i_rst, i_ce, i_stalled;
64
        input   [31:0]           i_instruction;
65
        input                   i_gie;
66
        input   [(AW-1):0]       i_pc;
67
        input                   i_pf_valid, i_illegal;
68
        output  wire            o_phase;
69
        output  reg             o_illegal;
70
        output  reg     [(AW-1):0]       o_pc;
71
        output  reg             o_gie;
72
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
73
        output  wire    [31:0]   o_I;
74
        output  reg             o_zI;
75
        output  reg     [3:0]    o_cond;
76
        output  reg             o_wF;
77
        output  reg     [3:0]    o_op;
78
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break, o_lock;
79
        output  reg             o_wR, o_rA, o_rB;
80
        output  wire            o_early_branch;
81
        output  wire    [(AW-1):0]       o_branch_pc;
82 71 dgisselq
        output  reg             o_pipe;
83 69 dgisselq
 
84
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
85
        wire                    o_dcd_early_branch;
86
        wire    [(AW-1):0]       o_dcd_branch_pc;
87
        reg     o_dcdI, o_dcdIz;
88
 
89
 
90
        wire    [4:0]    w_op;
91
        wire            w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
92
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
93
        wire            w_dcdR_pc, w_dcdR_cc;
94
        wire            w_dcdA_pc, w_dcdA_cc;
95
        wire            w_dcdB_pc, w_dcdB_cc;
96
        wire    [3:0]    w_cond;
97
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
98
        wire            w_wR, w_rA, w_rB, w_wR_n;
99
 
100
 
101
        wire    [31:0]   iword;
102
`ifdef  OPT_VLIW
103
        reg     [16:0]   r_nxt_half;
104
        assign  iword = (o_phase)
105
                                // set second half as a NOOP ... but really 
106
                                // shouldn't matter
107
                        ? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
108
                        : i_instruction;
109
`else
110
        assign  iword = { 1'b0, i_instruction[30:0] };
111
`endif
112
 
113
        assign  w_op= iword[26:22];
114
        assign  w_mov    = (w_op      == 5'h0f);
115
        assign  w_ldi    = (w_op[4:1] == 4'hb);
116
        assign  w_cmptst = (w_op[4:1] == 4'h8);
117
        assign  w_ldixx  = (w_op[4:1] == 4'h4);
118
        assign  w_ALU    = (~w_op[4]);
119
 
120
        // 4 LUTs
121
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
122
                                iword[30:27] };
123
        // 4 LUTs
124
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
125
                                iword[17:14] };
126
 
127
        // 0 LUTs
128
        assign  w_dcdA = w_dcdR;
129
        // 2 LUTs, 1 delay each
130
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
131
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
132
        // 0 LUTs
133
        assign  w_dcdA_pc = w_dcdR_pc;
134
        assign  w_dcdA_cc = w_dcdR_cc;
135
        // 2 LUTs, 1 delays each
136
        assign  w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
137
        assign  w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
138
 
139
        // Under what condition will we execute this
140
        // instruction?  Only the load immediate instruction
141
        // is completely unconditional.
142
        //
143
        // 3+4 LUTs
144
        assign  w_cond = (w_ldi) ? 4'h8 :
145
                        (iword[31])?{(iword[20:19]==2'b00),
146
                                        1'b0,iword[20:19]}
147
                        : { (iword[21:19]==3'h0), iword[21:19] };
148
 
149
        // 1 LUT
150
        assign  w_dcdM    = (w_op[4:1] == 4'h9);
151
        // 1 LUT
152
        assign  w_dcdDV   = (w_op[4:1] == 4'ha);
153
        // 1 LUT
154
        assign  w_dcdFP   = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
155
        // 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
156
        //      Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
157
        assign  w_rA     = (w_dcdFP)
158
                                // Divide's read A
159
                                ||(w_dcdDV)
160
                                // ALU read's A, unless it's a MOV to A
161
                                // This includes LDIHI/LDILO
162
                                ||((~w_op[4])&&(w_op[3:0]!=4'hf))
163
                                // STO's read A
164
                                ||((w_dcdM)&&(w_op[0]))
165
                                // Test/compares
166
                                ||(w_op[4:1]== 4'h8);
167
        // 1 LUTs -- do we read a register for operand B?  Specifically, do
168
        // we need to stall if the register is not (yet) ready?
169
        assign  w_rB     = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx)));
170
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
171
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
172
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
173
                                ||(w_cmptst);
174
        assign  w_wR     = ~w_wR_n;
175
        // 1-output bit (5 Opcode bits, 3 out-reg bits, 3 condition bits)
176
        //      
177
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
178
        assign  w_wF     = (w_cmptst)
179
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
180
                                ||((w_ALU)&&(~w_mov)&&(~w_ldixx))));
181
 
182
        // Bottom 13 bits: no LUT's
183
        // w_dcd[12: 0] -- no LUTs
184
        // w_dcd[   13] -- 2 LUTs
185
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
186
        // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
187
        reg     [22:0]   r_I;
188
        wire    [22:0]   w_I, w_fullI;
189
        wire            w_Iz;
190
 
191
        assign  w_fullI = (w_ldi) ? { iword[22:0] } // LDI
192
                        :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
193
                        :((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
194
                        : { {(23-14){iword[13]}}, iword[13:0] }
195
                        ));
196
 
197
`ifdef  OPT_VLIW
198
        wire    [5:0]    w_halfI;
199
        assign  w_halfI = (w_ldi) ? iword[5:0]
200
                                :((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
201
        assign  w_I  = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
202
`else
203
        assign  w_I  = w_fullI;
204
`endif
205
        assign  w_Iz = (w_I == 0);
206
 
207
 
208
`ifdef  OPT_VLIW
209
        //
210
        // The o_phase parameter is special.  It needs to let the software
211
        // following know that it cannot break/interrupt on an o_phase asserted
212
        // instruction, lest the break take place between the first and second
213
        // half of a VLIW instruction.  To do this, o_phase must be asserted
214
        // when the first instruction half is valid, but not asserted on either
215
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
216
        reg     r_phase;
217
        initial r_phase = 1'b0;
218
        always @(posedge i_clk)
219
                if (i_rst) // When no instruction is in the pipe, phase is zero
220
                        r_phase <= 1'b0;
221
                else if (i_ce)
222
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
223
        // Phase is '1' on the first instruction of a two-part set
224
        // But, due to the delay in processing, it's '1' when our output is
225
        // valid for that first part, but that'll be the same time we
226
        // are processing the second part ... so it may look to us like a '1'
227
        // on the second half of processing.
228
 
229
        assign  o_phase = r_phase;
230
`else
231
        assign  o_phase = 1'b0;
232
`endif
233
 
234
 
235 71 dgisselq
        initial o_illegal = 1'b0;
236 69 dgisselq
        always @(posedge i_clk)
237 71 dgisselq
                if (i_rst)
238
                        o_illegal <= 1'b0;
239
                else if (i_ce)
240 69 dgisselq
                begin
241
`ifdef  OPT_VLIW
242 71 dgisselq
                        o_illegal <= (i_illegal);
243 69 dgisselq
`else
244
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
245
`endif
246
                        if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
247
                                o_illegal <= 1'b1;
248
 
249
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
250
                                o_illegal <= 1'b1;
251
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
252
                                o_illegal <= 1'b1;
253
 
254
 
255
                        if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
256
                                o_illegal <= 1'b1;
257
                        else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
258
                                o_illegal <= 1'b1;
259
 
260 71 dgisselq
                        if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
261
                                &&(
262
                                        (w_op[2:0] != 3'h2)      // LOCK
263
                                        &&(w_op[2:0] != 3'h1)    // BREAK
264
                                        &&(w_op[2:0] != 3'h0)))  // NOOP
265
                                o_illegal <= 1'b1;
266
                end
267
 
268
 
269
        always @(posedge i_clk)
270
                if (i_ce)
271
                begin
272
`ifdef  OPT_VLIW
273
                        if (~o_phase)
274
                        begin
275
                                o_gie<= i_gie;
276
                                // i.e. dcd_pc+1
277
                                o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
278
                        end
279
`else
280
                        o_gie<= i_gie;
281
                        o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
282
`endif
283
 
284 69 dgisselq
                        // Under what condition will we execute this
285
                        // instruction?  Only the load immediate instruction
286
                        // is completely unconditional.
287
                        o_cond <= w_cond;
288
                        // Don't change the flags on conditional instructions,
289
                        // UNLESS: the conditional instruction was a CMP
290
                        // or TST instruction.
291
                        o_wF <= w_wF;
292
 
293
                        // Record what operation/op-code (4-bits) we are doing
294
                        //      Note that LDI magically becomes a MOV
295
                        //      instruction here.  That way it's a pass through
296
                        //      the ALU.  Likewise, the two compare instructions
297
                        //      CMP and TST becomes SUB and AND here as well.
298
                        // We keep only the bottom four bits, since we've
299
                        // already done the rest of the decode necessary to 
300
                        // settle between the other instructions.  For example,
301
                        // o_FP plus these four bits uniquely defines the FP
302
                        // instruction, o_DV plus the bottom of these defines
303
                        // the divide, etc.
304
                        o_op <= (w_ldi)? 4'hf:w_op[3:0];
305
 
306
                        // Default values
307
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
308
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
309
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
310
                        o_wR  <= w_wR;
311
                        o_rA  <= w_rA;
312
                        o_rB  <= w_rB;
313
                        r_I    <= w_I;
314
                        o_zI   <= w_Iz;
315
 
316
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
317
                        o_M    <=  w_dcdM;
318
                        o_DV   <=  w_dcdDV;
319
                        o_FP   <=  w_dcdFP;
320
 
321
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
322
                        o_lock  <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
323
`ifdef  OPT_VLIW
324
                        r_nxt_half <= { iword[31], iword[13:5],
325
                                ((iword[21])? iword[20:19] : 2'h0),
326
                                iword[4:0] };
327
`endif
328
                end
329
 
330
 
331
        generate
332
        if (EARLY_BRANCHING!=0)
333
        begin
334
                reg                     r_early_branch;
335
                reg     [(AW-1):0]       r_branch_pc;
336
                always @(posedge i_clk)
337
                        if ((i_ce)&&(w_dcdR_pc)&&(w_cond[3]))
338
                        begin
339
                                if ((w_op == 5'hf)&&(w_dcdB_pc)&&(w_dcdA_pc))
340
                                begin // Move (X+PC) to PC
341
                                        r_early_branch     <= 1'b1;
342
                                end else if (w_op[4:1] == 4'hb) // LDI to PC
343
                                begin // LDI x,PC
344
                                        r_early_branch     <= 1'b1;
345
                                end else if ((w_op[4:0] == 5'h00)&&(~w_rB)&&(w_dcdA_pc))
346
                                begin // Add x,PC
347
                                        r_early_branch     <= 1'b1;
348
                                end else begin
349
                                        r_early_branch     <= 1'b0;
350
                                end
351
                        end else begin
352
                                if (i_ce)
353
                                        r_early_branch <= 1'b0;
354
                        end
355
                always @(posedge i_clk)
356
                        if (i_ce)
357
                        begin
358
                                if (w_op[4:1] == 4'hb)
359
                                        r_branch_pc <= {{(AW-23){w_I[22]}},w_I};
360
                                else
361
                                r_branch_pc <= i_pc+{{(AW-23){w_I[22]}},w_I}
362
                                                +{{(AW-1){1'b0}},1'b1};
363
                        end
364
 
365
                assign  o_early_branch     = r_early_branch;
366
                assign  o_branch_pc        = r_branch_pc;
367
        end else begin
368
                assign  o_early_branch = 1'b0;
369
                assign  o_branch_pc = {(AW){1'b0}};
370
        end endgenerate
371
 
372 71 dgisselq
 
373
        // To be a pipeable operation there must be ...
374
        //      1. Two valid adjacent instructions
375
        //      2. Both must be memory operations, of the same time (both lods
376
        //              or both stos)
377
        //      3. Both must use the same register base address
378
        //      4. Both must be to the same address, or the address incremented
379
        //              by one
380
        // Note that we're not using iword here ... there's a lot of logic
381
        // taking place, and it's only valid if the new word is not compressed.
382
        //
383
        reg     r_valid;
384
        always @(posedge i_clk)
385
                if (i_ce)
386
                        o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
387
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
388
                                &&(i_instruction[17:14] == o_dcdB[3:0])
389
                                &&(i_gie == o_gie)
390
                                &&((i_instruction[21:19]==o_cond[2:0])
391
                                        ||(o_cond[2:0] == 3'h0))
392
                                &&((i_instruction[13:0]==r_I[13:0])
393
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
394
        always @(posedge i_clk)
395
                if (i_rst)
396
                        r_valid <= 1'b0;
397
                else if ((i_ce)&&(i_pf_valid))
398
                        r_valid <= 1'b1;
399
                else if (~i_stalled)
400
                        r_valid <= 1'b0;
401
 
402
 
403 69 dgisselq
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
404
 
405
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.