| 1 |
209 |
dgisselq |
////////////////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//
|
| 3 |
|
|
// Filename: iscachable.v
|
| 4 |
|
|
//
|
| 5 |
|
|
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
| 6 |
|
|
//
|
| 7 |
|
|
// Purpose: A helper function to both dcache and its formal properties,
|
| 8 |
|
|
// used to determine when a particular address is cachable. This
|
| 9 |
|
|
// module must be built of entirely combinatorial logic and nothing more.
|
| 10 |
|
|
//
|
| 11 |
|
|
// Creator: Dan Gisselquist, Ph.D.
|
| 12 |
|
|
// Gisselquist Technology, LLC
|
| 13 |
|
|
//
|
| 14 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 15 |
|
|
//
|
| 16 |
|
|
// Copyright (C) 2018-2019, Gisselquist Technology, LLC
|
| 17 |
|
|
//
|
| 18 |
|
|
// This program is free software (firmware): you can redistribute it and/or
|
| 19 |
|
|
// modify it under the terms of the GNU General Public License as published
|
| 20 |
|
|
// by the Free Software Foundation, either version 3 of the License, or (at
|
| 21 |
|
|
// your option) any later version.
|
| 22 |
|
|
//
|
| 23 |
|
|
// This program is distributed in the hope that it will be useful, but WITHOUT
|
| 24 |
|
|
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
| 25 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 26 |
|
|
// for more details.
|
| 27 |
|
|
//
|
| 28 |
|
|
// License: GPL, v3, as defined and found on www.gnu.org,
|
| 29 |
|
|
// http://www.gnu.org/licenses/gpl.html
|
| 30 |
|
|
//
|
| 31 |
|
|
//
|
| 32 |
|
|
////////////////////////////////////////////////////////////////////////////////
|
| 33 |
|
|
//
|
| 34 |
|
|
//
|
| 35 |
|
|
`default_nettype none
|
| 36 |
|
|
//
|
| 37 |
|
|
module iscachable(i_addr, o_cachable);
|
| 38 |
|
|
parameter ADDRESS_WIDTH=30;
|
| 39 |
|
|
localparam AW = ADDRESS_WIDTH; // Just for ease of notation below
|
| 40 |
|
|
parameter [AW-1:0] SDRAM_ADDR = 0, SDRAM_MASK = 0;
|
| 41 |
|
|
parameter [AW-1:0] BKRAM_ADDR = 30'h4000000,
|
| 42 |
|
|
BKRAM_MASK = 30'h4000000;
|
| 43 |
|
|
parameter [AW-1:0] FLASH_ADDR = 0, FLASH_MASK = 0;
|
| 44 |
|
|
|
| 45 |
|
|
input wire [AW-1:0] i_addr;
|
| 46 |
|
|
output reg o_cachable;
|
| 47 |
|
|
|
| 48 |
|
|
|
| 49 |
|
|
always @(*)
|
| 50 |
|
|
begin
|
| 51 |
|
|
o_cachable = 1'b0;
|
| 52 |
|
|
if ((SDRAM_ADDR !=0)&&((i_addr & SDRAM_MASK)== SDRAM_ADDR))
|
| 53 |
|
|
o_cachable = 1'b1;
|
| 54 |
|
|
else if ((FLASH_ADDR !=0)&&((i_addr & FLASH_MASK)== FLASH_ADDR))
|
| 55 |
|
|
o_cachable = 1'b1;
|
| 56 |
|
|
else if ((BKRAM_ADDR !=0)&&((i_addr & BKRAM_MASK)== BKRAM_ADDR))
|
| 57 |
|
|
o_cachable = 1'b1;
|
| 58 |
|
|
end
|
| 59 |
|
|
|
| 60 |
|
|
endmodule
|
