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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    memops.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     A memory unit to support a CPU.
//
//      In the interests of code simplicity, this memory operator is
//      susceptible to unknown results should a new command be sent to it
//      before it completes the last one.  Unpredictable results might then
//      occurr.
//
//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
//              error signal).
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015,2017-2019, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype        none
//
module  memops(i_clk, i_reset, i_stb, i_lock,
                i_op, i_addr, i_data, i_oreg,
                        o_busy, o_valid, o_err, o_wreg, o_result,
                o_wb_cyc_gbl, o_wb_cyc_lcl,
                        o_wb_stb_gbl, o_wb_stb_lcl,
                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data
`ifdef  FORMAL
                , f_nreqs, f_nacks, f_outstanding
`endif
                );
        parameter       ADDRESS_WIDTH=30;
        parameter [0:0]   IMPLEMENT_LOCK=1'b1,
                        WITH_LOCAL_BUS=1'b1,
                        OPT_ALIGNMENT_ERR=1'b1,
                        OPT_ZERO_ON_IDLE=1'b0;
        localparam      AW=ADDRESS_WIDTH;
        input   wire            i_clk, i_reset;
        input   wire            i_stb, i_lock;
        // CPU interface
        input   wire    [2:0]    i_op;
        input   wire    [31:0]   i_addr;
        input   wire    [31:0]   i_data;
        input   wire    [4:0]    i_oreg;
        // CPU outputs
        output  wire            o_busy;
        output  reg             o_valid;
        output  reg             o_err;
        output  reg     [4:0]    o_wreg;
        output  reg     [31:0]   o_result;
        // Wishbone outputs
        output  wire            o_wb_cyc_gbl;
        output  reg             o_wb_stb_gbl;
        output  wire            o_wb_cyc_lcl;
        output  reg             o_wb_stb_lcl;
        output  reg             o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  reg     [31:0]   o_wb_data;
        output  reg     [3:0]    o_wb_sel;
        // Wishbone inputs
        input   wire            i_wb_ack, i_wb_stall, i_wb_err;
        input   wire    [31:0]   i_wb_data;
// Formal
        parameter       F_LGDEPTH = 2;
`ifdef  FORMAL
        output  wire    [(F_LGDEPTH-1):0]        f_nreqs, f_nacks, f_outstanding;
`endif
 
        reg     misaligned;
 
        generate if (OPT_ALIGNMENT_ERR)
        begin : GENERATE_ALIGNMENT_ERR
                always @(*)
                casez({ i_op[2:1], i_addr[1:0] })
                4'b01?1: misaligned = i_stb; // Words must be halfword aligned
                4'b0110: misaligned = i_stb; // Words must be word aligned
                4'b10?1: misaligned = i_stb; // Halfwords must be aligned
                // 4'b11??: misaligned <= 1'b0; Byte access are never misaligned
                default: misaligned = 1'b0;
                endcase
        end else
                always @(*)     misaligned = 1'b0;
        endgenerate
 
        reg     r_wb_cyc_gbl, r_wb_cyc_lcl;
        wire    gbl_stb, lcl_stb;
        assign  lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff)
                                &&(!misaligned);
        assign  gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)||(i_addr[31:24]!=8'hff))
                                &&(!misaligned);
 
        initial r_wb_cyc_gbl = 1'b0;
        initial r_wb_cyc_lcl = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
        begin
                r_wb_cyc_gbl <= 1'b0;
                r_wb_cyc_lcl <= 1'b0;
        end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
        begin
                if ((i_wb_ack)||(i_wb_err))
                begin
                        r_wb_cyc_gbl <= 1'b0;
                        r_wb_cyc_lcl <= 1'b0;
                end
        end else begin // New memory operation
                // Grab the wishbone
                r_wb_cyc_lcl <= (lcl_stb);
                r_wb_cyc_gbl <= (gbl_stb);
        end
        initial o_wb_stb_gbl = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
                o_wb_stb_gbl <= 1'b0;
        else if ((i_wb_err)&&(r_wb_cyc_gbl))
                o_wb_stb_gbl <= 1'b0;
        else if (o_wb_cyc_gbl)
                o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
        else
                // Grab wishbone on any new transaction to the gbl bus
                o_wb_stb_gbl <= (gbl_stb);
 
        initial o_wb_stb_lcl = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
                o_wb_stb_lcl <= 1'b0;
        else if ((i_wb_err)&&(r_wb_cyc_lcl))
                o_wb_stb_lcl <= 1'b0;
        else if (o_wb_cyc_lcl)
                o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
        else
                // Grab wishbone on any new transaction to the lcl bus
                o_wb_stb_lcl  <= (lcl_stb);
 
        reg     [3:0]    r_op;
        initial o_wb_we   = 1'b0;
        initial o_wb_data = 0;
        initial o_wb_sel  = 0;
        always @(posedge i_clk)
        if (i_stb)
        begin
                o_wb_we   <= i_op[0];
                if (OPT_ZERO_ON_IDLE)
                begin
                        casez({ i_op[2:1], i_addr[1:0] })
                        4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
                        4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
                        4'b1100: o_wb_data <= {         i_data[7:0], 24'h00 };
                        4'b1101: o_wb_data <= {  8'h00, i_data[7:0], 16'h00 };
                        4'b1110: o_wb_data <= { 16'h00, i_data[7:0],  8'h00 };
                        4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
                        default: o_wb_data <= i_data;
                        endcase
                end else
                        casez({ i_op[2:1], i_addr[1:0] })
                        4'b10??: o_wb_data <= { (2){ i_data[15:0] } };
                        4'b11??: o_wb_data <= { (4){ i_data[7:0] } };
                        default: o_wb_data <= i_data;
                        endcase
 
                o_wb_addr <= i_addr[(AW+1):2];
                casez({ i_op[2:1], i_addr[1:0] })
                4'b01??: o_wb_sel <= 4'b1111;
                4'b100?: o_wb_sel <= 4'b1100;
                4'b101?: o_wb_sel <= 4'b0011;
                4'b1100: o_wb_sel <= 4'b1000;
                4'b1101: o_wb_sel <= 4'b0100;
                4'b1110: o_wb_sel <= 4'b0010;
                4'b1111: o_wb_sel <= 4'b0001;
                default: o_wb_sel <= 4'b1111;
                endcase
                r_op <= { i_op[2:1] , i_addr[1:0] };
        end else if ((OPT_ZERO_ON_IDLE)&&(!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl))
        begin
                o_wb_we   <= 1'b0;
                o_wb_addr <= 0;
                o_wb_data <= 32'h0;
                o_wb_sel  <= 4'h0;
        end
 
        initial o_valid = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
                o_valid <= 1'b0;
        else
                o_valid <= (((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
                                &&(i_wb_ack)&&(!o_wb_we));
        initial o_err = 1'b0;
        always @(posedge i_clk)
        if (i_reset)
                o_err <= 1'b0;
        else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
                o_err <= i_wb_err;
        else if ((i_stb)&&(!o_busy))
                o_err <= misaligned;
        else
                o_err <= 1'b0;
 
        assign  o_busy = (r_wb_cyc_gbl)||(r_wb_cyc_lcl);
 
        always @(posedge i_clk)
        if (i_stb)
                o_wreg    <= i_oreg;
        always @(posedge i_clk)
        if ((OPT_ZERO_ON_IDLE)&&(!i_wb_ack))
                o_result <= 32'h0;
        else begin
                casez(r_op)
                4'b01??: o_result <= i_wb_data;
                4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };
                4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };
                4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };
                4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };
                4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };
                4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };
                default: o_result <= i_wb_data;
                endcase
        end
 
        reg     lock_gbl, lock_lcl;
 
        generate
        if (IMPLEMENT_LOCK != 0)
        begin
 
                initial lock_gbl = 1'b0;
                initial lock_lcl = 1'b0;
 
                always @(posedge i_clk)
                if (i_reset)
                begin
                        lock_gbl <= 1'b0;
                        lock_lcl <= 1'b0;
                end else if (((i_wb_err)&&((r_wb_cyc_gbl)||(r_wb_cyc_lcl)))
                                ||(misaligned))
                begin
                        // Kill the lock if
                        //      there's a bus error, or
                        //      User requests a misaligned memory op
                        lock_gbl <= 1'b0;
                        lock_lcl <= 1'b0;
                end else begin
                        // Kill the lock if
                        //      i_lock goes down
                        //      User starts on the global bus, then switches
                        //        to local or vice versa
                        lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl))
                                        &&(!lcl_stb);
                        lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl))
                                        &&(!gbl_stb);
                end
 
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
        end else begin
 
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl);
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl);
 
                always @(*)
                        { lock_gbl, lock_lcl } = 2'b00;
 
                // Make verilator happy
                // verilator lint_off UNUSED
                wire    [2:0]    lock_unused;
                assign  lock_unused = { i_lock, lock_gbl, lock_lcl };
                // verilator lint_on  UNUSED
 
        end endgenerate
 
`ifdef  VERILATOR
        always @(posedge i_clk)
        if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
                assert(!i_stb);
`endif
 
 
        // Make verilator happy
        // verilator lint_off UNUSED
        generate if (AW < 22)
        begin : TOO_MANY_ADDRESS_BITS
 
                wire    [(21-AW):0] unused_addr;
                assign  unused_addr = i_addr[23:(AW+2)];
 
        end endgenerate
        // verilator lint_on  UNUSED
 
`ifdef  FORMAL
`define ASSERT  assert
`ifdef  MEMOPS
`define ASSUME  assume
`else
`define ASSUME  assert
`endif
 
        reg     f_past_valid;
        initial f_past_valid = 0;
        always @(posedge i_clk)
                f_past_valid = 1'b1;
        always @(*)
                if (!f_past_valid)
                        `ASSUME(i_reset);
        initial `ASSUME(!i_stb);
 
        wire    f_cyc, f_stb;
        assign  f_cyc = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
        assign  f_stb = (o_wb_stb_gbl)||(o_wb_stb_lcl);
 
`ifdef  MEMOPS
`define MASTER  fwb_master
`else
`define MASTER  fwb_counter
`endif
 
        fwb_master #(.AW(AW), .F_LGDEPTH(F_LGDEPTH),
                        .F_OPT_RMW_BUS_OPTION(IMPLEMENT_LOCK),
                        .F_OPT_DISCONTINUOUS(IMPLEMENT_LOCK))
                f_wb(i_clk, i_reset,
                        f_cyc, f_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
                        f_nreqs, f_nacks, f_outstanding);
 
 
        // Rule: Only one of the two CYC's may be valid, never both
        always @(posedge i_clk)
                `ASSERT((!o_wb_cyc_gbl)||(!o_wb_cyc_lcl));
 
        // Rule: Only one of the two STB's may be valid, never both
        always @(posedge i_clk)
                `ASSERT((!o_wb_stb_gbl)||(!o_wb_stb_lcl));
 
        // Rule: if WITH_LOCAL_BUS is ever false, neither the local STB nor CYC
        // may be valid
        always @(*)
                if (!WITH_LOCAL_BUS)
                begin
                        `ASSERT(!o_wb_cyc_lcl);
                        `ASSERT(!o_wb_stb_lcl);
                end
 
        // Rule: If the global CYC is ever true, the LCL one cannot be true
        // on the next clock without an intervening idle of both
        always @(posedge i_clk)
                if ((f_past_valid)&&($past(r_wb_cyc_gbl)))
                        `ASSERT(!r_wb_cyc_lcl);
 
        // Same for if the LCL CYC is true
        always @(posedge i_clk)
                if ((f_past_valid)&&($past(r_wb_cyc_lcl)))
                        `ASSERT(!r_wb_cyc_gbl);
 
        // STB can never be true unless CYC is also true
        always @(posedge i_clk)
                if (o_wb_stb_gbl)
                        `ASSERT(r_wb_cyc_gbl);
        always @(posedge i_clk)
                if (o_wb_stb_lcl)
                        `ASSERT(r_wb_cyc_lcl);
 
        // This core only ever has zero or one outstanding transaction(s)
        always @(posedge i_clk)
                if ((o_wb_stb_gbl)||(o_wb_stb_lcl))
                        `ASSERT(f_outstanding == 0);
                else
                        `ASSERT((f_outstanding == 0)||(f_outstanding == 1));
 
        // The LOCK function only allows up to two transactions (at most)
        // before CYC must be dropped.
        always @(posedge i_clk)
                if ((o_wb_stb_gbl)||(o_wb_stb_lcl))
                begin
                        if (IMPLEMENT_LOCK)
                                `ASSERT((f_outstanding == 0)||(f_outstanding == 1));
                        else
                                `ASSERT(f_nreqs <= 1);
                end
 
        always @(posedge i_clk)
        if ((f_past_valid)&&(o_busy))
        begin
 
                // If i_stb doesn't change, then neither do any of the other
                // inputs
                if (($past(i_stb))&&(i_stb))
                begin
                        `ASSUME($stable(i_op));
                        `ASSUME($stable(i_addr));
                        `ASSUME($stable(i_data));
                        `ASSUME($stable(i_oreg));
                        `ASSUME($stable(i_lock));
                end
 
 
                // No strobe's are allowed if a request is outstanding, either
                // having been accepted by the bus or waiting to be accepted
                // by the bus.
                if ((f_outstanding != 0)||(f_stb))
                        `ASSUME(!i_stb);
                /*
                if (o_busy)
                        assert( (!i_stb)
                                ||((!o_wb_stb_gbl)&&(!o_wb_stb_lcl)&&(i_lock)));
 
                if ((f_cyc)&&($past(f_cyc)))
                        assert($stable(r_op));
                */
        end
 
        always @(*)
                if (!IMPLEMENT_LOCK)
                        `ASSUME(!i_lock);
 
        always @(posedge i_clk)
                if ((f_past_valid)&&($past(f_cyc))&&($past(!i_lock)))
                        `ASSUME(!i_lock);
 
        // Following any i_stb request, assuming we are idle, immediately
        // begin a bus transaction
        always @(posedge i_clk)
        if ((f_past_valid)&&($past(i_stb))
                &&(!$past(f_cyc))&&(!$past(i_reset)))
        begin
                if ($past(misaligned))
                begin
                        `ASSERT(!f_cyc);
                        `ASSERT(!o_busy);
                        `ASSERT(o_err);
                        `ASSERT(!o_valid);
                end else begin
                        `ASSERT(f_cyc);
                        `ASSERT(o_busy);
                end
        end
 
        always @(posedge i_clk)
        if (o_busy)
                `ASSUME(!i_stb);
 
        always @(posedge i_clk)
        if (o_wb_cyc_gbl)
                `ASSERT((o_busy)||(lock_gbl));
 
        always @(posedge i_clk)
        if (o_wb_cyc_lcl)
                `ASSERT((o_busy)||(lock_lcl));
 
        always @(posedge i_clk)
                if (f_outstanding > 0)
                        `ASSERT(o_busy);
 
        // If a transaction ends in an error, send o_err on the output port.
        always @(posedge i_clk)
                if (f_past_valid)
                begin
                        if ($past(i_reset))
                                `ASSERT(!o_err);
                        else if (($past(f_cyc))&&($past(i_wb_err)))
                                `ASSERT(o_err);
                        else if ($past(misaligned))
                                `ASSERT(o_err);
                end
 
        // Always following a successful ACK, return an O_VALID value.
        always @(posedge i_clk)
                if (f_past_valid)
                begin
                        if ($past(i_reset))
                                `ASSERT(!o_valid);
                        else if(($past(f_cyc))&&($past(i_wb_ack))
                                        &&(!$past(o_wb_we)))
                                `ASSERT(o_valid);
                        else if ($past(misaligned))
                                `ASSERT((!o_valid)&&(o_err));
                        else
                                `ASSERT(!o_valid);
                end
 
        //always @(posedge i_clk)
        //      if ((f_past_valid)&&($past(f_cyc))&&(!$past(o_wb_we))&&($past(i_wb_ack)))
 
        /*
        input   wire    [2:0]   i_op;
        input   wire    [31:0]  i_addr;
        input   wire    [31:0]  i_data;
        input   wire    [4:0]   i_oreg;
        // CPU outputs
        output  wire            o_busy;
        output  reg             o_valid;
        output  reg             o_err;
        output  reg     [4:0]   o_wreg;
        output  reg     [31:0]  o_result;
        */
 
        initial o_wb_we = 1'b0;
        always @(posedge i_clk)
        if ((f_past_valid)&&(!$past(i_reset))&&($past(i_stb)))
        begin
                // On a write, assert o_wb_we should be true
                assert( $past(i_op[0]) == o_wb_we);
 
                // Word write
                if ($past(i_op[2:1]) == 2'b01)
                begin
                        `ASSERT(o_wb_sel == 4'hf);
                        `ASSERT(o_wb_data == $past(i_data));
                end
 
                // Halfword (short) write
                if ($past(i_op[2:1]) == 2'b10)
                begin
                        if (!$past(i_addr[1]))
                        begin
                                `ASSERT(o_wb_sel == 4'hc);
                                `ASSERT(o_wb_data[31:16] == $past(i_data[15:0]));
                        end else begin
                                `ASSERT(o_wb_sel == 4'h3);
                                `ASSERT(o_wb_data[15:0] == $past(i_data[15:0]));
                        end
                end
 
                if ($past(i_op[2:1]) == 2'b11)
                begin
                        if ($past(i_addr[1:0])==2'b00)
                        begin
                                `ASSERT(o_wb_sel == 4'h8);
                                `ASSERT(o_wb_data[31:24] == $past(i_data[7:0]));
                        end
 
                        if ($past(i_addr[1:0])==2'b01)
                        begin
                                `ASSERT(o_wb_sel == 4'h4);
                                `ASSERT(o_wb_data[23:16] == $past(i_data[7:0]));
                        end
                        if ($past(i_addr[1:0])==2'b10)
                        begin
                                `ASSERT(o_wb_sel == 4'h2);
                                `ASSERT(o_wb_data[15:8] == $past(i_data[7:0]));
                        end
                        if ($past(i_addr[1:0])==2'b11)
                        begin
                                `ASSERT(o_wb_sel == 4'h1);
                                `ASSERT(o_wb_data[7:0] == $past(i_data[7:0]));
                        end
                end
 
                `ASSUME($past(i_op[2:1] != 2'b00));
        end
 
        // This logic is fixed in the definitions of the lock(s) above
        // i.e., the user cna be stupid and this will still work
        /*
        always @(posedge i_clk)
                if ((i_lock)&&(i_stb)&&(WITH_LOCAL_BUS))
                begin
                        restrict((lock_gbl)||(i_addr[31:24] ==8'hff));
                        restrict((lock_lcl)||(i_addr[31:24]!==8'hff));
                end
        */
 
        always @(posedge i_clk)
                if (o_wb_stb_lcl)
                        `ASSERT(o_wb_addr[29:22] == 8'hff);
 
        always @(posedge i_clk)
                if ((f_past_valid)&&(!$past(i_reset))&&($past(misaligned)))
                begin
                        `ASSERT(!o_wb_cyc_gbl);
                        `ASSERT(!o_wb_cyc_lcl);
                        `ASSERT(!o_wb_stb_gbl);
                        `ASSERT(!o_wb_stb_lcl);
                        `ASSERT(o_err);
                        //OPT_ALIGNMENT_ERR=1'b0,
                        //OPT_ZERO_ON_IDLE=1'b0;
                end
 
        always @(posedge i_clk)
        if ((!f_past_valid)||($past(i_reset)))
                `ASSUME(!i_stb);
        always @(*)
        if (o_busy)
                `ASSUME(!i_stb);
 
        always @(posedge i_clk)
        if ((f_past_valid)&&(IMPLEMENT_LOCK)
                &&(!$past(i_reset))&&(!$past(i_wb_err))
                &&(!$past(misaligned))
                &&(!$past(lcl_stb))
                &&($past(i_lock))&&($past(lock_gbl)))
                assert(lock_gbl);
 
        always @(posedge i_clk)
        if ((f_past_valid)&&(IMPLEMENT_LOCK)
                        &&(!$past(i_reset))&&(!$past(i_wb_err))
                        &&(!$past(misaligned))
                        &&(!$past(lcl_stb))
                        &&($past(o_wb_cyc_gbl))&&($past(i_lock))
                        &&($past(lock_gbl)))
                assert(o_wb_cyc_gbl);
 
        always @(posedge i_clk)
        if ((f_past_valid)&&(IMPLEMENT_LOCK)
                        &&(!$past(i_reset))&&(!$past(i_wb_err))
                        &&(!$past(misaligned))
                        &&(!$past(gbl_stb))
                        &&($past(o_wb_cyc_lcl))&&($past(i_lock))
                        &&($past(lock_lcl)))
                assert(o_wb_cyc_lcl);
 
        //
        // Cover properties
        //
        always @(posedge i_clk)
                cover(i_wb_ack);
 
        // Cover a response on the same clock it is made
        always @(posedge i_clk)
                cover((o_wb_stb_gbl)&&(i_wb_ack));
 
        // Cover a response a clock later
        always @(posedge i_clk)
                cover((o_wb_stb_gbl)&&(i_wb_ack));
 
 
        generate if (WITH_LOCAL_BUS)
        begin
 
                // Same things on the local bus
                always @(posedge i_clk)
                        cover((o_wb_cyc_lcl)&&(!o_wb_stb_lcl)&&(i_wb_ack));
                always @(posedge i_clk)
                        cover((o_wb_stb_lcl)&&(i_wb_ack));
 
        end endgenerate
 
`endif
endmodule
//
//
// Usage (from yosys):
//              (BFOR)  (!ZOI,ALIGN)    (ZOI,ALIGN)     (!ZOI,!ALIGN)
//      Cells    230            226             281             225
//        FDRE   114            116             116             116
//        LUT2    17             23              76              19
//        LUT3     9             23              17              20
//        LUT4    15              4              11              14
//        LUT5    18             18               7              15
//        LUT6    33             18              54              38
//        MUX7    16             12                               2
//        MUX8     8              1                               1
//
//

Line No.	Rev	Author	Line
1	201	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2	3	dgisselq	`//`
3			`// Filename: memops.v`
4			`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7			`// Purpose: A memory unit to support a CPU.`
8			`//`
9	209	dgisselq	`// In the interests of code simplicity, this memory operator is`
10	3	dgisselq	`// susceptible to unknown results should a new command be sent to it`
11			`// before it completes the last one. Unpredictable results might then`
12			`// occurr.`
13			`//`
14	36	dgisselq	`// 20150919 -- Added support for handling BUS ERR's (i.e., the WB`
15			`// error signal).`
16			`//`
17	3	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
18	69	dgisselq	`// Gisselquist Technology, LLC`
19	3	dgisselq	`//`
20	201	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
21	3	dgisselq	`//`
22	209	dgisselq	`// Copyright (C) 2015,2017-2019, Gisselquist Technology, LLC`
23	3	dgisselq	`//`
24			`// This program is free software (firmware): you can redistribute it and/or`
25			`// modify it under the terms of the GNU General Public License as published`
26			`// by the Free Software Foundation, either version 3 of the License, or (at`
27			`// your option) any later version.`
28			`//`
29			`// This program is distributed in the hope that it will be useful, but WITHOUT`
30			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
31			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
32			`// for more details.`
33			`//`
34	201	dgisselq	`// You should have received a copy of the GNU General Public License along`
35			`// with this program. (It's in the $(ROOT)/doc directory. Run make with no`
36			`// target there if the PDF file isn't present.) If not, see`
37			`// <http://www.gnu.org/licenses/> for a copy.`
38			`//`
39	3	dgisselq	`// License: GPL, v3, as defined and found on www.gnu.org,`
40			`// http://www.gnu.org/licenses/gpl.html`
41			`//`
42			`//`
43	201	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
44	3	dgisselq	`//`
45	201	dgisselq	`//`
46	209	dgisselq	`default_nettype none
47			`//`
48			`module memops(i_clk, i_reset, i_stb, i_lock,`
49	2	dgisselq	`i_op, i_addr, i_data, i_oreg,`
50	36	dgisselq	`o_busy, o_valid, o_err, o_wreg, o_result,`
51			`o_wb_cyc_gbl, o_wb_cyc_lcl,`
52			`o_wb_stb_gbl, o_wb_stb_lcl,`
53	201	dgisselq	`o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,`
54	209	dgisselq	`i_wb_ack, i_wb_stall, i_wb_err, i_wb_data`
55			`ifdef FORMAL
56			`, f_nreqs, f_nacks, f_outstanding`
57			`endif
58			`);`
59			`parameter ADDRESS_WIDTH=30;`
60			`parameter [0:0] IMPLEMENT_LOCK=1'b1,`
61			`WITH_LOCAL_BUS=1'b1,`
62			`OPT_ALIGNMENT_ERR=1'b1,`
63			`OPT_ZERO_ON_IDLE=1'b0;`
64	201	dgisselq	`localparam AW=ADDRESS_WIDTH;`
65	209	dgisselq	`input wire i_clk, i_reset;`
66			`input wire i_stb, i_lock;`
67	2	dgisselq	`// CPU interface`
68	209	dgisselq	`input wire [2:0] i_op;`
69			`input wire [31:0] i_addr;`
70			`input wire [31:0] i_data;`
71			`input wire [4:0] i_oreg;`
72	2	dgisselq	`// CPU outputs`
73			`output wire o_busy;`
74			`output reg o_valid;`
75	36	dgisselq	`output reg o_err;`
76	2	dgisselq	`output reg [4:0] o_wreg;`
77			`output reg [31:0] o_result;`
78			`// Wishbone outputs`
79	69	dgisselq	`output wire o_wb_cyc_gbl;`
80			`output reg o_wb_stb_gbl;`
81			`output wire o_wb_cyc_lcl;`
82			`output reg o_wb_stb_lcl;`
83			`output reg o_wb_we;`
84	48	dgisselq	`output reg [(AW-1):0] o_wb_addr;`
85			`output reg [31:0] o_wb_data;`
86	201	dgisselq	`output reg [3:0] o_wb_sel;`
87	2	dgisselq	`// Wishbone inputs`
88	209	dgisselq	`input wire i_wb_ack, i_wb_stall, i_wb_err;`
89			`input wire [31:0] i_wb_data;`
90			`// Formal`
91			`parameter F_LGDEPTH = 2;`
92			`ifdef FORMAL
93			`output wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding;`
94			`endif
95	2	dgisselq
96	209	dgisselq	`reg misaligned;`
97
98			`generate if (OPT_ALIGNMENT_ERR)`
99			`begin : GENERATE_ALIGNMENT_ERR`
100			`always @(*)`
101			`casez({ i_op[2:1], i_addr[1:0] })`
102			`4'b01?1: misaligned = i_stb; // Words must be halfword aligned`
103			`4'b0110: misaligned = i_stb; // Words must be word aligned`
104			`4'b10?1: misaligned = i_stb; // Halfwords must be aligned`
105			`// 4'b11??: misaligned <= 1'b0; Byte access are never misaligned`
106			`default: misaligned = 1'b0;`
107			`endcase`
108			`end else`
109			`always @(*) misaligned = 1'b0;`
110			`endgenerate`
111
112	69	dgisselq	`reg r_wb_cyc_gbl, r_wb_cyc_lcl;`
113	36	dgisselq	`wire gbl_stb, lcl_stb;`
114	209	dgisselq	`assign lcl_stb = (i_stb)&&(WITH_LOCAL_BUS!=0)&&(i_addr[31:24]==8'hff)`
115			`&&(!misaligned);`
116			`assign gbl_stb = (i_stb)&&((WITH_LOCAL_BUS==0)\|\|(i_addr[31:24]!=8'hff))`
117			`&&(!misaligned);`
118	36	dgisselq
119	69	dgisselq	`initial r_wb_cyc_gbl = 1'b0;`
120			`initial r_wb_cyc_lcl = 1'b0;`
121	2	dgisselq	`always @(posedge i_clk)`
122	209	dgisselq	`if (i_reset)`
123			`begin`
124			`r_wb_cyc_gbl <= 1'b0;`
125			`r_wb_cyc_lcl <= 1'b0;`
126			`end else if ((r_wb_cyc_gbl)\|\|(r_wb_cyc_lcl))`
127			`begin`
128			`if ((i_wb_ack)\|\|(i_wb_err))`
129	36	dgisselq	`begin`
130	69	dgisselq	`r_wb_cyc_gbl <= 1'b0;`
131			`r_wb_cyc_lcl <= 1'b0;`
132	36	dgisselq	`end`
133	209	dgisselq	`end else begin // New memory operation`
134			`// Grab the wishbone`
135			`r_wb_cyc_lcl <= (lcl_stb);`
136			`r_wb_cyc_gbl <= (gbl_stb);`
137			`end`
138			`initial o_wb_stb_gbl = 1'b0;`
139	3	dgisselq	`always @(posedge i_clk)`
140	209	dgisselq	`if (i_reset)`
141			`o_wb_stb_gbl <= 1'b0;`
142			`else if ((i_wb_err)&&(r_wb_cyc_gbl))`
143			`o_wb_stb_gbl <= 1'b0;`
144			`else if (o_wb_cyc_gbl)`
145			`o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);`
146			`else`
147			`// Grab wishbone on any new transaction to the gbl bus`
148			`o_wb_stb_gbl <= (gbl_stb);`
149
150			`initial o_wb_stb_lcl = 1'b0;`
151	3	dgisselq	`always @(posedge i_clk)`
152	209	dgisselq	`if (i_reset)`
153			`o_wb_stb_lcl <= 1'b0;`
154			`else if ((i_wb_err)&&(r_wb_cyc_lcl))`
155			`o_wb_stb_lcl <= 1'b0;`
156			`else if (o_wb_cyc_lcl)`
157			`o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);`
158			`else`
159			`// Grab wishbone on any new transaction to the lcl bus`
160			`o_wb_stb_lcl <= (lcl_stb);`
161	201	dgisselq
162			`reg [3:0] r_op;`
163	209	dgisselq	`initial o_wb_we = 1'b0;`
164			`initial o_wb_data = 0;`
165			`initial o_wb_sel = 0;`
166	36	dgisselq	`always @(posedge i_clk)`
167	209	dgisselq	`if (i_stb)`
168			`begin`
169			`o_wb_we <= i_op[0];`
170			`if (OPT_ZERO_ON_IDLE)`
171	3	dgisselq	`begin`
172	201	dgisselq	`casez({ i_op[2:1], i_addr[1:0] })`
173			`4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };`
174			`4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };`
175			`4'b1100: o_wb_data <= { i_data[7:0], 24'h00 };`
176			`4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 };`
177			`4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 };`
178			`4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };`
179	209	dgisselq	`default: o_wb_data <= i_data;`
180			`endcase`
181			`end else`
182			`casez({ i_op[2:1], i_addr[1:0] })`
183	201	dgisselq	`4'b10??: o_wb_data <= { (2){ i_data[15:0] } };`
184			`4'b11??: o_wb_data <= { (4){ i_data[7:0] } };`
185			`default: o_wb_data <= i_data;`
186			`endcase`
187
188	209	dgisselq	`o_wb_addr <= i_addr[(AW+1):2];`
189			`casez({ i_op[2:1], i_addr[1:0] })`
190			`4'b01??: o_wb_sel <= 4'b1111;`
191			`4'b100?: o_wb_sel <= 4'b1100;`
192			`4'b101?: o_wb_sel <= 4'b0011;`
193			`4'b1100: o_wb_sel <= 4'b1000;`
194			`4'b1101: o_wb_sel <= 4'b0100;`
195			`4'b1110: o_wb_sel <= 4'b0010;`
196			`4'b1111: o_wb_sel <= 4'b0001;`
197			`default: o_wb_sel <= 4'b1111;`
198			`endcase`
199			`r_op <= { i_op[2:1] , i_addr[1:0] };`
200			`end else if ((OPT_ZERO_ON_IDLE)&&(!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl))`
201			`begin`
202			`o_wb_we <= 1'b0;`
203			`o_wb_addr <= 0;`
204			`o_wb_data <= 32'h0;`
205			`o_wb_sel <= 4'h0;`
206			`end`
207	2	dgisselq
208			`initial o_valid = 1'b0;`
209			`always @(posedge i_clk)`
210	209	dgisselq	`if (i_reset)`
211			`o_valid <= 1'b0;`
212			`else`
213			`o_valid <= (((o_wb_cyc_gbl)\|\|(o_wb_cyc_lcl))`
214			`&&(i_wb_ack)&&(!o_wb_we));`
215	36	dgisselq	`initial o_err = 1'b0;`
216			`always @(posedge i_clk)`
217	209	dgisselq	`if (i_reset)`
218			`o_err <= 1'b0;`
219			`else if ((r_wb_cyc_gbl)\|\|(r_wb_cyc_lcl))`
220			`o_err <= i_wb_err;`
221			`else if ((i_stb)&&(!o_busy))`
222			`o_err <= misaligned;`
223			`else`
224			`o_err <= 1'b0;`
225	2	dgisselq
226	209	dgisselq	`assign o_busy = (r_wb_cyc_gbl)\|\|(r_wb_cyc_lcl);`
227
228	2	dgisselq	`always @(posedge i_clk)`
229	209	dgisselq	`if (i_stb)`
230			`o_wreg <= i_oreg;`
231	2	dgisselq	`always @(posedge i_clk)`
232	209	dgisselq	`if ((OPT_ZERO_ON_IDLE)&&(!i_wb_ack))`
233			`o_result <= 32'h0;`
234			`else begin`
235	201	dgisselq	`casez(r_op)`
236			`4'b01??: o_result <= i_wb_data;`
237			`4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };`
238			`4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };`
239			`4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };`
240			`4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };`
241			`4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };`
242			`4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };`
243			`default: o_result <= i_wb_data;`
244			`endcase`
245	209	dgisselq	`end`
246	69	dgisselq
247	209	dgisselq	`reg lock_gbl, lock_lcl;`
248
249	69	dgisselq	`generate`
250			`if (IMPLEMENT_LOCK != 0)`
251			`begin`
252
253			`initial lock_gbl = 1'b0;`
254			`initial lock_lcl = 1'b0;`
255
256			`always @(posedge i_clk)`
257	209	dgisselq	`if (i_reset)`
258	69	dgisselq	`begin`
259	209	dgisselq	`lock_gbl <= 1'b0;`
260			`lock_lcl <= 1'b0;`
261			`end else if (((i_wb_err)&&((r_wb_cyc_gbl)\|\|(r_wb_cyc_lcl)))`
262			`\|\|(misaligned))`
263			`begin`
264			`// Kill the lock if`
265			`// there's a bus error, or`
266			`// User requests a misaligned memory op`
267			`lock_gbl <= 1'b0;`
268			`lock_lcl <= 1'b0;`
269			`end else begin`
270			`// Kill the lock if`
271			`// i_lock goes down`
272			`// User starts on the global bus, then switches`
273			`// to local or vice versa`
274			`lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)\|\|(lock_gbl))`
275			`&&(!lcl_stb);`
276			`lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)\|\|(lock_lcl))`
277			`&&(!gbl_stb);`
278	69	dgisselq	`end`
279
280			`assign o_wb_cyc_gbl = (r_wb_cyc_gbl)\|\|(lock_gbl);`
281			`assign o_wb_cyc_lcl = (r_wb_cyc_lcl)\|\|(lock_lcl);`
282			`end else begin`
283	209	dgisselq
284	69	dgisselq	`assign o_wb_cyc_gbl = (r_wb_cyc_gbl);`
285			`assign o_wb_cyc_lcl = (r_wb_cyc_lcl);`
286	209	dgisselq
287			`always @(*)`
288			`{ lock_gbl, lock_lcl } = 2'b00;`
289
290			`// Make verilator happy`
291			`// verilator lint_off UNUSED`
292			`wire [2:0] lock_unused;`
293			`assign lock_unused = { i_lock, lock_gbl, lock_lcl };`
294			`// verilator lint_on UNUSED`
295
296	69	dgisselq	`end endgenerate`
297	209	dgisselq
298			`ifdef VERILATOR
299			`always @(posedge i_clk)`
300			`if ((r_wb_cyc_gbl)\|\|(r_wb_cyc_lcl))`
301			`assert(!i_stb);`
302			`endif
303
304
305			`// Make verilator happy`
306			`// verilator lint_off UNUSED`
307			`generate if (AW < 22)`
308			`begin : TOO_MANY_ADDRESS_BITS`
309
310			`wire [(21-AW):0] unused_addr;`
311			`assign unused_addr = i_addr[23:(AW+2)];`
312
313			`end endgenerate`
314			`// verilator lint_on UNUSED`
315
316			`ifdef FORMAL
317			`define ASSERT assert
318			`ifdef MEMOPS
319			`define ASSUME assume
320			`else
321			`define ASSUME assert
322			`endif
323
324			`reg f_past_valid;`
325			`initial f_past_valid = 0;`
326			`always @(posedge i_clk)`
327			`f_past_valid = 1'b1;`
328			`always @(*)`
329			`if (!f_past_valid)`
330			`ASSUME(i_reset);
331			initial `ASSUME(!i_stb);
332
333			`wire f_cyc, f_stb;`
334			`assign f_cyc = (o_wb_cyc_gbl)\|\|(o_wb_cyc_lcl);`
335			`assign f_stb = (o_wb_stb_gbl)\|\|(o_wb_stb_lcl);`
336
337			`ifdef MEMOPS
338			`define MASTER fwb_master
339			`else
340			`define MASTER fwb_counter
341			`endif
342
343			`fwb_master #(.AW(AW), .F_LGDEPTH(F_LGDEPTH),`
344			`.F_OPT_RMW_BUS_OPTION(IMPLEMENT_LOCK),`
345			`.F_OPT_DISCONTINUOUS(IMPLEMENT_LOCK))`
346			`f_wb(i_clk, i_reset,`
347			`f_cyc, f_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,`
348			`i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,`
349			`f_nreqs, f_nacks, f_outstanding);`
350
351
352			`// Rule: Only one of the two CYC's may be valid, never both`
353			`always @(posedge i_clk)`
354			`ASSERT((!o_wb_cyc_gbl)\|\|(!o_wb_cyc_lcl));
355
356			`// Rule: Only one of the two STB's may be valid, never both`
357			`always @(posedge i_clk)`
358			`ASSERT((!o_wb_stb_gbl)\|\|(!o_wb_stb_lcl));
359
360			`// Rule: if WITH_LOCAL_BUS is ever false, neither the local STB nor CYC`
361			`// may be valid`
362			`always @(*)`
363			`if (!WITH_LOCAL_BUS)`
364			`begin`
365			`ASSERT(!o_wb_cyc_lcl);
366			`ASSERT(!o_wb_stb_lcl);
367			`end`
368
369			`// Rule: If the global CYC is ever true, the LCL one cannot be true`
370			`// on the next clock without an intervening idle of both`
371			`always @(posedge i_clk)`
372			`if ((f_past_valid)&&($past(r_wb_cyc_gbl)))`
373			`ASSERT(!r_wb_cyc_lcl);
374
375			`// Same for if the LCL CYC is true`
376			`always @(posedge i_clk)`
377			`if ((f_past_valid)&&($past(r_wb_cyc_lcl)))`
378			`ASSERT(!r_wb_cyc_gbl);
379
380			`// STB can never be true unless CYC is also true`
381			`always @(posedge i_clk)`
382			`if (o_wb_stb_gbl)`
383			`ASSERT(r_wb_cyc_gbl);
384			`always @(posedge i_clk)`
385			`if (o_wb_stb_lcl)`
386			`ASSERT(r_wb_cyc_lcl);
387
388			`// This core only ever has zero or one outstanding transaction(s)`
389			`always @(posedge i_clk)`
390			`if ((o_wb_stb_gbl)\|\|(o_wb_stb_lcl))`
391			`ASSERT(f_outstanding == 0);
392			`else`
393			`ASSERT((f_outstanding == 0)\|\|(f_outstanding == 1));
394
395			`// The LOCK function only allows up to two transactions (at most)`
396			`// before CYC must be dropped.`
397			`always @(posedge i_clk)`
398			`if ((o_wb_stb_gbl)\|\|(o_wb_stb_lcl))`
399			`begin`
400			`if (IMPLEMENT_LOCK)`
401			`ASSERT((f_outstanding == 0)\|\|(f_outstanding == 1));
402			`else`
403			`ASSERT(f_nreqs <= 1);
404			`end`
405
406			`always @(posedge i_clk)`
407			`if ((f_past_valid)&&(o_busy))`
408			`begin`
409
410			`// If i_stb doesn't change, then neither do any of the other`
411			`// inputs`
412			`if (($past(i_stb))&&(i_stb))`
413			`begin`
414			`ASSUME($stable(i_op));
415			`ASSUME($stable(i_addr));
416			`ASSUME($stable(i_data));
417			`ASSUME($stable(i_oreg));
418			`ASSUME($stable(i_lock));
419			`end`
420
421
422			`// No strobe's are allowed if a request is outstanding, either`
423			`// having been accepted by the bus or waiting to be accepted`
424			`// by the bus.`
425			`if ((f_outstanding != 0)\|\|(f_stb))`
426			`ASSUME(!i_stb);
427			`/*`
428			`if (o_busy)`
429			`assert( (!i_stb)`
430			`\|\|((!o_wb_stb_gbl)&&(!o_wb_stb_lcl)&&(i_lock)));`
431
432			`if ((f_cyc)&&($past(f_cyc)))`
433			`assert($stable(r_op));`
434			`*/`
435			`end`
436
437			`always @(*)`
438			`if (!IMPLEMENT_LOCK)`
439			`ASSUME(!i_lock);
440
441			`always @(posedge i_clk)`
442			`if ((f_past_valid)&&($past(f_cyc))&&($past(!i_lock)))`
443			`ASSUME(!i_lock);
444
445			`// Following any i_stb request, assuming we are idle, immediately`
446			`// begin a bus transaction`
447			`always @(posedge i_clk)`
448			`if ((f_past_valid)&&($past(i_stb))`
449			`&&(!$past(f_cyc))&&(!$past(i_reset)))`
450			`begin`
451			`if ($past(misaligned))`
452			`begin`
453			`ASSERT(!f_cyc);
454			`ASSERT(!o_busy);
455			`ASSERT(o_err);
456			`ASSERT(!o_valid);
457			`end else begin`
458			`ASSERT(f_cyc);
459			`ASSERT(o_busy);
460			`end`
461			`end`
462
463			`always @(posedge i_clk)`
464			`if (o_busy)`
465			`ASSUME(!i_stb);
466
467			`always @(posedge i_clk)`
468			`if (o_wb_cyc_gbl)`
469			`ASSERT((o_busy)\|\|(lock_gbl));
470
471			`always @(posedge i_clk)`
472			`if (o_wb_cyc_lcl)`
473			`ASSERT((o_busy)\|\|(lock_lcl));
474
475			`always @(posedge i_clk)`
476			`if (f_outstanding > 0)`
477			`ASSERT(o_busy);
478
479			`// If a transaction ends in an error, send o_err on the output port.`
480			`always @(posedge i_clk)`
481			`if (f_past_valid)`
482			`begin`
483			`if ($past(i_reset))`
484			`ASSERT(!o_err);
485			`else if (($past(f_cyc))&&($past(i_wb_err)))`
486			`ASSERT(o_err);
487			`else if ($past(misaligned))`
488			`ASSERT(o_err);
489			`end`
490
491			`// Always following a successful ACK, return an O_VALID value.`
492			`always @(posedge i_clk)`
493			`if (f_past_valid)`
494			`begin`
495			`if ($past(i_reset))`
496			`ASSERT(!o_valid);
497			`else if(($past(f_cyc))&&($past(i_wb_ack))`
498			`&&(!$past(o_wb_we)))`
499			`ASSERT(o_valid);
500			`else if ($past(misaligned))`

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[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Blame information for rev 209