Subversion Repositories zipcpu

///////////////////////////////////////////////////////////////////////////

//

// Filename:    memops.v

//

// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

//

// Purpose:     A memory unit to support a CPU.

//

//      In the interests of code simplicity, this memory operator is 

//      susceptible to unknown results should a new command be sent to it

//      before it completes the last one.  Unpredictable results might then

//      occurr.

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Tecnology, LLC

//

///////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

///////////////////////////////////////////////////////////////////////////

//

module  memops(i_clk, i_rst, i_stb,

                i_op, i_addr, i_data, i_oreg,

                        o_busy, o_valid, o_wreg, o_result,

                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,

                i_wb_ack, i_wb_stall, i_wb_data);

        input                   i_clk, i_rst;

        input                   i_stb;

        // CPU interface

        input                   i_op;

        input           [31:0]   i_addr;

        input           [31:0]   i_data;

        input           [4:0]    i_oreg;

        // CPU outputs

        output  wire            o_busy;

        output  reg             o_valid;

        output  reg     [4:0]    o_wreg;

        output  reg     [31:0]   o_result;

        // Wishbone outputs

        output  reg             o_wb_cyc, o_wb_stb, o_wb_we;

        output  reg     [31:0]   o_wb_addr, o_wb_data;

        // Wishbone inputs

        input                   i_wb_ack, i_wb_stall;

        input           [31:0]   i_wb_data;

        always @(posedge i_clk)

                if (i_rst)

                        o_wb_cyc <= 1'b0;

                else if (o_wb_cyc)

                        o_wb_cyc <= (~i_wb_ack);

                else if (i_stb) // New memory operation

                        // Grab the wishbone

                        o_wb_cyc  <= 1'b1;

        always @(posedge i_clk)

                if (o_wb_cyc)

                        o_wb_stb <= (o_wb_stb)&&(i_wb_stall);

                else

                        o_wb_stb  <= i_stb; // Grab wishbone on new operation

        always @(posedge i_clk)

                if (i_stb)

                begin

                        o_wb_we   <= i_op;

                        o_wb_data <= i_data;

                        o_wb_addr <= i_addr;

                end

        initial o_valid = 1'b0;

        always @(posedge i_clk)

                o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we);

        assign  o_busy = o_wb_cyc;

        always @(posedge i_clk)

                if (i_stb)

                        o_wreg    <= i_oreg;

        always @(posedge i_clk)

                if (i_wb_ack)

                        o_result <= i_wb_data;

endmodule