OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Blame information for rev 54

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    memops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A memory unit to support a CPU.
8
//
9
//      In the interests of code simplicity, this memory operator is 
10
//      susceptible to unknown results should a new command be sent to it
11
//      before it completes the last one.  Unpredictable results might then
12
//      occurr.
13
//
14 36 dgisselq
//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
15
//              error signal).
16
//
17 3 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Tecnology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////
39
//
40 2 dgisselq
module  memops(i_clk, i_rst, i_stb,
41
                i_op, i_addr, i_data, i_oreg,
42 36 dgisselq
                        o_busy, o_valid, o_err, o_wreg, o_result,
43
                o_wb_cyc_gbl, o_wb_cyc_lcl,
44
                        o_wb_stb_gbl, o_wb_stb_lcl,
45
                        o_wb_we, o_wb_addr, o_wb_data,
46
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
47 48 dgisselq
        parameter       ADDRESS_WIDTH=24, AW=ADDRESS_WIDTH;
48 2 dgisselq
        input                   i_clk, i_rst;
49
        input                   i_stb;
50
        // CPU interface
51
        input                   i_op;
52
        input           [31:0]   i_addr;
53
        input           [31:0]   i_data;
54
        input           [4:0]    i_oreg;
55
        // CPU outputs
56
        output  wire            o_busy;
57
        output  reg             o_valid;
58 36 dgisselq
        output  reg             o_err;
59 2 dgisselq
        output  reg     [4:0]    o_wreg;
60
        output  reg     [31:0]   o_result;
61
        // Wishbone outputs
62 36 dgisselq
        output  reg             o_wb_cyc_gbl, o_wb_stb_gbl;
63
        output  reg             o_wb_cyc_lcl, o_wb_stb_lcl, o_wb_we;
64 48 dgisselq
        output  reg     [(AW-1):0]       o_wb_addr;
65
        output  reg     [31:0]   o_wb_data;
66 2 dgisselq
        // Wishbone inputs
67 36 dgisselq
        input                   i_wb_ack, i_wb_stall, i_wb_err;
68 2 dgisselq
        input           [31:0]   i_wb_data;
69
 
70 36 dgisselq
        wire    gbl_stb, lcl_stb;
71
        assign  lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
72
        assign  gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
73
 
74 2 dgisselq
        always @(posedge i_clk)
75
                if (i_rst)
76 36 dgisselq
                begin
77
                        o_wb_cyc_gbl <= 1'b0;
78
                        o_wb_cyc_lcl <= 1'b0;
79
                end else if ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))
80
                begin
81
                        if ((i_wb_ack)||(i_wb_err))
82
                        begin
83
                                o_wb_cyc_gbl <= 1'b0;
84
                                o_wb_cyc_lcl <= 1'b0;
85
                        end
86
                end else if (i_stb) // New memory operation
87
                begin // Grab the wishbone
88
                        o_wb_cyc_lcl <= lcl_stb;
89
                        o_wb_cyc_gbl <= gbl_stb;
90
                end
91 3 dgisselq
        always @(posedge i_clk)
92 36 dgisselq
                if (o_wb_cyc_gbl)
93
                        o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
94 3 dgisselq
                else
95 36 dgisselq
                        o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation
96 3 dgisselq
        always @(posedge i_clk)
97 36 dgisselq
                if (o_wb_cyc_lcl)
98
                        o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
99
                else
100
                        o_wb_stb_lcl  <= lcl_stb; // Grab wishbone on new operation
101
        always @(posedge i_clk)
102 3 dgisselq
                if (i_stb)
103
                begin
104 2 dgisselq
                        o_wb_we   <= i_op;
105
                        o_wb_data <= i_data;
106 48 dgisselq
                        o_wb_addr <= i_addr[(AW-1):0];
107 2 dgisselq
                end
108
 
109
        initial o_valid = 1'b0;
110
        always @(posedge i_clk)
111 36 dgisselq
                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
112
        initial o_err = 1'b0;
113
        always @(posedge i_clk)
114
                o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
115
        assign  o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
116 2 dgisselq
 
117
        always @(posedge i_clk)
118 3 dgisselq
                if (i_stb)
119 2 dgisselq
                        o_wreg    <= i_oreg;
120
        always @(posedge i_clk)
121 3 dgisselq
                if (i_wb_ack)
122 2 dgisselq
                        o_result <= i_wb_data;
123
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.