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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: regset.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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module pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
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o_i, o_pc, o_v,
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o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_data);
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parameter LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN), BUSW=32;
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input i_clk, i_rst, i_new_pc, i_stall_n;
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input [(BUSW-1):0] i_pc;
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output reg [(BUSW-1):0] o_i;
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output reg [(BUSW-1):0] o_pc;
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output wire o_v;
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//
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output reg o_wb_cyc, o_wb_stb;
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output wire o_wb_we;
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output reg [(BUSW-1):0] o_wb_addr;
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output wire [(BUSW-1):0] o_wb_data;
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//
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input i_wb_ack, i_wb_stall;
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input [(BUSW-1):0] i_wb_data;
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// Fixed bus outputs: we read from the bus only, never write.
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// Thus the output data is ... irrelevant and don't care. We set it
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// to zero just to set it to something.
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assign o_wb_we = 1'b0;
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assign o_wb_data = 0;
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reg [(BUSW-1):0] r_cache_base, r_cache_offset;
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reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
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reg [(BUSW-1):0] cache[0:(CACHELEN-1)];
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wire [(LGCACHELEN-1):0] c_cache_offset;
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assign c_cache_offset = r_cache_offset[(LGCACHELEN-1):0];
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reg r_addr_set;
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reg [(BUSW-1):0] r_addr;
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wire [(BUSW-1):0] bus_nvalid;
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assign bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
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initial r_nvalid = 0;
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initial r_cache_base = 0;
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always @(posedge i_clk)
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begin
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if (i_rst)
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o_wb_cyc <= 1'b0;
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else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
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&&(i_pc > r_cache_base)
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&&(i_pc < r_cache_base + bus_nvalid))
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begin
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// The new instruction is in our cache, do nothing
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// with the bus here.
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end else if ((o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
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&&((i_pc < r_cache_base)
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||(i_pc >= r_cache_base + CACHELEN)))
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begin
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// We need to abandon our bus action to start over in
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// a new region, setting up a new cache. This may
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// happen mid cycle while waiting for a result. By
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// dropping o_wb_cyc, we state that we are no longer
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// interested in that result--whatever it might be.
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o_wb_cyc <= 1'b0;
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o_wb_stb <= 1'b0;
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end else if ((~o_wb_cyc)&&(
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((i_new_pc)&&((r_nvalid == 0)
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||(i_pc < r_cache_base)
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||(i_pc >= r_cache_base + CACHELEN)))
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||((r_addr_set)&&((r_addr < r_cache_base)
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||(r_addr >= r_cache_base + CACHELEN)))
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))
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begin
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// Start a bus transaction
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
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r_acks_waiting <= 0;
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r_nvalid <= 0;
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r_cache_base <= (i_new_pc) ? i_pc : r_addr;
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r_cache_offset <= 0;
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end else if ((~o_wb_cyc)&&(r_addr_set)
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&&(r_addr >= r_cache_base
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+ (1<<(LGCACHELEN-2))
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+ (1<<(LGCACHELEN-1))))
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begin
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// If we're using the last quarter of the cache, then
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// let's start a bus transaction to extend the cache.
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o_wb_cyc <= 1'b1;
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o_wb_stb <= 1'b1;
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o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
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r_acks_waiting <= 0;
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r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
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r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
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r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
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end else if (o_wb_cyc)
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begin
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// This handles everything ... but the case where
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// while reading we need to extend our cache.
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if ((o_wb_stb)&&(~i_wb_stall))
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begin
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o_wb_addr <= o_wb_addr + 1;
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if (o_wb_addr - r_cache_base >= CACHELEN-1)
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o_wb_stb <= 1'b0;
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end
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if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
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r_acks_waiting <= r_acks_waiting
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+ ((i_wb_ack)? 0:1);
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else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
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r_acks_waiting <= r_acks_waiting - 1;
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if (i_wb_ack)
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begin
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cache[r_nvalid[(LGCACHELEN-1):0]+c_cache_offset] <= i_wb_data;
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r_nvalid <= r_nvalid + 1;
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if ((r_acks_waiting == 1)&&(~o_wb_stb))
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o_wb_cyc <= 1'b0;
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end
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end
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end
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initial r_addr_set = 1'b0;
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always @(posedge i_clk)
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if (i_rst)
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r_addr_set <= 1'b0;
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else if (i_new_pc)
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r_addr_set <= 1'b1;
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// Now, read from the cache
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wire w_cv; // Cache valid, address is in the cache
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reg r_cv;
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assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
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&&(r_addr-r_cache_base < bus_nvalid));
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always @(posedge i_clk)
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r_cv <= (~i_new_pc)&&(w_cv);
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assign o_v = (r_cv)&&(~i_new_pc);
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always @(posedge i_clk)
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if (i_new_pc)
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r_addr <= i_pc;
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else if ((i_stall_n)&&(w_cv))
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r_addr <= r_addr + 1;
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wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;
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assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];
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assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+c_cache_offset;
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always @(posedge i_clk)
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if (i_stall_n)
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o_i <= cache[c_rdaddr];
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always @(posedge i_clk)
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if (i_stall_n)
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o_pc <= r_addr;
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endmodule
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