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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    pipefetch.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
//              with no stalls, can be quite a chore.  Worse, the Wishbone
//              takes a couple of cycles just to read one instruction from
//              the bus.  However, if we use pipeline accesses to the Wishbone
//              bus, then we can read more and faster.  Further, if we cache
//              these results so that we have them before we need them, then
//              we have a chance of keeping our CPU from stalling.  Those are
//              the purposes of this instruction fetch module: 1) Pipeline
//              wishbone accesses, and 2) an instruction cache.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
                        BUSW=32;
        input                           i_clk, i_rst, i_new_pc, i_stall_n;
        input           [(BUSW-1):0]     i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(BUSW-1):0]     o_pc;
        output  wire                    o_v;
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  reg     [(BUSW-1):0]     o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        input                   i_wb_ack, i_wb_stall;
        input           [(BUSW-1):0]     i_wb_data;
        //
        // Is the (data) memory unit also requesting access to the bus?
        input                           i_wb_request;
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
 
        reg     [(BUSW-1):0]             r_cache_base;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
 
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
 
        reg                     r_addr_set;
        reg     [(BUSW-1):0]     r_addr;
 
        wire    [(BUSW-1):0]     bus_nvalid;
        assign  bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
 
        // What are some of the conditions for which we need to restart the
        // cache?
        wire    w_pc_out_of_bounds;
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
                                        ||(i_pc < r_cache_base)
                                        ||(i_pc >= r_cache_base + CACHELEN)));
        wire    w_ran_off_end_of_cache;
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
                                        ||(r_addr >= r_cache_base + CACHELEN)));
        wire    w_running_out_of_cache;
        assign  w_running_out_of_cache = (r_addr_set)
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
                                                + (1<<(LGCACHELEN-1)));
        initial r_nvalid = 0;
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        begin
                if (i_rst)
                begin
                        o_wb_cyc <= 1'b0;
                        // r_cache_base <= RESET_ADDRESS;
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                //              &&(i_pc >= r_cache_base)
                //              &&(i_pc < r_cache_base + bus_nvalid))
                // begin
                        // The new instruction is in our cache, do nothing
                        // with the bus here.
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
                begin
                        // We need to abandon our bus action to start over in
                        // a new region, setting up a new cache.  This may
                        // happen mid cycle while waiting for a result.  By
                        // dropping o_wb_cyc, we state that we are no longer
                        // interested in that result--whatever it might be.
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
                begin
                        // Restart a bus cycle that was interrupted when the
                        // data section wanted access to our bus.
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= r_cache_base + bus_nvalid;
                end else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                begin
                        // Start a bus transaction
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        // r_nvalid <= 0;
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                        // r_cache_offset <= 0;
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                begin
                        // If we're using the last quarter of the cache, then
                        // let's start a bus transaction to extend the cache.
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
                        // r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
                end else if (o_wb_cyc)
                begin
                        // This handles everything ... but the case where
                        // while reading we need to extend our cache.
                        if ((o_wb_stb)&&(~i_wb_stall))
                        begin
                                // o_wb_addr <= o_wb_addr + 1;
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
                                        ||(i_wb_request))
                                        o_wb_stb <= 1'b0;
                        end
 
                        if (i_wb_ack)
                        begin
                                // r_nvalid <= r_nvalid + 1;
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                        o_wb_cyc <= 1'b0;
                        end
                end
        end
 
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                else if ((o_wb_cyc)&&(i_wb_ack))
                        r_nvalid <= r_nvalid+1;
 
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
 
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_cache_offset <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
 
        always @(posedge i_clk)
                if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                                        ||(w_ran_off_end_of_cache)))
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
                        o_wb_addr <= o_wb_addr + 1;
 
        initial r_acks_waiting = 0;
        always @(posedge i_clk)
                if (~o_wb_cyc)
                        r_acks_waiting <= 0;
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
                        r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
                                r_acks_waiting <= r_acks_waiting - 1;
 
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
                                        <= i_wb_data;
 
        initial r_addr_set = 1'b0;
        always @(posedge i_clk)
                if (i_rst)
                        r_addr_set <= 1'b0;
                else if (i_new_pc)
                        r_addr_set <= 1'b1;
 
        // Now, read from the cache
        wire    w_cv;   // Cache valid, address is in the cache
        reg     r_cv;
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
                        &&(r_addr-r_cache_base < bus_nvalid));
        always @(posedge i_clk)
                r_cv <= (~i_new_pc)&&(w_cv);
        assign  o_v = (r_cv)&&(~i_new_pc);
 
        always @(posedge i_clk)
                if (i_new_pc)
                        r_addr <= i_pc;
                else if ((i_stall_n)&&(w_cv))
                        r_addr <= r_addr + 1;
 
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
        always @(posedge i_clk)
                if (i_stall_n)
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
                if (i_stall_n)
                        o_pc <= r_addr;
 
 
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3	3	dgisselq	`// Filename: pipefetch.v`
4	2	dgisselq	`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7	3	dgisselq	`// Purpose: Keeping our CPU fed with instructions, at one per clock and`
8			`// with no stalls, can be quite a chore. Worse, the Wishbone`
9			`// takes a couple of cycles just to read one instruction from`
10			`// the bus. However, if we use pipeline accesses to the Wishbone`
11			`// bus, then we can read more and faster. Further, if we cache`
12			`// these results so that we have them before we need them, then`
13			`// we have a chance of keeping our CPU from stalling. Those are`
14			`// the purposes of this instruction fetch module: 1) Pipeline`
15			`// wishbone accesses, and 2) an instruction cache.`
16	2	dgisselq	`//`
17			`// Creator: Dan Gisselquist, Ph.D.`
18			`// Gisselquist Tecnology, LLC`
19			`//`
20			`////////////////////////////////////////////////////////////////////////////////`
21			`//`
22			`// Copyright (C) 2015, Gisselquist Technology, LLC`
23			`//`
24			`// This program is free software (firmware): you can redistribute it and/or`
25			`// modify it under the terms of the GNU General Public License as published`
26			`// by the Free Software Foundation, either version 3 of the License, or (at`
27			`// your option) any later version.`
28			`//`
29			`// This program is distributed in the hope that it will be useful, but WITHOUT`
30			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
31			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
32			`// for more details.`
33			`//`
34			`// License: GPL, v3, as defined and found on www.gnu.org,`
35			`// http://www.gnu.org/licenses/gpl.html`
36			`//`
37			`//`
38			`////////////////////////////////////////////////////////////////////////////////`
39			`//`
40			`module pipefetch(i_clk, i_rst, i_new_pc, i_stall_n, i_pc,`
41			`o_i, o_pc, o_v,`
42			`o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,`
43	3	dgisselq	`i_wb_ack, i_wb_stall, i_wb_data, i_wb_request);`
44			`parameter RESET_ADDRESS=32'h0010_0000,`
45			`LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),`
46			`BUSW=32;`
47	2	dgisselq	`input i_clk, i_rst, i_new_pc, i_stall_n;`
48			`input [(BUSW-1):0] i_pc;`
49			`output reg [(BUSW-1):0] o_i;`
50			`output reg [(BUSW-1):0] o_pc;`
51			`output wire o_v;`
52			`//`
53			`output reg o_wb_cyc, o_wb_stb;`
54			`output wire o_wb_we;`
55			`output reg [(BUSW-1):0] o_wb_addr;`
56			`output wire [(BUSW-1):0] o_wb_data;`
57			`//`
58			`input i_wb_ack, i_wb_stall;`
59			`input [(BUSW-1):0] i_wb_data;`
60	3	dgisselq	`//`
61			`// Is the (data) memory unit also requesting access to the bus?`
62			`input i_wb_request;`
63	2	dgisselq
64			`// Fixed bus outputs: we read from the bus only, never write.`
65			`// Thus the output data is ... irrelevant and don't care. We set it`
66			`// to zero just to set it to something.`
67			`assign o_wb_we = 1'b0;`
68			`assign o_wb_data = 0;`
69
70	3	dgisselq	`reg [(BUSW-1):0] r_cache_base;`
71	2	dgisselq	`reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;`
72			`reg [(BUSW-1):0] cache[0:(CACHELEN-1)];`
73
74	3	dgisselq	`reg [(LGCACHELEN-1):0] r_cache_offset;`
75	2	dgisselq
76			`reg r_addr_set;`
77			`reg [(BUSW-1):0] r_addr;`
78
79			`wire [(BUSW-1):0] bus_nvalid;`
80			`assign bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };`
81
82	3	dgisselq	`// What are some of the conditions for which we need to restart the`
83			`// cache?`
84			`wire w_pc_out_of_bounds;`
85			`assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)`
86			`\|\|(i_pc < r_cache_base)`
87			`\|\|(i_pc >= r_cache_base + CACHELEN)));`
88			`wire w_ran_off_end_of_cache;`
89			`assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)`
90			`\|\|(r_addr >= r_cache_base + CACHELEN)));`
91			`wire w_running_out_of_cache;`
92			`assign w_running_out_of_cache = (r_addr_set)`
93			`&&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))`
94			`+ (1<<(LGCACHELEN-1)));`
95	2	dgisselq	`initial r_nvalid = 0;`
96	3	dgisselq	`initial r_cache_base = RESET_ADDRESS;`
97	2	dgisselq	`always @(posedge i_clk)`
98			`begin`
99			`if (i_rst)`
100	3	dgisselq	`begin`
101	2	dgisselq	`o_wb_cyc <= 1'b0;`
102	3	dgisselq	`// r_cache_base <= RESET_ADDRESS;`
103			`// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)`
104			`// &&(i_pc >= r_cache_base)`
105			`// &&(i_pc < r_cache_base + bus_nvalid))`
106			`// begin`
107	2	dgisselq	`// The new instruction is in our cache, do nothing`
108			`// with the bus here.`
109	3	dgisselq	`end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))`
110	2	dgisselq	`begin`
111			`// We need to abandon our bus action to start over in`
112			`// a new region, setting up a new cache. This may`
113			`// happen mid cycle while waiting for a result. By`
114			`// dropping o_wb_cyc, we state that we are no longer`
115			`// interested in that result--whatever it might be.`
116			`o_wb_cyc <= 1'b0;`
117			`o_wb_stb <= 1'b0;`
118	3	dgisselq	`end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))`
119			`begin`
120			`// Restart a bus cycle that was interrupted when the`
121			`// data section wanted access to our bus.`
122			`o_wb_cyc <= 1'b1;`
123			`o_wb_stb <= 1'b1;`
124			`// o_wb_addr <= r_cache_base + bus_nvalid;`
125	2	dgisselq	`end else if ((~o_wb_cyc)&&(`
126	3	dgisselq	`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
127	2	dgisselq	`begin`
128			`// Start a bus transaction`
129			`o_wb_cyc <= 1'b1;`
130			`o_wb_stb <= 1'b1;`
131	3	dgisselq	`// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;`
132			`// r_nvalid <= 0;`
133			`// r_cache_base <= (i_new_pc) ? i_pc : r_addr;`
134			`// r_cache_offset <= 0;`
135			`end else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
136	2	dgisselq	`begin`
137			`// If we're using the last quarter of the cache, then`
138			`// let's start a bus transaction to extend the cache.`
139			`o_wb_cyc <= 1'b1;`
140			`o_wb_stb <= 1'b1;`
141	3	dgisselq	`// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));`
142			`// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));`
143			`// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));`
144			`// r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));`
145	2	dgisselq	`end else if (o_wb_cyc)`
146			`begin`
147			`// This handles everything ... but the case where`
148			`// while reading we need to extend our cache.`
149			`if ((o_wb_stb)&&(~i_wb_stall))`
150			`begin`
151	3	dgisselq	`// o_wb_addr <= o_wb_addr + 1;`
152			`if ((o_wb_addr - r_cache_base >= CACHELEN-1)`
153			`\|\|(i_wb_request))`
154	2	dgisselq	`o_wb_stb <= 1'b0;`
155			`end`
156
157			`if (i_wb_ack)`
158			`begin`
159	3	dgisselq	`// r_nvalid <= r_nvalid + 1;`
160	2	dgisselq	`if ((r_acks_waiting == 1)&&(~o_wb_stb))`
161			`o_wb_cyc <= 1'b0;`
162			`end`
163			`end`
164			`end`
165
166	3	dgisselq	`always @(posedge i_clk)`
167			`if ((~o_wb_cyc)&&(`
168			`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
169			`r_nvalid <= 0;`
170			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
171			`r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));`
172			`else if ((o_wb_cyc)&&(i_wb_ack))`
173			`r_nvalid <= r_nvalid+1;`
174
175			`always @(posedge i_clk)`
176			`if ((~o_wb_cyc)&&(`
177			`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
178			`r_cache_base <= (i_new_pc) ? i_pc : r_addr;`
179			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
180			`r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));`
181
182			`always @(posedge i_clk)`
183			`if ((~o_wb_cyc)&&(`
184			`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
185			`r_cache_offset <= 0;`
186			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
187			`r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));`
188
189			`always @(posedge i_clk)`
190			`if ((~o_wb_cyc)&&((w_pc_out_of_bounds)`
191			`\|\|(w_ran_off_end_of_cache)))`
192			`o_wb_addr <= (i_new_pc) ? i_pc : r_addr;`
193			`else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))`
194			`o_wb_addr <= o_wb_addr + 1;`
195
196			`initial r_acks_waiting = 0;`
197			`always @(posedge i_clk)`
198			`if (~o_wb_cyc)`
199			`r_acks_waiting <= 0;`
200			`else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))`
201			`r_acks_waiting <= r_acks_waiting + ((i_wb_ack)? 0:1);`
202			`else if ((i_wb_ack)&&((~o_wb_stb)\|\|(i_wb_stall)))`
203			`r_acks_waiting <= r_acks_waiting - 1;`
204
205			`always @(posedge i_clk)`
206			`if ((o_wb_cyc)&&(i_wb_ack))`
207			`cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]`
208			`<= i_wb_data;`
209
210	2	dgisselq	`initial r_addr_set = 1'b0;`
211			`always @(posedge i_clk)`
212			`if (i_rst)`
213			`r_addr_set <= 1'b0;`
214			`else if (i_new_pc)`
215			`r_addr_set <= 1'b1;`
216
217			`// Now, read from the cache`
218			`wire w_cv; // Cache valid, address is in the cache`
219			`reg r_cv;`
220			`assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)`
221			`&&(r_addr-r_cache_base < bus_nvalid));`
222			`always @(posedge i_clk)`
223			`r_cv <= (~i_new_pc)&&(w_cv);`
224			`assign o_v = (r_cv)&&(~i_new_pc);`
225
226			`always @(posedge i_clk)`
227			`if (i_new_pc)`
228			`r_addr <= i_pc;`
229			`else if ((i_stall_n)&&(w_cv))`
230			`r_addr <= r_addr + 1;`
231
232			`wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;`
233			`assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];`
234	3	dgisselq	`assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;`
235	2	dgisselq	`always @(posedge i_clk)`
236			`if (i_stall_n)`
237			`o_i <= cache[c_rdaddr];`
238			`always @(posedge i_clk)`
239			`if (i_stall_n)`
240			`o_pc <= r_addr;`
241
242
243			`endmodule`

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[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Blame information for rev 5