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////////////////////////////////////////////////////////////////////////////////
//
// Filename:    pipefetch.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
//              with no stalls, can be quite a chore.  Worse, the Wishbone
//              takes a couple of cycles just to read one instruction from
//              the bus.  However, if we use pipeline accesses to the Wishbone
//              bus, then we can read more and faster.  Further, if we cache
//              these results so that we have them before we need them, then
//              we have a chance of keeping our CPU from stalling.  Those are
//              the purposes of this instruction fetch module: 1) Pipeline
//              wishbone accesses, and 2) an instruction cache.
//
//      20150919 -- Fixed a nasty race condition whereby the pipefetch routine
//              would produce either the same instruction twice, or skip
//              an instruction.  This condition was dependent on the CPU stall
//              condition, and would only take place if the pipeline wasn't 
//              completely full throughout the stall.
//
//              Interface support was also added for trapping on illegal
//              instructions (i.e., instruction fetches that cause bus errors),
//              however the internal interface has not caught up to supporting
//              these exceptions yet.
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Tecnology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
                        o_i, o_pc, o_v,
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
                        o_illegal);
        parameter       RESET_ADDRESS=32'h0010_0000,
                        LGCACHELEN = 6, ADDRESS_WIDTH=24,
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
        input                           i_clk, i_rst, i_new_pc,
                                        i_clear_cache, i_stall_n;
        input           [(AW-1):0]       i_pc;
        output  reg     [(BUSW-1):0]     o_i;
        output  reg     [(AW-1):0]       o_pc;
        output  wire                    o_v;
        //
        output  reg             o_wb_cyc, o_wb_stb;
        output  wire            o_wb_we;
        output  reg     [(AW-1):0]       o_wb_addr;
        output  wire    [(BUSW-1):0]     o_wb_data;
        //
        input                   i_wb_ack, i_wb_stall, i_wb_err;
        input           [(BUSW-1):0]     i_wb_data;
        //
        // Is the (data) memory unit also requesting access to the bus?
        input                           i_wb_request;
        output  wire                    o_illegal;
 
        // Fixed bus outputs: we read from the bus only, never write.
        // Thus the output data is ... irrelevant and don't care.  We set it
        // to zero just to set it to something.
        assign  o_wb_we = 1'b0;
        assign  o_wb_data = 0;
 
        reg     [(AW-1):0]               r_cache_base;
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
 
        wire    [(LGCACHELEN-1):0]       w_cache_offset;
        reg     [1:0]                    r_cache_offset;
 
        reg                     r_addr_set;
        reg     [(AW-1):0]       r_addr;
 
        wire    [(AW-1):0]       bus_nvalid;
        assign  bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };
 
        // What are some of the conditions for which we need to restart the
        // cache?
        wire    w_pc_out_of_bounds;
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
                                        ||(i_pc < r_cache_base)
                                        ||(i_pc >= r_cache_base + CACHELEN)
                                        ||(i_pc >= r_cache_base + bus_nvalid+5)));
        wire    w_ran_off_end_of_cache;
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
                                        ||(r_addr >= r_cache_base + CACHELEN)
                                        ||(r_addr >= r_cache_base + bus_nvalid+5)));
        wire    w_running_out_of_cache;
        assign  w_running_out_of_cache = (r_addr_set)
                        &&(r_addr >= r_cache_base +
                                // {{(AW-LGCACHELEN-1),{1'b0}},2'b11,
                                //              {(LGCACHELEN-1){1'b0}}})
                                // (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))
                                +(3<<(LGCACHELEN-2)))
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
 
        initial r_cache_base = RESET_ADDRESS;
        always @(posedge i_clk)
        begin
                if ((i_rst)||(i_clear_cache)||((o_wb_cyc)&&(i_wb_err)))
                begin
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                        // r_cache_base <= RESET_ADDRESS;
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
                //              &&(i_pc >= r_cache_base)
                //              &&(i_pc < r_cache_base + bus_nvalid))
                // begin
                        // The new instruction is in our cache, do nothing
                        // with the bus here.
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
                begin
                        // We need to abandon our bus action to start over in
                        // a new region, setting up a new cache.  This may
                        // happen mid cycle while waiting for a result.  By
                        // dropping o_wb_cyc, we state that we are no longer
                        // interested in that result--whatever it might be.
                        o_wb_cyc <= 1'b0;
                        o_wb_stb <= 1'b0;
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
                begin
                        // Restart a bus cycle that was interrupted when the
                        // data section wanted access to our bus.
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= r_cache_base + bus_nvalid;
                end else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                begin
                        // Start a bus transaction
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                        // r_nvalid <= 0;
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                        // w_cache_offset <= 0;
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                begin
                        // If we're using the last quarter of the cache, then
                        // let's start a bus transaction to extend the cache.
                        o_wb_cyc <= 1'b1;
                        o_wb_stb <= 1'b1;
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
                        // w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2));
                end else if (o_wb_cyc)
                begin
                        // This handles everything ... but the case where
                        // while reading we need to extend our cache.
                        if ((o_wb_stb)&&(~i_wb_stall))
                        begin
                                // o_wb_addr <= o_wb_addr + 1;
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
                                        ||(i_wb_request))
                                        o_wb_stb <= 1'b0;
                        end
 
                        if (i_wb_ack)
                        begin
                                // r_nvalid <= r_nvalid + 1;
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
                                        o_wb_cyc <= 1'b0;
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
                                o_wb_cyc <= 1'b0;
                end
        end
 
 
        initial r_nvalid = 0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
                        r_nvalid <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_nvalid[LGCACHELEN:(LGCACHELEN-2)]
                                <= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111;
                                        // i.e.  - (1<<(LGCACHELEN-2));
                else if ((o_wb_cyc)&&(i_wb_ack))
                        r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1;
 
        always @(posedge i_clk)
                if (i_clear_cache)
                        r_cache_base <= i_pc;
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)
                                ||(w_ran_off_end_of_cache)))
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_base[(AW-1):(LGCACHELEN-2)]
                                <= r_cache_base[(AW-1):(LGCACHELEN-2)]
                                        + {{(AW-LGCACHELEN+1){1'b0}},1'b1};
                                        // i.e.  + (1<<(LGCACHELEN-2));
 
        always @(posedge i_clk)
                if (i_clear_cache)
                        r_cache_offset <= 0;
                else if ((~o_wb_cyc)&&(
                                (w_pc_out_of_bounds)
                                ||(w_ran_off_end_of_cache)))
                        r_cache_offset <= 0;
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
                        r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01;
        assign  w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} };
 
        always @(posedge i_clk)
                if (i_clear_cache)
                        o_wb_addr <= i_pc;
                else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
                begin
                        if (i_wb_ack)
                                o_wb_addr <= r_cache_base + bus_nvalid+1;
                        else
                                o_wb_addr <= r_cache_base + bus_nvalid;
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
                                        ||(w_ran_off_end_of_cache)))
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
                else if ((o_wb_stb)&&(~i_wb_stall))     // && o_wb_cyc
                        o_wb_addr <= o_wb_addr + 1;
 
        initial r_acks_waiting = 0;
        always @(posedge i_clk)
                if (~o_wb_cyc)
                        r_acks_waiting <= 0;
                // o_wb_cyc *must* be true for all following
                else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)
                        r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};
                else if ((i_wb_ack)&&((~o_wb_stb)||(i_wb_stall))) //&&(o_wb_cyc)
                        r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;
 
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_ack))
                        cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]
                                        <= i_wb_data;
 
        initial r_addr_set = 1'b0;
        always @(posedge i_clk)
                if ((i_rst)||(i_clear_cache))
                        r_addr_set <= 1'b0;
                else if (i_new_pc)
                        r_addr_set <= 1'b1;
 
        // Now, read from the cache
        wire    w_cv;   // Cache valid, address is in the cache
        reg     r_cv;
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
                        &&(r_addr-r_cache_base < bus_nvalid));
        always @(posedge i_clk)
                r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
        assign  o_v = (r_cv)&&(~i_new_pc);
 
        always @(posedge i_clk)
                if (i_new_pc)
                        r_addr <= i_pc;
                else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
                        r_addr <= r_addr + {{(AW-1){1'b0}},1'b1};
 
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset;
        always @(posedge i_clk)
                if ((~o_v)||((i_stall_n)&&(o_v)))
                        o_i <= cache[c_rdaddr];
        always @(posedge i_clk)
                if ((~o_v)||((i_stall_n)&&(o_v)))
                        o_pc <= r_addr;
 
        reg     [(AW-1):0]       ill_address;
        initial ill_address = 0;
        always @(posedge i_clk)
                if ((o_wb_cyc)&&(i_wb_err))
                        ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};
 
        assign  o_illegal = (o_pc == ill_address);
 
 
endmodule

Line No.	Rev	Author	Line
1	2	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3	3	dgisselq	`// Filename: pipefetch.v`
4	2	dgisselq	`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7	3	dgisselq	`// Purpose: Keeping our CPU fed with instructions, at one per clock and`
8			`// with no stalls, can be quite a chore. Worse, the Wishbone`
9			`// takes a couple of cycles just to read one instruction from`
10			`// the bus. However, if we use pipeline accesses to the Wishbone`
11			`// bus, then we can read more and faster. Further, if we cache`
12			`// these results so that we have them before we need them, then`
13			`// we have a chance of keeping our CPU from stalling. Those are`
14			`// the purposes of this instruction fetch module: 1) Pipeline`
15			`// wishbone accesses, and 2) an instruction cache.`
16	2	dgisselq	`//`
17	36	dgisselq	`// 20150919 -- Fixed a nasty race condition whereby the pipefetch routine`
18			`// would produce either the same instruction twice, or skip`
19			`// an instruction. This condition was dependent on the CPU stall`
20			`// condition, and would only take place if the pipeline wasn't`
21			`// completely full throughout the stall.`
22			`//`
23			`// Interface support was also added for trapping on illegal`
24			`// instructions (i.e., instruction fetches that cause bus errors),`
25			`// however the internal interface has not caught up to supporting`
26			`// these exceptions yet.`
27			`//`
28	2	dgisselq	`// Creator: Dan Gisselquist, Ph.D.`
29			`// Gisselquist Tecnology, LLC`
30			`//`
31			`////////////////////////////////////////////////////////////////////////////////`
32			`//`
33			`// Copyright (C) 2015, Gisselquist Technology, LLC`
34			`//`
35			`// This program is free software (firmware): you can redistribute it and/or`
36			`// modify it under the terms of the GNU General Public License as published`
37			`// by the Free Software Foundation, either version 3 of the License, or (at`
38			`// your option) any later version.`
39			`//`
40			`// This program is distributed in the hope that it will be useful, but WITHOUT`
41			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
42			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
43			`// for more details.`
44			`//`
45			`// License: GPL, v3, as defined and found on www.gnu.org,`
46			`// http://www.gnu.org/licenses/gpl.html`
47			`//`
48			`//`
49			`////////////////////////////////////////////////////////////////////////////////`
50			`//`
51	18	dgisselq	`module pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,`
52	2	dgisselq	`o_i, o_pc, o_v,`
53			`o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,`
54	36	dgisselq	`i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,`
55			`o_illegal);`
56	3	dgisselq	`parameter RESET_ADDRESS=32'h0010_0000,`
57	48	dgisselq	`LGCACHELEN = 6, ADDRESS_WIDTH=24,`
58			`CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;`
59	18	dgisselq	`input i_clk, i_rst, i_new_pc,`
60			`i_clear_cache, i_stall_n;`
61	48	dgisselq	`input [(AW-1):0] i_pc;`
62	2	dgisselq	`output reg [(BUSW-1):0] o_i;`
63	48	dgisselq	`output reg [(AW-1):0] o_pc;`
64	2	dgisselq	`output wire o_v;`
65			`//`
66			`output reg o_wb_cyc, o_wb_stb;`
67			`output wire o_wb_we;`
68	48	dgisselq	`output reg [(AW-1):0] o_wb_addr;`
69	2	dgisselq	`output wire [(BUSW-1):0] o_wb_data;`
70			`//`
71	36	dgisselq	`input i_wb_ack, i_wb_stall, i_wb_err;`
72	2	dgisselq	`input [(BUSW-1):0] i_wb_data;`
73	3	dgisselq	`//`
74			`// Is the (data) memory unit also requesting access to the bus?`
75			`input i_wb_request;`
76	36	dgisselq	`output wire o_illegal;`
77	2	dgisselq
78			`// Fixed bus outputs: we read from the bus only, never write.`
79			`// Thus the output data is ... irrelevant and don't care. We set it`
80			`// to zero just to set it to something.`
81			`assign o_wb_we = 1'b0;`
82			`assign o_wb_data = 0;`
83
84	48	dgisselq	`reg [(AW-1):0] r_cache_base;`
85	2	dgisselq	`reg [(LGCACHELEN):0] r_nvalid, r_acks_waiting;`
86			`reg [(BUSW-1):0] cache[0:(CACHELEN-1)];`
87
88	56	dgisselq	`wire [(LGCACHELEN-1):0] w_cache_offset;`
89			`reg [1:0] r_cache_offset;`
90	2	dgisselq
91			`reg r_addr_set;`
92	48	dgisselq	`reg [(AW-1):0] r_addr;`
93	2	dgisselq
94	48	dgisselq	`wire [(AW-1):0] bus_nvalid;`
95			`assign bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };`
96	2	dgisselq
97	3	dgisselq	`// What are some of the conditions for which we need to restart the`
98			`// cache?`
99			`wire w_pc_out_of_bounds;`
100			`assign w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)`
101			`\|\|(i_pc < r_cache_base)`
102	48	dgisselq	`\|\|(i_pc >= r_cache_base + CACHELEN)`
103			`\|\|(i_pc >= r_cache_base + bus_nvalid+5)));`
104	3	dgisselq	`wire w_ran_off_end_of_cache;`
105			`assign w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)`
106	48	dgisselq	`\|\|(r_addr >= r_cache_base + CACHELEN)`
107			`\|\|(r_addr >= r_cache_base + bus_nvalid+5)));`
108	3	dgisselq	`wire w_running_out_of_cache;`
109			`assign w_running_out_of_cache = (r_addr_set)`
110	56	dgisselq	`&&(r_addr >= r_cache_base +`
111			`// {{(AW-LGCACHELEN-1),{1'b0}},2'b11,`
112			`// {(LGCACHELEN-1){1'b0}}})`
113			`// (1<<(LGCACHELEN-2)) + (1<<(LGCACHELEN-1)))`
114			`+(3<<(LGCACHELEN-2)))`
115	48	dgisselq	`&&(\|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);`
116
117	3	dgisselq	`initial r_cache_base = RESET_ADDRESS;`
118	2	dgisselq	`always @(posedge i_clk)`
119			`begin`
120	63	dgisselq	`if ((i_rst)\|\|(i_clear_cache)\|\|((o_wb_cyc)&&(i_wb_err)))`
121	3	dgisselq	`begin`
122	2	dgisselq	`o_wb_cyc <= 1'b0;`
123	18	dgisselq	`o_wb_stb <= 1'b0;`
124	3	dgisselq	`// r_cache_base <= RESET_ADDRESS;`
125			`// end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)`
126			`// &&(i_pc >= r_cache_base)`
127			`// &&(i_pc < r_cache_base + bus_nvalid))`
128			`// begin`
129	2	dgisselq	`// The new instruction is in our cache, do nothing`
130			`// with the bus here.`
131	3	dgisselq	`end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))`
132	2	dgisselq	`begin`
133			`// We need to abandon our bus action to start over in`
134			`// a new region, setting up a new cache. This may`
135			`// happen mid cycle while waiting for a result. By`
136			`// dropping o_wb_cyc, we state that we are no longer`
137			`// interested in that result--whatever it might be.`
138			`o_wb_cyc <= 1'b0;`
139			`o_wb_stb <= 1'b0;`
140	3	dgisselq	`end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))`
141			`begin`
142			`// Restart a bus cycle that was interrupted when the`
143			`// data section wanted access to our bus.`
144			`o_wb_cyc <= 1'b1;`
145			`o_wb_stb <= 1'b1;`
146			`// o_wb_addr <= r_cache_base + bus_nvalid;`
147	2	dgisselq	`end else if ((~o_wb_cyc)&&(`
148	3	dgisselq	`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
149	2	dgisselq	`begin`
150			`// Start a bus transaction`
151			`o_wb_cyc <= 1'b1;`
152			`o_wb_stb <= 1'b1;`
153	3	dgisselq	`// o_wb_addr <= (i_new_pc) ? i_pc : r_addr;`
154			`// r_nvalid <= 0;`
155			`// r_cache_base <= (i_new_pc) ? i_pc : r_addr;`
156	56	dgisselq	`// w_cache_offset <= 0;`
157	3	dgisselq	`end else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
158	2	dgisselq	`begin`
159			`// If we're using the last quarter of the cache, then`
160			`// let's start a bus transaction to extend the cache.`
161			`o_wb_cyc <= 1'b1;`
162			`o_wb_stb <= 1'b1;`
163	3	dgisselq	`// o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));`
164			`// r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));`
165			`// r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));`
166	56	dgisselq	`// w_cache_offset <= w_cache_offset + (1<<(LGCACHELEN-2));`
167	2	dgisselq	`end else if (o_wb_cyc)`
168			`begin`
169			`// This handles everything ... but the case where`
170			`// while reading we need to extend our cache.`
171			`if ((o_wb_stb)&&(~i_wb_stall))`
172			`begin`
173	3	dgisselq	`// o_wb_addr <= o_wb_addr + 1;`
174			`if ((o_wb_addr - r_cache_base >= CACHELEN-1)`
175			`\|\|(i_wb_request))`
176	2	dgisselq	`o_wb_stb <= 1'b0;`
177			`end`
178
179			`if (i_wb_ack)`
180			`begin`
181	3	dgisselq	`// r_nvalid <= r_nvalid + 1;`
182	2	dgisselq	`if ((r_acks_waiting == 1)&&(~o_wb_stb))`
183			`o_wb_cyc <= 1'b0;`
184	36	dgisselq	`end else if ((r_acks_waiting == 0)&&(~o_wb_stb))`
185			`o_wb_cyc <= 1'b0;`
186	2	dgisselq	`end`
187			`end`
188
189	63	dgisselq
190	36	dgisselq	`initial r_nvalid = 0;`
191	3	dgisselq	`always @(posedge i_clk)`
192	18	dgisselq	`if ((i_rst)\|\|(i_clear_cache)) // Required, so we can reload memoy and then reset`
193	11	dgisselq	`r_nvalid <= 0;`
194			`else if ((~o_wb_cyc)&&(`
195	3	dgisselq	`(w_pc_out_of_bounds)\|\|(w_ran_off_end_of_cache)))`
196			`r_nvalid <= 0;`
197			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
198	56	dgisselq	`r_nvalid[LGCACHELEN:(LGCACHELEN-2)]`
199			`<= r_nvalid[LGCACHELEN:(LGCACHELEN-2)] +3'b111;`
200			`// i.e. - (1<<(LGCACHELEN-2));`
201	3	dgisselq	`else if ((o_wb_cyc)&&(i_wb_ack))`
202	56	dgisselq	`r_nvalid <= r_nvalid + {{(LGCACHELEN){1'b0}},1'b1}; // +1;`
203	3	dgisselq
204			`always @(posedge i_clk)`
205	18	dgisselq	`if (i_clear_cache)`
206			`r_cache_base <= i_pc;`
207			`else if ((~o_wb_cyc)&&(`
208			`(w_pc_out_of_bounds)`
209			`\|\|(w_ran_off_end_of_cache)))`
210	3	dgisselq	`r_cache_base <= (i_new_pc) ? i_pc : r_addr;`
211			`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
212	56	dgisselq	`r_cache_base[(AW-1):(LGCACHELEN-2)]`
213			`<= r_cache_base[(AW-1):(LGCACHELEN-2)]`
214			`+ {{(AW-LGCACHELEN+1){1'b0}},1'b1};`
215			`// i.e. + (1<<(LGCACHELEN-2));`
216	3	dgisselq
217			`always @(posedge i_clk)`
218	18	dgisselq	`if (i_clear_cache)`
219	3	dgisselq	`r_cache_offset <= 0;`
220	18	dgisselq	`else if ((~o_wb_cyc)&&(`
221			`(w_pc_out_of_bounds)`
222			`\|\|(w_ran_off_end_of_cache)))`
223			`r_cache_offset <= 0;`
224	3	dgisselq	`else if ((~o_wb_cyc)&&(w_running_out_of_cache))`
225	56	dgisselq	`r_cache_offset[1:0] <= r_cache_offset[1:0] + 2'b01;`
226			`assign w_cache_offset = { r_cache_offset, {(LGCACHELEN-2){1'b0}} };`
227	3	dgisselq
228			`always @(posedge i_clk)`
229	18	dgisselq	`if (i_clear_cache)`
230			`o_wb_addr <= i_pc;`
231	38	dgisselq	`else if ((o_wb_cyc)&&(w_pc_out_of_bounds))`
232			`begin`
233			`if (i_wb_ack)`
234			`o_wb_addr <= r_cache_base + bus_nvalid+1;`
235			`else`
236			`o_wb_addr <= r_cache_base + bus_nvalid;`
237			`end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)`
238	3	dgisselq	`\|\|(w_ran_off_end_of_cache)))`
239			`o_wb_addr <= (i_new_pc) ? i_pc : r_addr;`
240	63	dgisselq	`else if ((o_wb_stb)&&(~i_wb_stall)) // && o_wb_cyc`
241	3	dgisselq	`o_wb_addr <= o_wb_addr + 1;`
242
243			`initial r_acks_waiting = 0;`
244			`always @(posedge i_clk)`
245			`if (~o_wb_cyc)`
246			`r_acks_waiting <= 0;`
247	63	dgisselq	`// o_wb_cyc must be true for all following`
248			`else if ((o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack)) //&&(o_wb_cyc)`
249	56	dgisselq	`r_acks_waiting <= r_acks_waiting + {{(LGCACHELEN){1'b0}},1'b1};`
250	63	dgisselq	`else if ((i_wb_ack)&&((~o_wb_stb)\|\|(i_wb_stall))) //&&(o_wb_cyc)`
251	56	dgisselq	`r_acks_waiting <= r_acks_waiting + {(LGCACHELEN+1){1'b1}}; // - 1;`
252	3	dgisselq
253			`always @(posedge i_clk)`
254			`if ((o_wb_cyc)&&(i_wb_ack))`
255	56	dgisselq	`cache[r_nvalid[(LGCACHELEN-1):0]+w_cache_offset]`
256	3	dgisselq	`<= i_wb_data;`
257
258	2	dgisselq	`initial r_addr_set = 1'b0;`
259			`always @(posedge i_clk)`
260	18	dgisselq	`if ((i_rst)\|\|(i_clear_cache))`
261	2	dgisselq	`r_addr_set <= 1'b0;`
262			`else if (i_new_pc)`
263			`r_addr_set <= 1'b1;`
264
265			`// Now, read from the cache`
266			`wire w_cv; // Cache valid, address is in the cache`
267			`reg r_cv;`
268			`assign w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)`
269			`&&(r_addr-r_cache_base < bus_nvalid));`
270			`always @(posedge i_clk)`
271	36	dgisselq	`r_cv <= (~i_new_pc)&&((w_cv)\|\|((~i_stall_n)&&(r_cv)));`
272	2	dgisselq	`assign o_v = (r_cv)&&(~i_new_pc);`
273
274			`always @(posedge i_clk)`
275			`if (i_new_pc)`
276			`r_addr <= i_pc;`
277	36	dgisselq	`else if ( ((i_stall_n)&&(w_cv)) \|\| ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )`
278	56	dgisselq	`r_addr <= r_addr + {{(AW-1){1'b0}},1'b1};`
279	2	dgisselq
280			`wire [(LGCACHELEN-1):0] c_rdaddr, c_cache_base;`
281			`assign c_cache_base = r_cache_base[(LGCACHELEN-1):0];`
282	56	dgisselq	`assign c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+w_cache_offset;`
283	2	dgisselq	`always @(posedge i_clk)`
284	36	dgisselq	`if ((~o_v)\|\|((i_stall_n)&&(o_v)))`
285	2	dgisselq	`o_i <= cache[c_rdaddr];`
286			`always @(posedge i_clk)`
287	36	dgisselq	`if ((~o_v)\|\|((i_stall_n)&&(o_v)))`
288	2	dgisselq	`o_pc <= r_addr;`
289
290	63	dgisselq	`reg [(AW-1):0] ill_address;`
291			`initial ill_address = 0;`
292			`always @(posedge i_clk)`
293			`if ((o_wb_cyc)&&(i_wb_err))`
294			`ill_address <= o_wb_addr - {{(AW-LGCACHELEN-1){1'b0}}, r_acks_waiting};`
295
296			`assign o_illegal = (o_pc == ill_address);`
297
298
299	2	dgisselq	`endmodule`

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