Subversion Repositories zipcpu

///////////////////////////////////////////////////////////////////////////////

//

// Filename:    zipcpu.v

//

// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

//

// Purpose:     This is the top level module holding the core of the Zip CPU

//              together.  The Zip CPU is designed to be as simple as possible.

//              The instruction set is about as RISC as you can get, there are

//              only 16 instruction types supported (of which one isn't yet

//              supported ...)  Please see the accompanying iset.html file

//              for a description of these instructions.

//

//              All instructions are 32-bits wide.  All bus accesses, both

//              address and data, are 32-bits over a wishbone bus.

//

//      The Zip CPU is fully pipelined with the following pipeline stages:

//

//              1. Prefetch, returns the instruction from memory.  On the

//              Basys board that I'm working on, one instruction may be

//              issued every 20 clocks or so, unless and until I implement a

//              cache or local memory.

//

//              2. Instruction Decode

//

//              3. Read Operands

//

//              4. Apply Instruction

//

//              4. Write-back Results

//

//      A lot of difficult work has been placed into the pipeline stall

//      handling.  My original proposal was not to allow pipeline stalls at all.

//      The idea would be that the CPU would just run every clock and whatever

//      stalled answer took place would just get fixed a clock or two later,

//      meaning that the compiler could just schedule everything out.

//      This idea died at the memory interface, which can take a variable

//      amount of time to read or write any value, thus the whole CPU needed

//      to stall on a stalled memory access.

//

//      My next idea was to just let things complete.  I.e., once an instrution

//      starts, it continues to completion no matter what and we go on.  This

//      failed at writing the PC.  If the PC gets written in something such as

//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks

//      later, if whether or not something happens in those clocks depends

//      upon the instruction fetch filling the pipeline, then the CPU has a

//      non-deterministic behavior.

//

//      This leads to two possibilities: either *everything* stalls upon a 

//      stall condition, or partial results need to be destroyed before

//      they are written.  This is made more difficult by the fact that

//      once a command is written to the memory unit, whether it be a

//      read or a write, there is no undoing it--since peripherals on the

//      bus may act upon the answer with whatever side effects they might

//      have.  (For example, writing a '1' to the interrupt register will

//      clear certain interrupts ...)  Further, since the memory ops depend

//      upon conditions, the we'll need to wait for the condition codes to

//      be available before executing a memory op.  Thus, memory ops can 

//      proceed without stalling whenever either the previous instruction

//      doesn't write the flags register, or when the memory instruction doesn't

//      depend upon the flags register.

//

//      The other possibility is that we leave independent instruction

//      execution behind, so that the pipeline is always full and stalls,

//      or moves forward, together on every clock.

//

//      For now, we pick the first approach: independent instruction execution.

//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions

//      in their pipeline.  This leaves another problem: what happens on a

//      MOV -1+PC,PC instruction?  There will be four instructions behind this

//      one (or is it five?) that will need to be 'cancelled'.  So here's

//      the plan: Anything can be cancelled before the ALU/MEM stage,

//      since memory ops cannot be canceled after being issued.  Thus, the

//      ALU/MEM stage must stall if any prior instruction is going to write

//      the PC register (i.e. JMP).

//

//      Further, let's define a "STALL" as a reason to not execute a stage

//      due to some condition at or beyond the stage, and let's define

//      a VALID flag to mean that this stage has completed.  Thus, the clock

//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).

//      The ALU/MEM stages will also depend upon a master clock enable

//      (~SLEEP) condition as well.

//

//

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Tecnology, LLC

//

///////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

///////////////////////////////////////////////////////////////////////////////

//

// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined

// fetches are more complicated and therefore use more FPGA resources, while

// single fetches will cause the CPU to stall for about 5 stalls each 

// instruction cycle, effectively reducing the instruction count per clock to

// about 0.2.  However, the area cost may be worth it.  Consider:

//

//      Slice LUTs              ZipSystem       ZipCPU

//      Single Fetching         2521            1734

//      Pipelined fetching      2796            2046

//

// `define      OPT_SINGLE_FETCH

//

//

//

`define CPU_CC_REG      4'he

`define CPU_PC_REG      4'hf

`define CPU_TRAP_BIT    9

`define CPU_BREAK_BIT   7

`define CPU_STEP_BIT    6

`define CPU_GIE_BIT     5

`define CPU_SLEEP_BIT   4

// Compile time defines

// (Currently unused)

// `define      OPT_SINGLE_FETCH

// (Best path--define these!)

`define OPT_CONDITIONAL_FLAGS

`define OPT_ILLEGAL_INSTRUCTION

`ifndef OPT_SINGLE_FETCH

        // The following are pipeline optimization options.

        // They make no sense in a single instruction fetch mode.

`define OPT_PRECLEAR_BUS

`define OPT_EARLY_BRANCHING

`define OPT_PIPELINED_BUS_ACCESS

`endif

module  zipcpu(i_clk, i_rst, i_interrupt,

                // Debug interface

                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,

                        o_dbg_stall, o_dbg_reg, o_dbg_cc,

                        o_break,

                // CPU interface to the wishbone bus

                o_wb_gbl_cyc, o_wb_gbl_stb,

                        o_wb_lcl_cyc, o_wb_lcl_stb,

                        o_wb_we, o_wb_addr, o_wb_data,

                        i_wb_ack, i_wb_stall, i_wb_data,

                        i_wb_err,

                // Accounting/CPU usage interface

                o_op_stall, o_pf_stall, o_i_count);

        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,

                        LGICACHE=6, AW=ADDRESS_WIDTH;

        input                   i_clk, i_rst, i_interrupt;

        // Debug interface -- inputs

        input                   i_halt, i_clear_pf_cache;

        input           [4:0]    i_dbg_reg;

        input                   i_dbg_we;

        input           [31:0]   i_dbg_data;

        // Debug interface -- outputs

        output  reg             o_dbg_stall;

        output  reg     [31:0]   o_dbg_reg;

        output  reg     [1:0]    o_dbg_cc;

        output  wire            o_break;

        // Wishbone interface -- outputs

        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;

        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;

        output  wire    [(AW-1):0]       o_wb_addr;

        output  wire    [31:0]   o_wb_data;

        // Wishbone interface -- inputs

        input                   i_wb_ack, i_wb_stall;

        input           [31:0]   i_wb_data;

        input                   i_wb_err;

        // Accounting outputs ... to help us count stalls and usage

        output  wire            o_op_stall;

        output  wire            o_pf_stall;

        output  wire            o_i_count;

        // Registers

        reg     [31:0]   regset [0:31];

        // Condition codes

        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z

        wire    [10:0]   w_uflags, w_iflags;

        reg             trap, break_en, step, gie, sleep;

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg             ill_err;

`else

        wire            ill_err;

`endif

        reg             bus_err_flag;

        // The master chip enable

        wire            master_ce;

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //              Variable declarations

        //

        reg     [(AW-1):0]       pf_pc;

        reg             new_pc, op_break;

        wire    clear_pipeline;

        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;

        wire            dcd_stalled;

        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;

        wire    [(AW-1):0]       pf_addr;

        wire    [31:0]           pf_data;

        wire    [31:0]           instruction;

        wire    [(AW-1):0]       instruction_pc;

        wire    pf_valid, instruction_gie, pf_illegal;

        //

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Variable declarations

        //

        //

        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;

        wire            op_stall, dcd_ce;

        reg     [3:0]    dcdOp;

        reg     [4:0]    dcdA, dcdB;

        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;

        reg     [3:0]    dcdF;

        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,

                                dcdM, dcdF_wr, dcd_gie, dcd_break;

        reg     [(AW-1):0]       dcd_pc;

        reg     [23:0]   r_dcdI;

        reg             dcd_zI; // true if dcdI == 0

        wire    dcdA_stall, dcdB_stall, dcdF_stall;

`ifdef  OPT_PRECLEAR_BUS

        reg     dcd_clear_bus;

`endif

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg     dcd_illegal;

`endif

`ifdef  OPT_EARLY_BRANCHING

        reg                     dcd_early_branch_stb, dcd_early_branch;

        reg     [(AW-1):0]       dcd_branch_pc;

`else

        wire                    dcd_early_branch_stb, dcd_early_branch;

        wire    [(AW-1):0]       dcd_branch_pc;

`endif

        //

        //

        //      PIPELINE STAGE #3 :: Read Operands

        //              Variable declarations

        //

        //

        //

        // Now, let's read our operands

        reg     [4:0]    alu_reg;

        reg     [3:0]    opn;

        reg     [4:0]    opR;

        reg     [31:0]   r_opA, r_opB;

        reg     [(AW-1):0]       op_pc;

        wire    [31:0]   w_opA, w_opB;

        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;

        reg             opR_wr, opR_cc, opF_wr, op_gie,

                        opA_rd, opB_rd;

        wire    [10:0]   opFl;

        reg     [6:0]    r_opF;

        wire    [8:0]    opF;

        wire            op_ce;

`ifdef  OPT_PRECLEAR_BUS

        reg     op_clear_bus;

`endif

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg     op_illegal;

`endif

        //

        //

        //      PIPELINE STAGE #4 :: ALU / Memory

        //              Variable declarations

        //

        //

        reg     [(AW-1):0]       alu_pc;

        reg             alu_pc_valid;;

        wire            alu_ce, alu_stall;

        wire    [31:0]   alu_result;

        wire    [3:0]    alu_flags;

        wire            alu_valid;

        wire            set_cond;

        reg             alu_wr, alF_wr, alu_gie;

`ifdef  OPT_ILLEGAL_INSTRUCTION

        reg             alu_illegal;

`else

        wire            alu_illegal;

`endif

        wire    mem_ce, mem_stalled;

`ifdef  OPT_PIPELINED_BUS_ACCESS

        wire    mem_pipe_stalled;

`endif

        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,

                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;

        wire    [4:0]            mem_wreg;

        wire                    mem_busy, mem_rdbusy;

        wire    [(AW-1):0]       mem_addr;

        wire    [31:0]           mem_data, mem_result;

        reg     [4:0]            mem_last_reg; // Last register result to go in

        //

        //

        //      PIPELINE STAGE #5 :: Write-back

        //              Variable declarations

        //

        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;

        wire    [4:0]    wr_reg_id;

        wire    [31:0]   wr_reg_vl;

        wire    w_switch_to_interrupt, w_release_from_interrupt;

        reg     [(AW-1):0]       upc, ipc;

        //

        //      MASTER: clock enable.

        //

        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //              Calculate stall conditions

        //

        //      PIPELINE STAGE #2 :: Instruction Decode

        //              Calculate stall conditions

        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);

        assign          dcd_stalled = (dcdvalid)&&(

                                        (op_stall)

                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))

                                        ||((opvalid_mem)&&(op_wr_pc))

                                        ||((opvalid_mem)&&(opR_cc)));

        //

        //      PIPELINE STAGE #3 :: Read Operands

        //              Calculate stall conditions

        assign  op_stall = ((mem_stalled)&&(opvalid_mem))

                                ||((alu_stall)&&(opvalid_alu));

        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));

        //

        //      PIPELINE STAGE #4 :: ALU / Memory

        //              Calculate stall conditions

        //

        // 1. Basic stall is if the previous stage is valid and the next is

        //      busy.  

        // 2. Also stall if the prior stage is valid and the master clock enable

        //      is de-selected

        // 3. Next case: Stall if we want to start a memory operation and the

        //      prior operation will write either the PC or CC registers.

        // 4. Last case: Stall if we would otherwise move a break instruction

        //      through the ALU.  Break instructions are not allowed through

        //      the ALU.

        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2

                        ||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                &&((wr_write_pc)||(wr_write_cc))) // Case 3

                        ||((opvalid)&&(op_break)); // Case 4

        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);

        //

`ifdef  OPT_PIPELINED_BUS_ACCESS

        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)

                        &&(set_cond)&&(~mem_stalled);

        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(

                                (mem_pipe_stalled)

                                ||((~op_pipe)&&(mem_busy))

                                // Stall waiting for flags to be valid

                                // Or waiting for a write to the PC register

                                // Or CC register, since that can change the

                                //  PC as well

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)

                                        &&((wr_write_pc)||(wr_write_cc)))));

`else

        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);

        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(

                                (~master_ce)

                                // Stall waiting for flags to be valid

                                // Or waiting for a write to the PC register

                                // Or CC register, since that can change the

                                //  PC as well

                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));

`endif

        //

        //

        //      PIPELINE STAGE #1 :: Prefetch

        //

        //

`ifdef  OPT_SINGLE_FETCH

        wire            pf_ce;

        assign          pf_ce = (~dcd_stalled);

        prefetch        #(ADDRESS_WIDTH)

                        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,

                                instruction, instruction_pc, instruction_gie,

                                        pf_valid, pf_illegal,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                pf_ack, pf_stall, pf_err, i_wb_data);

`else // Pipe fetch

        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)

                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),

                                        i_clear_pf_cache, ~dcd_stalled,

                                        (new_pc)?pf_pc:dcd_branch_pc,

                                        instruction, instruction_pc, pf_valid,

                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,

                                        pf_ack, pf_stall, pf_err, i_wb_data,

`ifdef  OPT_PRECLEAR_BUS

                                ((dcd_clear_bus)&&(dcdvalid))

                                ||((op_clear_bus)&&(opvalid))

                                ||

`endif

                                (mem_cyc_lcl)||(mem_cyc_gbl),

                                pf_illegal);

        assign  instruction_gie = gie;

`endif

        initial dcdvalid = 1'b0;

        always @(posedge i_clk)

                if (i_rst)

                        dcdvalid <= 1'b0;

                else if (dcd_ce)

                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);

                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))

                        dcdvalid <= 1'b0;

`ifdef  OPT_EARLY_BRANCHING

        always @(posedge i_clk)

                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(~sleep))

                begin

                        dcd_early_branch <= 1'b0;

                        // First case, a move to PC instruction

                        if ((instruction[31:28] == 4'h2)

                                &&((instruction_gie)

                                        ||((~instruction[20])&&(~instruction[15])))

                                &&(instruction[23:21]==3'h0))

                        begin

                                dcd_early_branch_stb <= 1'b1;

                                dcd_early_branch <= 1'b1;

                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };

                        end else // Next case, an Add Imm -> PC instruction

                        if ((instruction[31:28] == 4'ha) // Add

                                &&(~instruction[20]) // Immediate

                                &&(instruction[23:21]==3'h0)) // Always

                        begin

                                dcd_early_branch_stb <= 1'b1;

                                dcd_early_branch <= 1'b1;

                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };

                        end else // Next case: load Immediate to PC

                        if (instruction[31:28] == 4'h3)

                        begin

                                dcd_early_branch_stb <= 1'b1;

                                dcd_early_branch <= 1'b1;

                                // r_dcdI <= { instruction[23:0] };

                        end

                end else

                begin

                        if (dcd_ce) dcd_early_branch <= 1'b0;

                        dcd_early_branch_stb <= 1'b0;

                end

        always @(posedge i_clk)

                if (dcd_ce)

                begin

                        if (instruction[31]) // Add

                                dcd_branch_pc <= instruction_pc+{ {(AW-20){instruction[19]}}, instruction[19:0] } + {{(AW-1){1'b0}},1'b1};

                        else if (~instruction[28]) // 4'h2 = MOV

                                dcd_branch_pc <= instruction_pc+{ {(AW-15){instruction[14]}}, instruction[14:0] } + {{(AW-1){1'b0}},1'b1};

                        else // if (instruction[28]) // 4'h3 = LDI

                                dcd_branch_pc <= instruction_pc+{ {(AW-24){instruction[23]}}, instruction[23:0] } + {{(AW-1){1'b0}},1'b1};

                end

`else   //      OPT_EARLY_BRANCHING

        assign  dcd_early_branch_stb = 1'b0;

        assign  dcd_early_branch     = 1'b0;

        assign  dcd_branch_pc        = {(AW){1'b0}};

`endif  //      OPT_EARLY_BRANCHING

        always @(posedge i_clk)

                if (dcd_ce)

                begin

                        dcd_pc <= instruction_pc+1;

                        // Record what operation we are doing

                        dcdOp <= instruction[31:28];

                        // Default values

                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };

                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };

                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);

                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);

                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);

                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);

                        dcdM    <= 1'b0;

`ifdef  OPT_CONDITIONAL_FLAGS

                        dcdF_wr <= (instruction[23:21]==3'h0);

`else

                        dcdF_wr <= 1'b1;

`endif

`ifdef  OPT_PRECLEAR_BUS

                        dcd_clear_bus <= 1'b0;

`endif

`ifdef  OPT_ILLEGAL_INSTRUCTION

                        dcd_illegal <= pf_illegal;

`endif

                        // Set the condition under which we do this operation

                        // The top four bits are a mask, the bottom four the

                        // value the flags must equal once anded with the mask

                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };

                        casez(instruction[31:28])

                        4'h2: begin // Move instruction

                                if (~instruction_gie)

                                begin

                                        dcdA[4] <= instruction[20];

                                        dcdB[4] <= instruction[15];

                                end

                                dcdA_wr <= 1'b1;

                                dcdA_rd <= 1'b0;

                                dcdB_rd <= 1'b1;

                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };

                                dcd_zI <= (instruction[14:0] == 0);

                                dcdF_wr <= 1'b0; // Don't write flags

                                end

                        4'h3: begin // Load immediate

                                dcdA_wr <= 1'b1;

                                dcdA_rd <= 1'b0;

                                dcdB_rd <= 1'b0;

                                r_dcdI <= { instruction[23:0] };

                                dcd_zI <= (instruction[23:0] == 0);

                                dcdF_wr <= 1'b0; // Don't write flags

                                dcdF    <= 4'h8; // This is unconditional

                                dcdOp <= 4'h2;

                                end

                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK

`ifdef  OPT_CONDITIONAL_FLAGS

                                // Don't write flags except for multiplies

                                //   and then only if they are unconditional

                                dcdF_wr <= ((instruction[27:25] != 3'h7)

                                        &&(instruction[23:21]==3'h0));

`else

                                // Don't write flags except for multiplies

                                dcdF_wr <= (instruction[27:25] != 3'h7);

`endif

                                r_dcdI <= { 8'h00, instruction[15:0] };

                                dcd_zI <= (instruction[15:0] == 0);

                                if (instruction[27:24] == 4'he)

                                begin

                                        // NOOP instruction

                                        dcdA_wr <= 1'b0;

                                        dcdA_rd <= 1'b0;

                                        dcdB_rd <= 1'b0;

                                        dcdOp <= 4'h2;

                                        // Might also be a break.  Big

                                        // instruction set hole here.

`ifdef  OPT_ILLEGAL_INSTRUCTION

                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);

`endif

                                end else if (instruction[27:24] == 4'hf)

                                begin // Load partial immediate(s)

                                        dcdA_wr <= 1'b1;

                                        dcdA_rd <= 1'b1;

                                        dcdB_rd <= 1'b0;

                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };

                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);

                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);

                                        dcdOp <= { 3'h3, instruction[20] };

                                end else begin

                                        // Actual multiply instruction

                                        r_dcdI <= { 8'h00, instruction[15:0] };

                                        dcd_zI <= (instruction[15:0] == 0);

                                        dcdA_rd <= 1'b1;

                                        dcdB_rd <= (instruction[19:16] != 4'hf);

                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;

                                end end

                        4'b011?: begin // Load/Store

                                dcdF_wr <= 1'b0; // Don't write flags

                                dcdA_wr <= (~instruction[28]); // Write on loads

                                dcdA_rd <= (instruction[28]); // Read on stores

                                dcdB_rd <= instruction[20];

                                if (instruction[20])

                                begin

                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };