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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: busdelay.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: Delay any access to the wishbone bus by a single clock.
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//
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// When the first Zip System would not meet the timing requirements of
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// the board it was placed upon, this bus delay was added to help out.
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// It may no longer be necessary, having cleaned some other problems up
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// first, but it will remain here as a means of alleviating timing
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// problems.
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//
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// The specific problem takes place on the stall line: a wishbone master
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// *must* know on the first clock whether or not the bus will stall.
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//
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//
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// After a period of time, I started a new design where the timing
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// associated with this original bus clock just wasn't ... fast enough.
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// I needed to delay the stall line as well. A new busdelay was then
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// written and debugged whcih delays the stall line. (I know, you aren't
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// supposed to delay the stall line--but what if you *have* to in order
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// to meet timing?) This new logic has been merged in with the old,
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// and the DELAY_STALL line can be set to non-zero to use it instead
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// of the original logic. Don't use it if you don't need it: it will
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// consume resources and slow your bus down more, but if you do need
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// it--don't be afraid to use it.
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//
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// Both versions of the bus delay will maintain a single access per
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// clock when pipelined, they only delay the time between the strobe
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// going high and the actual command being accomplished.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module busdelay(i_clk, i_reset,
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// The input bus
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
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// The delayed bus
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o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr,o_dly_data,o_dly_sel,
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i_dly_ack, i_dly_stall, i_dly_data, i_dly_err);
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parameter AW=32, DW=32;
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localparam F_LGDEPTH=4;
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parameter [0:0] DELAY_STALL = 1;
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input wire i_clk, i_reset;
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// Input/master bus
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input wire [(AW-1):0] i_wb_addr;
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input wire [(DW-1):0] i_wb_data;
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input wire [(DW/8-1):0] i_wb_sel;
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output reg o_wb_ack;
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output wire o_wb_stall;
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output reg [(DW-1):0] o_wb_data;
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output reg o_wb_err;
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// Delayed bus
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output reg o_dly_cyc, o_dly_stb, o_dly_we;
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output reg [(AW-1):0] o_dly_addr;
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output reg [(DW-1):0] o_dly_data;
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output reg [(DW/8-1):0] o_dly_sel;
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input wire i_dly_ack;
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input wire i_dly_stall;
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input wire [(DW-1):0] i_dly_data;
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input wire i_dly_err;
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`ifdef FORMAL
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wire [2+AW+DW+DW/8-1:0] f_wpending;
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`endif
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generate
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if (DELAY_STALL != 0)
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begin
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reg r_stb, r_we;
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reg [(AW-1):0] r_addr;
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reg [(DW-1):0] r_data;
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reg [(DW/8-1):0] r_sel;
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initial o_dly_cyc = 1'b0;
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initial o_dly_stb = 1'b0;
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initial o_dly_we = 1'b0;
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initial o_dly_addr = 0;
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initial o_dly_data = 0;
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initial o_dly_sel = 0;
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initial r_stb = 1'b0;
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initial r_we = 1'b0;
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initial r_addr = 0;
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initial r_data = 0;
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initial r_sel = 0;
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initial o_wb_ack = 1'b0;
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initial o_wb_err = 1'b0;
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always @(posedge i_clk)
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begin
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o_dly_cyc <= (i_wb_cyc)&&(!i_reset)&&(!o_wb_err)
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&&((!i_dly_err)||(!o_dly_cyc));
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if ((!i_dly_stall)||(!o_dly_stb))
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begin
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r_we <= i_wb_we;
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r_addr <= i_wb_addr;
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r_data <= i_wb_data;
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r_sel <= i_wb_sel;
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if (r_stb)
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begin
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o_dly_we <= r_we;
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o_dly_addr <= r_addr;
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o_dly_data <= r_data;
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o_dly_sel <= r_sel;
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o_dly_stb <= 1'b1;
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end else begin
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o_dly_we <= i_wb_we;
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o_dly_addr <= i_wb_addr;
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o_dly_data <= i_wb_data;
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o_dly_sel <= i_wb_sel;
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o_dly_stb <= i_wb_stb;
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end
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r_stb <= 1'b0;
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end else if ((!r_stb)&&(!o_wb_stall))
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begin
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r_we <= i_wb_we;
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r_addr <= i_wb_addr;
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r_data <= i_wb_data;
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r_sel <= i_wb_sel;
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r_stb <= i_wb_stb;
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end
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if ((!i_wb_cyc)||((i_dly_err)&&(o_dly_cyc))||(o_wb_err))
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begin
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o_dly_stb <= 1'b0;
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r_stb <= 1'b0;
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end
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if ((i_reset)||(!i_wb_cyc)||(o_wb_err))
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o_wb_ack <= 1'b0;
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else
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o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(!i_dly_err);
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o_wb_data <= i_dly_data;
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if (!i_wb_cyc)
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o_wb_err <= 1'b0;
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else
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o_wb_err <= (i_dly_err)&&(o_dly_cyc);
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if (i_reset)
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begin
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r_stb <= 0;
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r_we <= 0;
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o_dly_stb <= 0;
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o_wb_err <= 0;
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o_wb_ack <= 0;
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end
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end
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assign o_wb_stall = r_stb;
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`ifdef FORMAL
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assign f_wpending = { r_stb, r_we, r_addr, r_data, r_sel };
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`endif
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end else begin
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initial o_dly_cyc = 1'b0;
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initial o_dly_stb = 1'b0;
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initial o_dly_we = 1'b0;
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initial o_dly_addr = 0;
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initial o_dly_data = 0;
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initial o_dly_sel = 0;
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initial o_wb_ack = 0;
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initial o_wb_err = 0;
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always @(posedge i_clk)
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if (i_reset)
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o_dly_cyc <= 1'b0;
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else if ((i_dly_err)&&(o_dly_cyc))
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o_dly_cyc <= 1'b0;
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else if ((o_wb_err)&&(i_wb_cyc))
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o_dly_cyc <= 1'b0;
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else
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o_dly_cyc <= i_wb_cyc;
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// Add the i_wb_cyc criteria here, so we can simplify the
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// o_wb_stall criteria below, which would otherwise *and*
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// these two.
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always @(posedge i_clk)
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if (i_reset)
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o_dly_stb <= 1'b0;
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else if ((i_dly_err)&&(o_dly_cyc))
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o_dly_stb <= 1'b0;
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else if ((o_wb_err)&&(i_wb_cyc))
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o_dly_stb <= 1'b0;
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else if (!i_wb_cyc)
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o_dly_stb <= 1'b0;
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else if (!o_wb_stall)
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o_dly_stb <= (i_wb_stb);
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_dly_we <= i_wb_we;
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_dly_addr<= i_wb_addr;
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_dly_data <= i_wb_data;
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always @(posedge i_clk)
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if (!o_wb_stall)
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o_dly_sel <= i_wb_sel;
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always @(posedge i_clk)
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if (i_reset)
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o_wb_ack <= 1'b0;
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else
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o_wb_ack <= ((i_dly_ack)&&(!i_dly_err)
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&&(o_dly_cyc)&&(i_wb_cyc))
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&&(!o_wb_err);
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always @(posedge i_clk)
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if (i_reset)
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o_wb_err <= 1'b0;
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else if (!o_dly_cyc)
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o_wb_err <= 1'b0;
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else
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o_wb_err <= (o_wb_err)||(i_dly_err)&&(i_wb_cyc);
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always @(posedge i_clk)
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o_wb_data <= i_dly_data;
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// Our only non-delayed line, yet still really delayed. Perhaps
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// there's a way to register this?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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// assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc
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assign o_wb_stall = (i_dly_stall)&&(o_dly_stb);
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`ifdef FORMAL
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// f_wpending isn't used if DELAY_STALL is zero, but we'll give
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// it a seemingly useful value anyway--if for no other reason
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// than to be sure we set it to the right number of bits
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assign f_wpending = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel };
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`endif
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end endgenerate
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`ifdef FORMAL
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`ifdef BUSDELAY
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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initial `ASSUME(i_reset);
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always @(*)
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if (!f_past_valid)
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`ASSUME(i_reset);
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wire [(F_LGDEPTH-1):0] f_wb_nreqs,f_wb_nacks, f_wb_outstanding,
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f_dly_nreqs, f_dly_nacks, f_dly_outstanding;
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localparam ACK_DELAY = 5,
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STALL_DELAY = 4;
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fwb_slave #(.AW(AW), .DW(DW),
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.F_LGDEPTH(F_LGDEPTH),
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.F_MAX_STALL(STALL_DELAY+1),
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.F_MAX_ACK_DELAY(ACK_DELAY+1+2*STALL_DELAY),
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.F_MAX_REQUESTS((1<<F_LGDEPTH)-2),
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.F_OPT_RMW_BUS_OPTION(1),
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.F_OPT_DISCONTINUOUS(1))
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f_wbs(i_clk, i_reset,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_sel,
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o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
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f_wb_nreqs, f_wb_nacks, f_wb_outstanding);
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fwb_master #(.AW(AW), .DW(DW),
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.F_LGDEPTH(F_LGDEPTH),
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.F_MAX_STALL(STALL_DELAY),
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.F_MAX_ACK_DELAY(ACK_DELAY),
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.F_MAX_REQUESTS(0),
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.F_OPT_RMW_BUS_OPTION(1),
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.F_OPT_DISCONTINUOUS(1))
|
| 311 |
|
|
f_wbm(i_clk, i_reset,
|
| 312 |
|
|
o_dly_cyc, o_dly_stb, o_dly_we, o_dly_addr, o_dly_data,
|
| 313 |
|
|
o_dly_sel,
|
| 314 |
|
|
i_dly_ack, i_dly_stall, i_dly_data, i_dly_err,
|
| 315 |
|
|
f_dly_nreqs, f_dly_nacks, f_dly_outstanding);
|
| 316 |
|
|
|
| 317 |
|
|
wire [2+AW+DW+DW/8-1:0] f_wb_request, f_dly_request;
|
| 318 |
|
|
assign f_wb_request = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel };
|
| 319 |
|
|
assign f_dly_request={ o_dly_stb,o_dly_we,o_dly_addr,o_dly_data,o_dly_sel };
|
| 320 |
|
|
|
| 321 |
|
|
localparam STB_BIT = 2+AW+DW+DW/8-1;
|
| 322 |
|
|
reg [2+AW+DW+DW/8-1:0] f_pending;
|
| 323 |
|
|
initial f_pending = 0;
|
| 324 |
|
|
always @(posedge i_clk)
|
| 325 |
|
|
if (!DELAY_STALL)
|
| 326 |
|
|
f_pending = 0;
|
| 327 |
|
|
else if ((i_reset)||(!i_wb_cyc)||(i_dly_err))
|
| 328 |
|
|
f_pending[STB_BIT] <= 1'b0;
|
| 329 |
|
|
else if ((i_wb_stb)&&(!o_wb_stall))
|
| 330 |
|
|
begin
|
| 331 |
|
|
f_pending <= f_wb_request;
|
| 332 |
|
|
|
| 333 |
|
|
if ((!i_dly_stall)||(!o_dly_stb))
|
| 334 |
|
|
f_pending[STB_BIT] <= 1'b0;
|
| 335 |
|
|
|
| 336 |
|
|
end else if ((!i_dly_stall)&&(f_pending[STB_BIT]))
|
| 337 |
|
|
f_pending[STB_BIT] <= 1'b0;
|
| 338 |
|
|
|
| 339 |
|
|
wire f_wb_busy, f_dly_busy, f_wb_req, f_dly_req;
|
| 340 |
|
|
assign f_wb_busy = (i_wb_stb)&&(o_wb_stall);
|
| 341 |
|
|
assign f_dly_busy = (o_dly_stb)&&(i_dly_stall);
|
| 342 |
|
|
assign f_wb_req = (i_wb_stb)&&(!o_wb_stall);
|
| 343 |
|
|
assign f_dly_req = (o_dly_stb)&&(!i_dly_stall);
|
| 344 |
|
|
always @(posedge i_clk)
|
| 345 |
|
|
if (!DELAY_STALL)
|
| 346 |
|
|
begin
|
| 347 |
|
|
if ((f_past_valid)&&($past(f_wb_req))&&(!$past(i_reset))
|
| 348 |
|
|
&&(!$past(o_wb_err))&&(!o_wb_err))
|
| 349 |
|
|
assert(($past(f_wb_request) == f_dly_request));
|
| 350 |
|
|
if ((f_past_valid)&&($past(i_reset)))
|
| 351 |
|
|
assert(!o_dly_stb);
|
| 352 |
|
|
if ((f_past_valid)&&(!$past(i_wb_cyc)))
|
| 353 |
|
|
assert(!o_dly_stb);
|
| 354 |
|
|
if ((o_dly_stb)&&(i_dly_stall))
|
| 355 |
|
|
assert(o_wb_stall);
|
| 356 |
|
|
end else if ((DELAY_STALL)&&(f_past_valid))
|
| 357 |
|
|
begin
|
| 358 |
|
|
if ($past(i_reset))
|
| 359 |
|
|
assert(!f_pending[STB_BIT]);
|
| 360 |
|
|
if (!$past(f_dly_busy))
|
| 361 |
|
|
assert(!f_pending[STB_BIT]);
|
| 362 |
|
|
//
|
| 363 |
|
|
if (($past(i_reset))||($past(i_dly_err)))
|
| 364 |
|
|
begin
|
| 365 |
|
|
assert(!f_pending[STB_BIT]);
|
| 366 |
|
|
end else if ($past(f_wb_req))
|
| 367 |
|
|
begin
|
| 368 |
|
|
if ($past(f_dly_busy))
|
| 369 |
|
|
assert($past(f_wb_request) == f_pending);
|
| 370 |
|
|
end else if ((!$past(i_dly_stall))&&($past(f_pending[STB_BIT]))
|
| 371 |
|
|
&&($past(i_wb_cyc)))
|
| 372 |
|
|
begin
|
| 373 |
|
|
assert(f_dly_request == $past(f_pending));
|
| 374 |
|
|
end
|
| 375 |
|
|
end
|
| 376 |
|
|
|
| 377 |
|
|
// Constrain the induction solver: whatever's in our f_pending
|
| 378 |
|
|
// hold register should be identical to whatever is in the f_wpending
|
| 379 |
|
|
// wires above.
|
| 380 |
|
|
always @(posedge i_clk)
|
| 381 |
|
|
if ((DELAY_STALL)&&(f_past_valid)&&(!$past(i_reset)))
|
| 382 |
|
|
begin
|
| 383 |
|
|
if (!$past(i_wb_cyc))
|
| 384 |
|
|
assert((!f_pending[STB_BIT])
|
| 385 |
|
|
&&(!f_wpending[STB_BIT]));
|
| 386 |
|
|
else if (($past(f_dly_busy))&&($past(f_wb_busy)))
|
| 387 |
|
|
assert(f_pending == f_wpending);
|
| 388 |
|
|
else if(($past(f_dly_busy))&&($past(f_pending[STB_BIT])))
|
| 389 |
|
|
assert(f_pending == f_wpending);
|
| 390 |
|
|
end
|
| 391 |
|
|
|
| 392 |
|
|
always @(posedge i_clk)
|
| 393 |
|
|
if ((!DELAY_STALL)&&(f_past_valid)&&(!$past(i_reset))
|
| 394 |
|
|
&&($past(i_wb_stb))&&(!$past(o_wb_stall))
|
| 395 |
|
|
&&(!$past(o_wb_err))&&(!o_wb_err))
|
| 396 |
|
|
assert(f_dly_request == $past(f_wb_request));
|
| 397 |
|
|
|
| 398 |
|
|
always @(posedge i_clk)
|
| 399 |
|
|
if ((DELAY_STALL)&&(!i_reset)&&(!o_wb_err))
|
| 400 |
|
|
assert(f_pending[STB_BIT] == f_wpending[STB_BIT]);
|
| 401 |
|
|
|
| 402 |
|
|
// Upon any request at the input, there should always be a request
|
| 403 |
|
|
// on the output at the very next clock
|
| 404 |
|
|
always @(posedge i_clk)
|
| 405 |
|
|
if ((f_past_valid)&&($past(i_wb_stb))&&(i_wb_cyc))
|
| 406 |
|
|
assert((o_dly_stb)||(o_wb_err));
|
| 407 |
|
|
|
| 408 |
|
|
// Following any dropping of CYC or raising of RESET, STB should
|
| 409 |
|
|
// go down as well
|
| 410 |
|
|
always @(posedge i_clk)
|
| 411 |
|
|
if ((f_past_valid)&&(($past(!i_wb_cyc))||($past(i_reset))))
|
| 412 |
|
|
assert(!o_dly_stb);
|
| 413 |
|
|
|
| 414 |
|
|
always @(posedge i_clk)
|
| 415 |
|
|
if ((DELAY_STALL)&&(f_past_valid)
|
| 416 |
|
|
&&(!$past(i_reset))
|
| 417 |
|
|
&&($past(i_wb_cyc))
|
| 418 |
|
|
&&($past(f_pending[STB_BIT])))
|
| 419 |
|
|
begin
|
| 420 |
|
|
if ($past(i_dly_err))
|
| 421 |
|
|
assert(!o_dly_stb);
|
| 422 |
|
|
else
|
| 423 |
|
|
assert(o_dly_stb);
|
| 424 |
|
|
end
|
| 425 |
|
|
|
| 426 |
|
|
|
| 427 |
|
|
// Make sure we get no more than one ack per request
|
| 428 |
|
|
reg [(F_LGDEPTH-1):0] f_pending_acks;
|
| 429 |
|
|
always @(*)
|
| 430 |
|
|
if (DELAY_STALL)
|
| 431 |
|
|
begin
|
| 432 |
|
|
f_pending_acks <= 0;
|
| 433 |
|
|
if ((f_past_valid)
|
| 434 |
|
|
&&((o_wb_err)||(o_wb_ack))
|
| 435 |
|
|
&&(o_dly_cyc))
|
| 436 |
|
|
f_pending_acks <= 1;
|
| 437 |
|
|
end else
|
| 438 |
|
|
f_pending_acks <= (((o_wb_ack)||(o_wb_err)) ? 1:0);
|
| 439 |
|
|
|
| 440 |
|
|
reg [(F_LGDEPTH-1):0] f_pending_reqs;
|
| 441 |
|
|
always @(*)
|
| 442 |
|
|
if (DELAY_STALL)
|
| 443 |
|
|
begin
|
| 444 |
|
|
f_pending_reqs <= ((o_dly_stb) ? 1:0)
|
| 445 |
|
|
+ ((f_pending[STB_BIT]) ? 1:0);
|
| 446 |
|
|
end else begin
|
| 447 |
|
|
f_pending_reqs <= (!f_past_valid) ? 0 :
|
| 448 |
|
|
((o_dly_stb) ? 1:0);
|
| 449 |
|
|
end
|
| 450 |
|
|
|
| 451 |
|
|
reg [(F_LGDEPTH-1):0] f_expected, f_exp_nreqs, f_exp_nacks;
|
| 452 |
|
|
always @(*)
|
| 453 |
|
|
f_expected <= f_dly_outstanding + f_pending_reqs+f_pending_acks;
|
| 454 |
|
|
always @(*)
|
| 455 |
|
|
f_exp_nreqs<= f_dly_nreqs + f_pending_reqs;
|
| 456 |
|
|
always @(*)
|
| 457 |
|
|
f_exp_nacks<= f_dly_nacks - f_pending_acks;
|
| 458 |
|
|
always @(*)
|
| 459 |
|
|
if (i_wb_cyc)
|
| 460 |
|
|
assert(f_dly_outstanding <= f_wb_outstanding);
|
| 461 |
|
|
|
| 462 |
|
|
always @(posedge i_clk)
|
| 463 |
|
|
if ((!i_reset)&&(i_wb_cyc)&&(o_dly_cyc)&&(!i_dly_err))
|
| 464 |
|
|
assert(f_expected == f_wb_outstanding);
|
| 465 |
|
|
|
| 466 |
|
|
always @(posedge i_clk)
|
| 467 |
|
|
if ((i_wb_cyc)&&(o_dly_cyc)&&(!i_reset)&&(!i_dly_err))
|
| 468 |
|
|
begin
|
| 469 |
|
|
assert(f_exp_nreqs == f_wb_nreqs);
|
| 470 |
|
|
assert(f_exp_nacks == f_wb_nacks);
|
| 471 |
|
|
end
|
| 472 |
|
|
`endif
|
| 473 |
|
|
endmodule
|
