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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: wbdblpriarb.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: This should almost be identical to the priority arbiter, save
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// for a simple diffence: it allows the arbitration of two
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// separate wishbone buses. The purpose of this is to push the address
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// resolution back one cycle, so that by the first clock visible to this
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// core, it is known which of two parts of the bus the desired address
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// will be on, save that we still use the arbiter since the underlying
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// device doesn't know that there are two wishbone buses.
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//
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// So at this point we've deviated from the WB spec somewhat, by allowing
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// two CYC and two STB lines. Everything else is the same. This allows
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// (in this case the Zip CPU) to determine whether or not the access
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// will be to the local ZipSystem bus or the external WB bus on the clock
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// before the local bus access, otherwise peripherals were needing to do
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// multiple device selection comparisons/test within a clock: 1) is this
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// for the local or external bus, and 2) is this referencing me as a
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// peripheral. This then caused the ZipCPU to fail all timing specs.
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// By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the
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// determination of local vs external can be made one clock earlier
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// where there's still time for the logic, and the second comparison
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// now has time to complete.
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//
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// So let me try to explain this again. To use this arbiter, one of the
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// two masters sets CYC and STB before, only the master determines which
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// of two address spaces the CYC and STB apply to before the clock and
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// only sets the appropriate CYC and STB lines. Then, on the clock tick,
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// the arbiter determines who gets *both* busses, as they both share every
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// other WB line. Thus, only one of CYC_A and CYC_B going out will ever
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// be high at a given time.
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//
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// Hopefully this makes more sense than it sounds. If not, check out the
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// code below for a better explanation.
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//
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// 20150919 -- Added supported for the WB error signal.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2018-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module wbdblpriarb(i_clk, i_reset,
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// Bus A
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i_a_cyc_a,i_a_cyc_b,i_a_stb_a,i_a_stb_b,i_a_we,i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
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// Bus B
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i_b_cyc_a,i_b_cyc_b,i_b_stb_a,i_b_stb_b,i_b_we,i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
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// Both buses
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o_cyc_a, o_cyc_b, o_stb_a, o_stb_b, o_we, o_adr, o_dat, o_sel,
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i_ack, i_stall, i_err
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`ifdef FORMAL
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, f_nreqs_a, f_nacks_a, f_outstanding_a,
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f_nreqs_b, f_nacks_b, f_outstanding_b,
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f_a_nreqs_a, f_a_nacks_a, f_a_outstanding_a,
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f_a_nreqs_b, f_a_nacks_b, f_a_outstanding_b,
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f_b_nreqs_a, f_b_nacks_a, f_b_outstanding_a,
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f_b_nreqs_b, f_b_nacks_b, f_b_outstanding_b
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`endif
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);
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parameter DW=32, AW=32;
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//
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// ZERO_ON_IDLE uses more logic than the alternative. It should be
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// useful for reducing power, as these circuits tend to drive wires
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// all the way across the design, but it may also slow down the master
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// clock. I've used it as an option when using VERILATOR, 'cause
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// zeroing things on idle can make them stand out all the more when
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// staring at wires and dumps and such.
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parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0;
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//
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//
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parameter F_LGDEPTH = 3;
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//
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//
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parameter F_MAX_STALL = 0;
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parameter F_MAX_ACK_DELAY=0;
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//
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// Wishbone doesn't use an i_ce signal. While it could, they dislike
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// what it would (might) do to the synchronous reset signal, i_reset.
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input wire i_clk, i_reset;
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// Bus A
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input wire i_a_cyc_a, i_a_cyc_b, i_a_stb_a, i_a_stb_b, i_a_we;
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input wire [(AW-1):0] i_a_adr;
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input wire [(DW-1):0] i_a_dat;
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input wire [(DW/8-1):0] i_a_sel;
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output wire o_a_ack, o_a_stall, o_a_err;
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// Bus B
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input wire i_b_cyc_a, i_b_cyc_b, i_b_stb_a, i_b_stb_b, i_b_we;
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input wire [(AW-1):0] i_b_adr;
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input wire [(DW-1):0] i_b_dat;
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input wire [(DW/8-1):0] i_b_sel;
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output wire o_b_ack, o_b_stall, o_b_err;
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//
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output wire o_cyc_a,o_cyc_b, o_stb_a, o_stb_b, o_we;
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output wire [(AW-1):0] o_adr;
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output wire [(DW-1):0] o_dat;
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output wire [(DW/8-1):0] o_sel;
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input wire i_ack, i_stall, i_err;
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`ifdef FORMAL
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output wire [(F_LGDEPTH-1):0]
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f_nreqs_a, f_nacks_a, f_outstanding_a,
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f_nreqs_b, f_nacks_b, f_outstanding_b,
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f_a_nreqs_a, f_a_nacks_a, f_a_outstanding_a,
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f_a_nreqs_b, f_a_nacks_b, f_a_outstanding_b,
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f_b_nreqs_a, f_b_nacks_a, f_b_outstanding_a,
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f_b_nreqs_b, f_b_nacks_b, f_b_outstanding_b;
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`endif
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// All of our logic is really captured in the 'r_a_owner' register.
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// This register determines who owns the bus. If no one is requesting
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// the bus, ownership goes to A on the next clock. Otherwise, if B is
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// requesting the bus and A is not, then ownership goes to not A on
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// the next clock. (Sounds simple ...)
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//
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// The CYC logic is here to make certain that, by the time we determine
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// who the bus owner is, we can do so based upon determined criteria.
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reg r_a_owner;
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initial r_a_owner = 1'b1;
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always @(posedge i_clk)
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if (i_reset)
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r_a_owner <= 1'b1;
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/*
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// Remain with the "last owner" until 1) the other bus requests
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// access, and 2) the last owner no longer wants it. This
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// logic "idles" on the last owner.
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//
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// This is an alternating bus owner strategy
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//
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else if ((!o_cyc_a)&&(!o_cyc_b))
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r_a_owner <= ((i_b_stb_a)||(i_b_stb_b))? 1'b0:1'b1;
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//
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// Expanding this out
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//
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// else if ((r_a_owner)&&((i_a_cyc_a)||(i_a_cyc_b)))
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// r_a_owner <= 1'b1;
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// else if ((!r_a_owner)&&((i_b_cyc_a)||(i_b_cyc_b)))
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// r_a_owner <= 1'b0;
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// else if ((r_a_owner)&&((i_b_stb_a)||(i_b_stb_b)))
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// r_a_owner <= 1'b0;
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// else if ((!r_a_owner)&&((i_a_stb_a)||(i_a_stb_b)))
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// r_a_owner <= 1'b0;
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//
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// Logic required:
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//
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// Reset line
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// + 9 inputs (data)
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// + 9 inputs (CE)
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// Could be done with three LUTs
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// First two evaluate o_cyc_a and o_cyc_b (above)
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*/
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// Option 2:
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//
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// "Idle" on A as the owner.
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// If a request is made from B, AND A is idle, THEN
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// switch. Otherwise, if B is ever idle, revert back to A
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// regardless of whether A wants it or not.
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else if ((!i_b_cyc_a)&&(!i_b_cyc_b))
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r_a_owner <= 1'b1;
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else if ((!i_a_cyc_a)&&(!i_a_cyc_b)
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&&((i_b_stb_a)||(i_b_stb_b)))
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r_a_owner <= 1'b0;
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// Realistically, if neither master owns the bus, the output is a
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// don't care. Thus we trigger off whether or not 'A' owns the bus.
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// If 'B' owns it all we care is that 'A' does not. Likewise, if
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// neither owns the bus than the values on these various lines are
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// irrelevant.
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assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a);
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assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b);
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assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a;
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assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b;
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assign o_we = (r_a_owner) ? i_a_we : i_b_we;
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generate if (OPT_ZERO_ON_IDLE)
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begin
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wire o_cyc, o_stb;
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assign o_cyc = ((o_cyc_a)||(o_cyc_b));
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assign o_stb = ((o_stb_a)||(o_stb_b));
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assign o_adr = (o_stb)?((r_a_owner) ? i_a_adr : i_b_adr):0;
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assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0;
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assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0;
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assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0;
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assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
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assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
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end else begin
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assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr;
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assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat;
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assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel;
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// We cannot allow the return acknowledgement to ever go high if
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// the master in question does not own the bus. Hence we force it
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// low if the particular master doesn't own the bus.
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assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0;
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// Stall must be asserted on the same cycle the input master asserts
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// the bus, if the bus isn't granted to him.
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assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
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//
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//
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assign o_a_err = ( r_a_owner) ? i_err : 1'b0;
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assign o_b_err = (!r_a_owner) ? i_err : 1'b0;
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end endgenerate
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`ifdef FORMAL
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`define ASSERT assert
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`ifdef WBDBLPRIARB
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`define ASSUME assume
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`else
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`define ASSUME assert
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`endif
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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initial `ASSUME(i_reset);
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always @(*)
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if (!f_past_valid)
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`ASSUME(i_reset);
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initial `ASSUME(!i_a_cyc_a);
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initial `ASSUME(!i_a_stb_a);
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initial `ASSUME(!i_a_cyc_b);
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initial `ASSUME(!i_a_stb_b);
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initial `ASSUME(!i_b_cyc_a);
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initial `ASSUME(!i_b_stb_a);
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initial `ASSUME(!i_b_cyc_b);
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initial `ASSUME(!i_b_stb_b);
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initial `ASSUME(!i_ack);
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initial `ASSUME(!i_err);
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always @(*)
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`ASSUME((!i_a_cyc_a)||(!i_a_cyc_b));
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always @(*)
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`ASSUME((!i_b_cyc_a)||(!i_b_cyc_b));
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_a_cyc_a)))
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`ASSUME(!i_a_cyc_b);
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| 280 |
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|
|
| 281 |
|
|
always @(posedge i_clk)
|
| 282 |
|
|
if ((f_past_valid)&&($past(i_a_cyc_b)))
|
| 283 |
|
|
`ASSUME(!i_a_cyc_a);
|
| 284 |
|
|
|
| 285 |
|
|
always @(posedge i_clk)
|
| 286 |
|
|
if ((f_past_valid)&&($past(i_b_cyc_a)))
|
| 287 |
|
|
`ASSUME(!i_b_cyc_b);
|
| 288 |
|
|
|
| 289 |
|
|
always @(posedge i_clk)
|
| 290 |
|
|
if ((f_past_valid)&&($past(i_b_cyc_b)))
|
| 291 |
|
|
`ASSUME(!i_b_cyc_a);
|
| 292 |
|
|
|
| 293 |
|
|
wire f_cyc, f_stb;
|
| 294 |
|
|
assign f_cyc = (o_cyc_a)||(o_cyc_b);
|
| 295 |
|
|
assign f_stb = (o_stb_a)||(o_stb_b);
|
| 296 |
|
|
always @(posedge i_clk)
|
| 297 |
|
|
begin
|
| 298 |
|
|
if (o_cyc_a)
|
| 299 |
|
|
`ASSERT((i_a_cyc_a)||(i_b_cyc_a));
|
| 300 |
|
|
if (o_cyc_b)
|
| 301 |
|
|
`ASSERT((i_a_cyc_b)||(i_b_cyc_b));
|
| 302 |
|
|
`ASSERT((!o_cyc_a)||(!o_cyc_b));
|
| 303 |
|
|
end
|
| 304 |
|
|
|
| 305 |
|
|
always @(posedge i_clk)
|
| 306 |
|
|
if ((f_past_valid)&&(!$past(i_reset)))
|
| 307 |
|
|
begin
|
| 308 |
|
|
if ($past(f_cyc))
|
| 309 |
|
|
begin
|
| 310 |
|
|
if (($past(o_cyc_a))&&(o_cyc_a))
|
| 311 |
|
|
`ASSERT($past(r_a_owner) == r_a_owner);
|
| 312 |
|
|
if (($past(o_cyc_b))&&(o_cyc_b))
|
| 313 |
|
|
`ASSERT($past(r_a_owner) == r_a_owner);
|
| 314 |
|
|
end else begin
|
| 315 |
|
|
if (($past(i_a_stb_a))||($past(i_a_stb_b)))
|
| 316 |
|
|
`ASSERT(r_a_owner);
|
| 317 |
|
|
if (($past(i_b_stb_a))||($past(i_b_stb_b)))
|
| 318 |
|
|
`ASSERT(!r_a_owner);
|
| 319 |
|
|
end
|
| 320 |
|
|
end
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
fwb_master #(.AW(AW), .DW(DW),
|
| 324 |
|
|
.F_MAX_STALL(F_MAX_STALL),
|
| 325 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
| 326 |
|
|
.F_MAX_ACK_DELAY(F_MAX_ACK_DELAY),
|
| 327 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 328 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 329 |
|
|
f_wbm_a(i_clk, i_reset,
|
| 330 |
|
|
o_cyc_a, o_stb_a, o_we, o_adr, o_dat, o_sel,
|
| 331 |
|
|
(o_cyc_a)&&(i_ack), i_stall, 32'h0, (o_cyc_a)&&(i_err),
|
| 332 |
|
|
f_nreqs_a, f_nacks_a, f_outstanding_a);
|
| 333 |
|
|
fwb_master #(.AW(AW), .DW(DW),
|
| 334 |
|
|
.F_MAX_STALL(F_MAX_STALL),
|
| 335 |
|
|
.F_MAX_ACK_DELAY(F_MAX_ACK_DELAY),
|
| 336 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
| 337 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 338 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 339 |
|
|
f_wbm_b(i_clk, i_reset,
|
| 340 |
|
|
o_cyc_b, o_stb_b, o_we, o_adr, o_dat, o_sel,
|
| 341 |
|
|
(o_cyc_b)&&(i_ack), i_stall, 32'h0, (o_cyc_b)&&(i_err),
|
| 342 |
|
|
f_nreqs_b, f_nacks_b, f_outstanding_b);
|
| 343 |
|
|
|
| 344 |
|
|
`ifdef WBDBLPRIARB
|
| 345 |
|
|
`define F_SLAVE fwb_slave
|
| 346 |
|
|
`else
|
| 347 |
|
|
`define F_SLAVE fwb_counter
|
| 348 |
|
|
`endif
|
| 349 |
|
|
|
| 350 |
|
|
`F_SLAVE #(.AW(AW), .DW(DW), .F_MAX_STALL(0),
|
| 351 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
| 352 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 353 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 354 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 355 |
|
|
f_wba_a(i_clk, i_reset,
|
| 356 |
|
|
i_a_cyc_a, i_a_stb_a, i_a_we, i_a_adr, i_a_dat, i_a_sel,
|
| 357 |
|
|
(o_cyc_a)&&(o_a_ack), o_a_stall, 32'h0, (o_cyc_a)&&(o_a_err),
|
| 358 |
|
|
f_a_nreqs_a, f_a_nacks_a, f_a_outstanding_a);
|
| 359 |
|
|
`F_SLAVE #(.AW(AW), .DW(DW), .F_MAX_STALL(0),
|
| 360 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
| 361 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 362 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 363 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 364 |
|
|
f_wba_b(i_clk, i_reset,
|
| 365 |
|
|
i_a_cyc_b, i_a_stb_b, i_a_we, i_a_adr, i_a_dat, i_a_sel,
|
| 366 |
|
|
(o_cyc_b)&&(o_a_ack), o_a_stall, 32'h0, (o_cyc_b)&&(o_a_err),
|
| 367 |
|
|
f_a_nreqs_b, f_a_nacks_b, f_a_outstanding_b);
|
| 368 |
|
|
`F_SLAVE #(.AW(AW), .DW(DW), .F_MAX_STALL(0),
|
| 369 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
| 370 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 371 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 372 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 373 |
|
|
f_wbb_a(i_clk, i_reset,
|
| 374 |
|
|
i_b_cyc_a, i_b_stb_a, i_b_we, i_b_adr, i_b_dat, i_b_sel,
|
| 375 |
|
|
(o_cyc_a)&&(o_b_ack), o_b_stall, 32'h0, (o_cyc_a)&&(o_b_err),
|
| 376 |
|
|
f_b_nreqs_a, f_b_nacks_a, f_b_outstanding_a);
|
| 377 |
|
|
`F_SLAVE #(.AW(AW), .DW(DW), .F_MAX_STALL(0),
|
| 378 |
|
|
.F_LGDEPTH(F_LGDEPTH),
|
| 379 |
|
|
.F_MAX_ACK_DELAY(0),
|
| 380 |
|
|
.F_OPT_RMW_BUS_OPTION(1),
|
| 381 |
|
|
.F_OPT_DISCONTINUOUS(1))
|
| 382 |
|
|
f_wbb_b(i_clk, i_reset,
|
| 383 |
|
|
i_b_cyc_b, i_b_stb_b, i_b_we, i_b_adr, i_b_dat, i_b_sel,
|
| 384 |
|
|
(o_cyc_b)&&(o_b_ack), o_b_stall, 32'h0, (o_cyc_b)&&(o_b_err),
|
| 385 |
|
|
f_b_nreqs_b, f_b_nacks_b, f_b_outstanding_b);
|
| 386 |
|
|
|
| 387 |
|
|
always @(posedge i_clk)
|
| 388 |
|
|
if ((f_past_valid)&&(!$past(i_reset)))
|
| 389 |
|
|
begin
|
| 390 |
|
|
if (r_a_owner)
|
| 391 |
|
|
begin
|
| 392 |
|
|
`ASSERT(f_b_nreqs_a == 0);
|
| 393 |
|
|
`ASSERT(f_b_nreqs_b == 0);
|
| 394 |
|
|
//
|
| 395 |
|
|
`ASSERT(f_b_nacks_a == 0);
|
| 396 |
|
|
`ASSERT(f_b_nacks_b == 0);
|
| 397 |
|
|
//
|
| 398 |
|
|
if (i_a_cyc_a)
|
| 399 |
|
|
begin
|
| 400 |
|
|
`ASSERT(f_a_outstanding_a == f_outstanding_a);
|
| 401 |
|
|
`ASSERT(f_a_outstanding_b == 0);
|
| 402 |
|
|
`ASSERT(f_outstanding_b == 0);
|
| 403 |
|
|
`ASSERT(f_a_nreqs_b == 0);
|
| 404 |
|
|
`ASSERT(f_a_nacks_b == 0);
|
| 405 |
|
|
end else if (i_a_cyc_b)
|
| 406 |
|
|
begin
|
| 407 |
|
|
`ASSERT(f_a_outstanding_b == f_outstanding_b);
|
| 408 |
|
|
`ASSERT(f_a_outstanding_a == 0);
|
| 409 |
|
|
`ASSERT(f_outstanding_a == 0);
|
| 410 |
|
|
`ASSERT(f_a_nreqs_a == 0);
|
| 411 |
|
|
`ASSERT(f_a_nacks_a == 0);
|
| 412 |
|
|
end
|
| 413 |
|
|
end else begin
|
| 414 |
|
|
`ASSERT(f_a_nreqs_a == 0);
|
| 415 |
|
|
`ASSERT(f_a_nreqs_b == 0);
|
| 416 |
|
|
//
|
| 417 |
|
|
`ASSERT(f_a_nacks_a == 0);
|
| 418 |
|
|
`ASSERT(f_a_nacks_b == 0);
|
| 419 |
|
|
//
|
| 420 |
|
|
if (i_b_cyc_a)
|
| 421 |
|
|
begin
|
| 422 |
|
|
`ASSERT(f_b_outstanding_a == f_outstanding_a);
|
| 423 |
|
|
`ASSERT(f_b_outstanding_b == 0);
|
| 424 |
|
|
`ASSERT(f_outstanding_b == 0);
|
| 425 |
|
|
`ASSERT(f_b_nreqs_b == 0);
|
| 426 |
|
|
`ASSERT(f_b_nacks_b == 0);
|
| 427 |
|
|
end else if (i_b_cyc_b)
|
| 428 |
|
|
begin
|
| 429 |
|
|
`ASSERT(f_b_outstanding_b == f_outstanding_b);
|
| 430 |
|
|
`ASSERT(f_b_outstanding_a == 0);
|
| 431 |
|
|
`ASSERT(f_outstanding_a == 0);
|
| 432 |
|
|
`ASSERT(f_b_nreqs_a == 0);
|
| 433 |
|
|
`ASSERT(f_b_nacks_a == 0);
|
| 434 |
|
|
end
|
| 435 |
|
|
end
|
| 436 |
|
|
end
|
| 437 |
|
|
|
| 438 |
|
|
always @(posedge i_clk)
|
| 439 |
|
|
if ((r_a_owner)&&(i_b_cyc_a))
|
| 440 |
|
|
`ASSUME((i_b_stb_a)&&(!i_b_stb_b));
|
| 441 |
|
|
always @(posedge i_clk)
|
| 442 |
|
|
if ((r_a_owner)&&(i_b_cyc_b))
|
| 443 |
|
|
`ASSUME((i_b_stb_b)&&(!i_b_stb_a));
|
| 444 |
|
|
|
| 445 |
|
|
always @(posedge i_clk)
|
| 446 |
|
|
if ((!r_a_owner)&&(i_a_cyc_a))
|
| 447 |
|
|
`ASSUME((i_a_stb_a)&&(!i_a_stb_b));
|
| 448 |
|
|
always @(posedge i_clk)
|
| 449 |
|
|
if ((!r_a_owner)&&(i_a_cyc_b))
|
| 450 |
|
|
`ASSUME((i_a_stb_b)&&(!i_a_stb_a));
|
| 451 |
|
|
|
| 452 |
|
|
`endif
|
| 453 |
|
|
endmodule
|
| 454 |
|
|
|
