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///////////////////////////////////////////////////////////////////////////

//

// Filename:    zipsystem.v

//

// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

//

// Purpose:     This portion of the ZIP CPU implements a number of soft

//              peripherals to the CPU nearby its CORE.  The functionality

//              sits on the data bus, and does not include any true

//              external hardware peripherals.  The peripherals included here

//              include:

//

//

//      Local interrupt controller--for any/all of the interrupts generated

//              here.  This would include a pin for interrupts generated

//              elsewhere, so this interrupt controller could be a master

//              handling all interrupts.  My interrupt controller would work

//              for this purpose.

//

//              The ZIP-CPU supports only one interrupt because, as I understand

//              modern systems (Linux), they tend to send all interrupts to the

//              same interrupt vector anyway.  Hence, that's what we do here.

//

//      Bus Error interrupts -- generates an interrupt any time the wishbone

//              bus produces an error on a given access, for whatever purpose

//              also records the address on the bus at the time of the error.

//

//      Trap instructions

//              Writing to this "register" will always create an interrupt.

//              After the interrupt, this register may be read to see what

//              value had been written to it.

//

//      Bit reverse register ... ?

//

//      (Potentially an eventual floating point co-processor ...)

//

//      Real-time clock

//

//      Interval timer(s) (Count down from fixed value, and either stop on

//              zero, or issue an interrupt and restart automatically on zero)

//              These can be implemented as watchdog timers if desired--the

//              only difference is that a watchdog timer's interrupt feeds the

//              reset line instead of the processor interrupt line.

//

//      Watch-dog timer: this is the same as an interval timer, only it's

//              interrupt/time-out line is wired to the reset line instead of

//              the interrupt line of the CPU.

//

//      ROM Memory map

//              Set a register to control this map, and a DMA will begin to

//              fill this memory from a slower FLASH.  Once filled, accesses

//              will be from this memory instead of 

//

//

//      Doing some market comparison, let's look at what peripherals a TI

//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,

//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,

//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,

//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,

//      watchdog-timers,

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Tecnology, LLC

//

///////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2015, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

///////////////////////////////////////////////////////////////////////////

//

// While I hate adding delays to any bus access, these two are required

// to make timing close in my Basys-3 design.

`define DELAY_EXT_BUS

`define DELAY_DBG_BUS

//

//

// Now, where am I placing all of my peripherals?

`define PERIPHBASE      32'hc0000000

`define INTCTRL         4'h0    // 

`define WATCHDOG        4'h1    // Interrupt generates reset signal

`define CACHECTRL       4'h2    // Sets IVEC[0]

`define CTRINT          4'h3    // Sets IVEC[5]

`define TIMER_A         4'h4    // Sets IVEC[4]

`define TIMER_B         4'h5    // Sets IVEC[3]

`define TIMER_C         4'h6    // Sets IVEC[2]

`define JIFFIES         4'h7    // Sets IVEC[1]

`define MSTR_TASK_CTR   4'h8

`define MSTR_MSTL_CTR   4'h9

`define MSTR_PSTL_CTR   4'ha

`define MSTR_ASTL_CTR   4'hb

`define USER_TASK_CTR   4'hc

`define USER_MSTL_CTR   4'hd

`define USER_PSTL_CTR   4'he

`define USER_ASTL_CTR   4'hf

`define CACHEBASE       16'hc010        //

// `define      RTC_CLOCK       32'hc0000008    // A global something

// `define      BITREV          32'hc0000003

//

//      DBGCTRL

//              10 HALT

//               9 HALT(ED)

//               8 STEP (W=1 steps, and returns to halted)

//               7 INTERRUPT-FLAG

//               6 RESET_FLAG

//              ADDRESS:

//               5      PERIPHERAL-BIT

//              [4:0]   REGISTER-ADDR

//      DBGDATA

//              read/writes internal registers

module  zipsystem(i_clk, i_rst,

                // Wishbone master interface from the CPU

                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,

                        i_wb_ack, i_wb_stall, i_wb_data,

                // Incoming interrupts

                i_ext_int,

                // Wishbone slave interface for debugging purposes

                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,

                        o_dbg_ack, o_dbg_stall, o_dbg_data);

        parameter       RESET_ADDRESS=32'h0100000;

        input   i_clk, i_rst;

        // Wishbone master

        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;

        output  wire    [31:0]   o_wb_addr;

        output  wire    [31:0]   o_wb_data;

        input                   i_wb_ack, i_wb_stall;

        input           [31:0]   i_wb_data;

        // Incoming interrupts

        input                   i_ext_int;

        // Wishbone slave

        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;

        input           [31:0]   i_dbg_data;

        output  wire            o_dbg_ack;

        output  wire            o_dbg_stall;

        output  wire    [31:0]   o_dbg_data;

        wire    [31:0]   ext_idata;

        // Delay the debug port by one clock, to meet timing requirements

        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;

        wire    [31:0]   dbg_idata, dbg_odata;

        reg             dbg_ack;

`ifdef  DELAY_DBG_BUS

        busdelay #(1,32) wbdelay(i_clk,

                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,

                        o_dbg_ack, o_dbg_stall, o_dbg_data,

                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,

                        dbg_ack, dbg_stall, dbg_odata);

`else

        assign  dbg_cyc     = i_dbg_cyc;

        assign  dbg_stb     = i_dbg_stb;

        assign  dbg_we      = i_dbg_we;

        assign  dbg_addr    = i_dbg_addr;

        assign  dbg_idata   = i_dbg_data;

        assign  o_dbg_ack   = dbg_ack;

        assign  o_dbg_stall = dbg_stall;

        assign  o_dbg_data  = dbg_odata;

`endif

        // 

        //

        //

        wire    sys_cyc, sys_stb, sys_we;

        wire    [3:0]    sys_addr;

        wire    [31:0]   cpu_addr;

        wire    [31:0]   sys_data;

        // wire         sys_ack, sys_stall;

        //

        // The external debug interface

        //

        // We offer only a limited interface here, requiring a pre-register

        // write to set the local address.  This interface allows access to

        // the Zip System on a debug basis only, and not to the rest of the

        // wishbone bus.  Further, to access these registers, the control

        // register must first be accessed to both stop the CPU and to 

        // set the following address in question.  Hence all accesses require

        // two accesses: write the address to the control register (and halt

        // the CPU if not halted), then read/write the data from the data

        // register.

        //

        wire            cpu_break, dbg_cmd_write;

        reg             cmd_reset, cmd_halt, cmd_step;

        reg     [5:0]    cmd_addr;

        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);

        //

        initial cmd_reset = 1'b1;

        always @(posedge i_clk)

                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));

        //

        initial cmd_halt  = 1'b1;

        always @(posedge i_clk)

                if (i_rst)

                        cmd_halt <= 1'b1;

                else if (dbg_cmd_write)

                        cmd_halt <= dbg_idata[10];

                else if ((cmd_step)||(cpu_break))

                        cmd_halt  <= 1'b1;

        //

        initial cmd_step  = 1'b0;

        always @(posedge i_clk)

                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);

        //

        always @(posedge i_clk)

                if (dbg_cmd_write)

                        cmd_addr <= dbg_idata[5:0];

        wire    cpu_reset;

        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);

        wire    cpu_halt, cpu_dbg_stall;

        assign  cpu_halt = (cmd_halt)&&(~cmd_step);

        wire    [31:0]   pic_data;

        wire    [31:0]   cmd_data;

        assign  cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15],

                        cpu_reset, cmd_addr };

`ifdef  USE_TRAP

        //

        // The TRAP peripheral

        //

        wire            trap_ack, trap_stall, trap_int;

        wire    [31:0]   trap_data;

        ziptrap trapp(i_clk,

                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,

                                sys_data,

                                trap_ack, trap_stall, trap_data, trap_int);

`endif

        //

        // The WATCHDOG Timer

        //

        wire            wdt_ack, wdt_stall, wdt_reset;

        wire    [31:0]   wdt_data;

        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,

                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,

                                sys_data,

                        wdt_ack, wdt_stall, wdt_data, wdt_reset);

        //

        // The Flash Cache, a pre-read cache to memory that can be used to

        // create a fast memory access area

        //

        wire            cache_int;

        wire    [31:0]   cache_data;

        wire            cache_stb, cache_ack, cache_stall;

        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;

        wire    [31:0]   fc_data, fc_addr;

        flashcache      #(10) manualcache(i_clk,

                                sys_cyc, cache_stb,

                                ((sys_stb)&&(sys_addr == `CACHECTRL)),

                                sys_we, cpu_addr[9:0], sys_data,

                                        cache_ack, cache_stall, cache_data,

                                // Need the outgoing CACHE wishbone bus

                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,

                                        fc_ack, fc_stall, ext_idata,

                                // Cache interrupt, for upon completion

                                cache_int);

        // Counters -- for performance measurement and accounting

        //

        // Here's the stuff we'll be counting ....

        //

        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;

        //

        // The master counters will, in general, not be reset.  They'll be used

        // for an overall counter.

        //

        // Master task counter

        wire            mtc_ack, mtc_stall, mtc_int;

        wire    [31:0]   mtc_data;

        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,

                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),

                                        sys_we, sys_data,

                                mtc_ack, mtc_stall, mtc_data, mtc_int);

        // Master Operand Stall counter

        wire            moc_ack, moc_stall, moc_int;

        wire    [31:0]   moc_data;

        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,

                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),

                                        sys_we, sys_data,

                                moc_ack, moc_stall, moc_data, moc_int);

        // Master PreFetch-Stall counter

        wire            mpc_ack, mpc_stall, mpc_int;

        wire    [31:0]   mpc_data;

        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,

                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),

                                        sys_we, sys_data,

                                mpc_ack, mpc_stall, mpc_data, mpc_int);

        // Master Instruction counter

        wire            mic_ack, mic_stall, mic_int;

        wire    [31:0]   mic_data;

        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,

                                (sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),

                                        sys_we, sys_data,

                                mic_ack, mic_stall, mic_data, mic_int);

        //

        // The user counters are different from those of the master.  They will

        // be reset any time a task is given control of the CPU.

        //

        // User task counter

        wire            utc_ack, utc_stall, utc_int;

        wire    [31:0]   utc_data;

        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,

                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),

                                        sys_we, sys_data,

                                utc_ack, utc_stall, utc_data, utc_int);

        // User Op-Stall counter

        wire            uoc_ack, uoc_stall, uoc_int;

        wire    [31:0]   uoc_data;

        zipcounter      umstall_ctr(i_clk,(cpu_op_stall), sys_cyc,

                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),

                                        sys_we, sys_data,

                                uoc_ack, uoc_stall, uoc_data, uoc_int);

        // User PreFetch-Stall counter

        wire            upc_ack, upc_stall, upc_int;

        wire    [31:0]   upc_data;

        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,

                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),

                                        sys_we, sys_data,

                                upc_ack, upc_stall, upc_data, upc_int);

        // User instruction counter

        wire            uic_ack, uic_stall, uic_int;

        wire    [31:0]   uic_data;

        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,

                                (sys_stb)&&(sys_addr == `USER_ASTL_CTR),

                                        sys_we, sys_data,

                                uic_ack, uic_stall, uic_data, uic_int);

        // A little bit of pre-cleanup (actr = accounting counters)

        wire            actr_ack, actr_stall;

        wire    [31:0]   actr_data;

        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)

                                |(utc_ack | uoc_ack | upc_ack | uic_ack));

        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)

                                |(utc_stall | uoc_stall | upc_stall|uic_stall));

        assign  actr_data = ((mtc_ack) ? mtc_data

                                : ((moc_ack) ? moc_data

                                : ((mpc_ack) ? mpc_data

                                : ((mic_ack) ? mic_data

                                : ((utc_ack) ? utc_data

                                : ((uoc_ack) ? uoc_data

                                : ((upc_ack) ? upc_data

                                : uic_data)))))));

        //

        // Counter Interrupt controller

        //

        reg             ctri_ack;

        wire            ctri_stall, ctri_int, ctri_sel;

        wire    [7:0]    ctri_vector;

        wire    [31:0]   ctri_data;

        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);

        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,

                                        utc_int, uoc_int, upc_int, uic_int };

        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),

                                sys_data, ctri_data, ctri_vector, ctri_int);

        always @(posedge i_clk)

                ctri_ack <= ctri_sel;

        //

        // Timer A

        //

        wire            tma_ack, tma_stall, tma_int;

        wire    [31:0]   tma_data;

        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,

                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,

                                sys_data,

                        tma_ack, tma_stall, tma_data, tma_int);

        //

        // Timer B

        //

        wire            tmb_ack, tmb_stall, tmb_int;

        wire    [31:0]   tmb_data;

        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,

                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,

                                sys_data,

                        tmb_ack, tmb_stall, tmb_data, tmb_int);

        //

        // Timer C

        //

        wire            tmc_ack, tmc_stall, tmc_int;

        wire    [31:0]   tmc_data;

        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,

                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,

                                sys_data,

                        tmc_ack, tmc_stall, tmc_data, tmc_int);

        //

        // JIFFIES

        //

        wire            jif_ack, jif_stall, jif_int;

        wire    [31:0]   jif_data;

        zipjiffies jiffies(i_clk, ~cmd_halt,

                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,

                                sys_data,

                        jif_ack, jif_stall, jif_data, jif_int);

        //

        // The programmable interrupt controller peripheral

        //

        wire            pic_interrupt;

        wire    [6:0]    int_vector;

        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,

                                        jif_int, cache_int };

        icontrol #(7)   pic(i_clk, cpu_reset,

                                (sys_cyc)&&(sys_stb)&&(sys_we)

                                        &&(sys_addr==`INTCTRL),

                                sys_data, pic_data,

                                int_vector, pic_interrupt);

        reg     pic_ack;

        always @(posedge i_clk)

                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);

        //

        // The CPU itself

        //

        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;

        wire    [31:0]   cpu_data, wb_data;

        wire            cpu_ack, cpu_stall;

        wire    [31:0]   cpu_dbg_data;

        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])

                                        &&(dbg_we)&&(dbg_addr));

        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,

                        cpu_halt, cmd_addr[4:0], cpu_dbg_we,

                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,

                                cpu_break,

                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,

                                cpu_ack, cpu_stall, wb_data,

                        cpu_op_stall, cpu_pf_stall, cpu_i_count);

        // Now, arbitrate the bus ... first for the local peripherals

        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));

        assign  sys_stb = (cpu_cyc)

                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))

                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));

        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;

        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];

        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;

        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));

        // Return debug response values

        assign  dbg_odata = (~dbg_addr)?cmd_data

                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);

        initial dbg_ack = 1'b0;

        always @(posedge i_clk)

                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&

                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));

        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)

                                &&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));

        // Now for the external wishbone bus

        //      Need to arbitrate between the flash cache and the CPU

        // The way this works, though, the CPU will stall once the flash 

        // cache gets access to the bus--the CPU will be stuck until the 

        // flash cache is finished with the bus.

        wire            ext_cyc, ext_stb, ext_we;

        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;

        wire    [31:0]   ext_addr, ext_odata;

        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,

                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,

                                        fc_ack, fc_stall,

                        cpu_addr, cpu_data, cpu_we,

                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),

                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,

                        ext_addr, ext_odata, ext_we, ext_stb,

                                ext_cyc, ext_ack, ext_stall);

`ifdef  DELAY_EXT_BUS

        busdelay #(32,32) extbus(i_clk,

                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,

                                ext_ack, ext_stall, ext_idata,

                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,

                                i_wb_ack, i_wb_stall, i_wb_data);

`else

        assign  o_wb_cyc   = ext_cyc;

        assign  o_wb_stb   = ext_stb;

        assign  o_wb_we    = ext_we;

        assign  o_wb_addr  = ext_addr;

        assign  o_wb_data  = ext_odata;

        assign  ext_ack    = i_wb_ack;

        assign  ext_stall  = i_wb_stall;

        assign  ext_idata  = i_wb_data;

`endif

        wire            tmr_ack;

        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);

        wire    [31:0]   tmr_data;

        assign  tmr_data = (tma_ack)?tma_data

                                :(tmb_ack ? tmb_data

                                :(tmc_ack ? tmc_data

                                :jif_data));

        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)

                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)

                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)

                        :(ext_idata)));

        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall

                                | wdt_stall | cache_stall

                                | cpu_ext_stall);

        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);

endmodule