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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [sim/] [verilator/] [README.md] - Blame information for rev 209
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dgisselq |
## The ZipCPU's Simulator
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This directory contains the basic ZipCPU simulator.
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Ok, even this isn't the *best* simulator of the ZipCPU. While this simulator
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*is* fully functional, it only simulates the
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[ZipCPU](../../rtl/core/zipcpu.v), encased in either the
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[ZipSystem](../../rtl/zipsystem.v)
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or the [ZipBones](../../rtl/zipbones.v),
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plus [memory](memsim.cpp). This simulator doesn't handle any interactions
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with the
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[flash](http://opencores.org/project,qspiflash), the
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[serial port](https://github.com/ZipCPU/wbuart32), the
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[SD-card](https://github.com/ZipCPU/sdspi), etc. All of these interactions
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(and more) are available from the
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[simulator](https://github.com/ZipCPU/zbasic/tree/master/sim/verilated)
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within the
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[ZBasic repository](https://github.com/ZipCPU/zbasic).
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However, this simulator *is* very basic to the CPU's functionality. If you
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just want to know if the CPU works by itself, if it can properly execute the
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instructions given to it--even to the point of testing
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interrupts etc, then this simulation will work. It's just not fully
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functional for testing all of the other peripheral components necessary
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to make a CPU useful.
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