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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: memsim.h
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU core
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//
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// Purpose: This creates a memory like device to act on a WISHBONE bus.
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// It doesn't exercise the bus thoroughly, but does give some
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// exercise to the bus to see whether or not the bus master
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// can control it.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory, run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#ifndef MEMSIM_H
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#define MEMSIM_H
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class MEMSIM {
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public:
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typedef unsigned int BUSW;
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typedef unsigned char uchar;
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BUSW *m_mem, m_len, m_mask;
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int m_nxt_ack;
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BUSW m_nxt_data;
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MEMSIM(const unsigned int nwords);
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~MEMSIM(void);
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void load(const char *fname);
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void load(const unsigned addr, const char *buf,const unsigned len);
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void apply(const uchar wb_cyc, const uchar wb_stb,
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const uchar wb_we,
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const BUSW wb_addr, const BUSW wb_data,
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const uchar wb_sel,
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uchar &o_ack, uchar &o_stall, BUSW &o_data);
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void operator()(const uchar wb_cyc, const uchar wb_stb,
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const uchar wb_we,
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const BUSW wb_addr, const BUSW wb_data,
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const uchar wb_sel,
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uchar &o_ack, uchar &o_stall, BUSW &o_data) {
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apply(wb_cyc, wb_stb, wb_we, wb_addr, wb_data, wb_sel, o_ack, o_stall, o_data);
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}
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BUSW &operator[](const BUSW addr) { return m_mem[addr&m_mask]; }
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};
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#endif
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