1 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/config.sub gcc-5.3.0-zip/config.sub
|
2 |
|
|
--- gcc-5.3.0-original/config.sub 2015-01-02 04:30:21.000000000 -0500
|
3 |
|
|
+++ gcc-5.3.0-zip/config.sub 2016-01-30 12:27:56.023073747 -0500
|
4 |
|
|
@@ -316,7 +316,7 @@
|
5 |
|
|
| visium \
|
6 |
|
|
| we32k \
|
7 |
|
|
| x86 | xc16x | xstormy16 | xtensa \
|
8 |
|
|
- | z8k | z80)
|
9 |
|
|
+ | z8k | z80 | zip)
|
10 |
|
|
basic_machine=$basic_machine-unknown
|
11 |
|
|
;;
|
12 |
|
|
c54x)
|
13 |
|
|
@@ -1547,6 +1547,9 @@
|
14 |
|
|
# system, and we'll never get to this point.
|
15 |
|
|
|
16 |
|
|
case $basic_machine in
|
17 |
|
|
+ zip-*)
|
18 |
|
|
+ os=-elf
|
19 |
|
|
+ ;;
|
20 |
|
|
score-*)
|
21 |
|
|
os=-elf
|
22 |
|
|
;;
|
23 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure gcc-5.3.0-zip/configure
|
24 |
|
|
--- gcc-5.3.0-original/configure 2015-05-03 13:29:57.000000000 -0400
|
25 |
|
|
+++ gcc-5.3.0-zip/configure 2016-01-30 16:19:48.264867231 -0500
|
26 |
|
|
@@ -3927,6 +3927,8 @@
|
27 |
|
|
vax-*-*)
|
28 |
|
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
29 |
|
|
;;
|
30 |
|
|
+ zip*)
|
31 |
|
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
|
32 |
|
|
esac
|
33 |
|
|
|
34 |
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
35 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure.ac gcc-5.3.0-zip/configure.ac
|
36 |
|
|
--- gcc-5.3.0-original/configure.ac 2015-05-03 13:29:57.000000000 -0400
|
37 |
|
|
+++ gcc-5.3.0-zip/configure.ac 2016-02-12 10:47:23.847194843 -0500
|
38 |
|
|
@@ -1274,6 +1274,10 @@
|
39 |
|
|
vax-*-*)
|
40 |
|
|
noconfigdirs="$noconfigdirs target-newlib target-libgloss"
|
41 |
|
|
;;
|
42 |
|
|
+ zip*)
|
43 |
|
|
+ noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
|
44 |
|
|
+ unsupported_languages="$unsupported_languages fortran java"
|
45 |
|
|
+ ;;
|
46 |
|
|
esac
|
47 |
|
|
|
48 |
|
|
# If we aren't building newlib, then don't build libgloss, since libgloss
|
49 |
117 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cfgexpand.c gcc-5.3.0-zip/gcc/cfgexpand.c
|
50 |
|
|
--- gcc-5.3.0-original/gcc/cfgexpand.c 2015-07-23 06:39:26.000000000 -0400
|
51 |
|
|
+++ gcc-5.3.0-zip/gcc/cfgexpand.c 2016-04-01 06:40:17.288326711 -0400
|
52 |
|
|
@@ -108,6 +108,14 @@
|
53 |
|
|
#include "tree-chkp.h"
|
54 |
|
|
#include "rtl-chkp.h"
|
55 |
|
|
|
56 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
57 |
|
|
+#include <stdio.h>
|
58 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
|
59 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
60 |
|
|
+#else
|
61 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
62 |
|
|
+#endif
|
63 |
|
|
+
|
64 |
|
|
/* Some systems use __main in a way incompatible with its use in gcc, in these
|
65 |
|
|
cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
|
66 |
|
|
give the same symbol without quotes for an alternative entry point. You
|
67 |
111 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
|
68 |
|
|
--- gcc-5.3.0-original/gcc/cgraphbuild.c 2015-01-09 15:18:42.000000000 -0500
|
69 |
|
|
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c 2016-03-24 22:13:24.815287808 -0400
|
70 |
|
|
@@ -62,6 +62,13 @@
|
71 |
|
|
#include "ipa-prop.h"
|
72 |
|
|
#include "ipa-inline.h"
|
73 |
|
|
|
74 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
75 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
76 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
77 |
|
|
+#else
|
78 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
79 |
|
|
+#endif
|
80 |
|
|
+
|
81 |
|
|
/* Context of record_reference. */
|
82 |
|
|
struct record_reference_ctx
|
83 |
|
|
{
|
84 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
|
85 |
|
|
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c 1969-12-31 19:00:00.000000000 -0500
|
86 |
|
|
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c 2016-02-14 00:54:31.821055716 -0500
|
87 |
|
|
@@ -0,0 +1,52 @@
|
88 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
89 |
|
|
+//
|
90 |
|
|
+// Filename: common/config/zip/zip-common.c
|
91 |
|
|
+//
|
92 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
93 |
|
|
+//
|
94 |
|
|
+// Purpose: To eliminate the frame register automatically.
|
95 |
|
|
+//
|
96 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
97 |
|
|
+// Gisselquist Technology, LLC
|
98 |
|
|
+//
|
99 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
100 |
|
|
+//
|
101 |
|
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
102 |
|
|
+//
|
103 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
104 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
105 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
106 |
|
|
+// your option) any later version.
|
107 |
|
|
+//
|
108 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
109 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
110 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
111 |
|
|
+// for more details.
|
112 |
|
|
+//
|
113 |
|
|
+// You should have received a copy of the GNU General Public License along
|
114 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
115 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
116 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
117 |
|
|
+//
|
118 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
119 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
120 |
|
|
+//
|
121 |
|
|
+//
|
122 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
123 |
|
|
+#include "config.h"
|
124 |
|
|
+#include "system.h"
|
125 |
|
|
+#include "coretypes.h"
|
126 |
|
|
+#include "tm.h"
|
127 |
|
|
+#include "common/common-target.h"
|
128 |
|
|
+#include "common/common-target-def.h"
|
129 |
|
|
+
|
130 |
|
|
+static const struct default_options zip_option_optimization_table[] =
|
131 |
|
|
+ {
|
132 |
|
|
+ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
|
133 |
|
|
+ { OPT_LEVELS_NONE, 0, NULL, 0 }
|
134 |
|
|
+ };
|
135 |
|
|
+
|
136 |
|
|
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
|
137 |
|
|
+#define TARGET_OPTION_OPTIMIZATION_TABLE zip_option_optimization_table
|
138 |
|
|
+
|
139 |
|
|
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
|
140 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
|
141 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h 2016-09-13 10:23:45.886099269 -0400
|
142 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h 2015-07-24 12:00:26.000000000 -0400
|
143 |
|
|
@@ -21,7 +21,7 @@
|
144 |
|
|
#ifndef GCC_AARCH64_LINUX_H
|
145 |
|
|
#define GCC_AARCH64_LINUX_H
|
146 |
|
|
|
147 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
|
148 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
|
149 |
|
|
|
150 |
|
|
#undef ASAN_CC1_SPEC
|
151 |
|
|
#define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
|
152 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
|
153 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h 2016-09-13 10:23:45.886099269 -0400
|
154 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
155 |
|
|
@@ -23,8 +23,8 @@
|
156 |
|
|
#define EXTRA_SPECS \
|
157 |
|
|
{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
|
158 |
|
|
|
159 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
160 |
|
|
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
|
161 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
162 |
|
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
163 |
|
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
164 |
|
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
165 |
|
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
166 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
|
167 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h 2016-09-13 10:23:45.886099269 -0400
|
168 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h 2015-01-05 07:33:28.000000000 -0500
|
169 |
|
|
@@ -68,8 +68,8 @@
|
170 |
|
|
GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI. */
|
171 |
|
|
|
172 |
|
|
#undef GLIBC_DYNAMIC_LINKER
|
173 |
|
|
-#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/tools/lib/ld-linux.so.3"
|
174 |
|
|
-#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/tools/lib/ld-linux-armhf.so.3"
|
175 |
|
|
+#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/lib/ld-linux.so.3"
|
176 |
|
|
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
|
177 |
|
|
#define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
|
178 |
|
|
|
179 |
|
|
#define GLIBC_DYNAMIC_LINKER \
|
180 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
|
181 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h 2016-09-13 10:23:45.886099269 -0400
|
182 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h 2015-06-23 05:26:54.000000000 -0400
|
183 |
|
|
@@ -62,7 +62,7 @@
|
184 |
|
|
|
185 |
|
|
#define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
|
186 |
|
|
|
187 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
188 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
189 |
|
|
|
190 |
|
|
#define LINUX_TARGET_LINK_SPEC "%{h*} \
|
191 |
|
|
%{static:-Bstatic} \
|
192 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
|
193 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/bfin/linux.h 2016-09-13 10:23:45.886099269 -0400
|
194 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h 2015-01-05 07:33:28.000000000 -0500
|
195 |
|
|
@@ -45,7 +45,7 @@
|
196 |
|
|
%{shared:-G -Bdynamic} \
|
197 |
|
|
%{!shared: %{!static: \
|
198 |
|
|
%{rdynamic:-export-dynamic} \
|
199 |
|
|
- -dynamic-linker /tools/lib/ld-uClibc.so.0} \
|
200 |
|
|
+ -dynamic-linker /lib/ld-uClibc.so.0} \
|
201 |
|
|
%{static}} -init __init -fini __fini"
|
202 |
|
|
|
203 |
|
|
#undef TARGET_SUPPORTS_SYNC_CALLS
|
204 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
|
205 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/cris/linux.h 2016-09-13 10:23:45.886099269 -0400
|
206 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h 2015-01-05 07:33:28.000000000 -0500
|
207 |
|
|
@@ -102,7 +102,7 @@
|
208 |
|
|
#undef CRIS_DEFAULT_CPU_VERSION
|
209 |
|
|
#define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
|
210 |
|
|
|
211 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
212 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
213 |
|
|
|
214 |
|
|
#undef CRIS_LINK_SUBTARGET_SPEC
|
215 |
|
|
#define CRIS_LINK_SUBTARGET_SPEC \
|
216 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
|
217 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h 2016-09-13 10:23:45.886099269 -0400
|
218 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h 2015-06-25 13:53:14.000000000 -0400
|
219 |
|
|
@@ -129,9 +129,9 @@
|
220 |
|
|
#endif
|
221 |
|
|
|
222 |
|
|
#if FBSD_MAJOR < 6
|
223 |
|
|
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
|
224 |
|
|
+#define FBSD_DYNAMIC_LINKER "/usr/libexec/ld-elf.so.1"
|
225 |
|
|
#else
|
226 |
|
|
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
|
227 |
|
|
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
|
228 |
|
|
#endif
|
229 |
|
|
|
230 |
|
|
/* NOTE: The freebsd-spec.h header is included also for various
|
231 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
|
232 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/frv/linux.h 2016-09-13 10:23:45.886099269 -0400
|
233 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h 2015-01-05 07:33:28.000000000 -0500
|
234 |
|
|
@@ -34,7 +34,7 @@
|
235 |
|
|
#define ENDFILE_SPEC \
|
236 |
|
|
"%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
|
237 |
|
|
|
238 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
239 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
240 |
|
|
|
241 |
|
|
#undef LINK_SPEC
|
242 |
|
|
#define LINK_SPEC "\
|
243 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
|
244 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/i386/gnu.h 2016-09-13 10:23:45.886099269 -0400
|
245 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
|
246 |
|
|
@@ -22,7 +22,7 @@
|
247 |
|
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
248 |
|
|
|
249 |
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
250 |
|
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so"
|
251 |
|
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
|
252 |
|
|
|
253 |
|
|
#undef STARTFILE_SPEC
|
254 |
|
|
#if defined HAVE_LD_PIE
|
255 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
|
256 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-09-13 10:23:45.890099248 -0400
|
257 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h 2015-01-05 07:33:28.000000000 -0500
|
258 |
|
|
@@ -22,6 +22,6 @@
|
259 |
|
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
|
260 |
|
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
|
261 |
|
|
|
262 |
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
|
263 |
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld-kfreebsd-x86-64.so.1"
|
264 |
|
|
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
|
265 |
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
266 |
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
|
267 |
|
|
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
|
268 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
|
269 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h 2016-09-13 10:23:45.886099269 -0400
|
270 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
271 |
|
|
@@ -19,4 +19,4 @@
|
272 |
|
|
<http://www.gnu.org/licenses/>. */
|
273 |
|
|
|
274 |
|
|
#define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
|
275 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
276 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
277 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
|
278 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/i386/linux64.h 2016-09-13 10:23:45.890099248 -0400
|
279 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
280 |
|
|
@@ -27,6 +27,6 @@
|
281 |
|
|
#define GNU_USER_LINK_EMULATION64 "elf_x86_64"
|
282 |
|
|
#define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
|
283 |
|
|
|
284 |
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
|
285 |
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux-x86-64.so.2"
|
286 |
|
|
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
|
287 |
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
|
288 |
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
|
289 |
|
|
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
|
290 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
|
291 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/i386/linux.h 2016-09-13 10:23:45.890099248 -0400
|
292 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h 2015-01-05 07:33:28.000000000 -0500
|
293 |
|
|
@@ -20,4 +20,4 @@
|
294 |
|
|
<http://www.gnu.org/licenses/>. */
|
295 |
|
|
|
296 |
|
|
#define GNU_USER_LINK_EMULATION "elf_i386"
|
297 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
298 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
299 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
|
300 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/ia64/linux.h 2016-09-13 10:23:45.890099248 -0400
|
301 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h 2015-01-05 07:33:28.000000000 -0500
|
302 |
|
|
@@ -55,7 +55,7 @@
|
303 |
|
|
/* Define this for shared library support because it isn't in the main
|
304 |
|
|
linux.h file. */
|
305 |
|
|
|
306 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-ia64.so.2"
|
307 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
|
308 |
|
|
|
309 |
|
|
#undef LINK_SPEC
|
310 |
|
|
#define LINK_SPEC "\
|
311 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
|
312 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-09-13 10:23:45.890099248 -0400
|
313 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
314 |
|
|
@@ -32,4 +32,4 @@
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
318 |
|
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
319 |
|
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
320 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
|
321 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h 2016-09-13 10:23:45.890099248 -0400
|
322 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
|
323 |
|
|
@@ -31,5 +31,4 @@
|
324 |
|
|
while (0)
|
325 |
|
|
|
326 |
|
|
#undef GNU_USER_DYNAMIC_LINKER
|
327 |
|
|
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
328 |
|
|
-
|
329 |
|
|
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
|
330 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
|
331 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/linux.h 2016-09-13 10:23:45.890099248 -0400
|
332 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/linux.h 2015-01-05 07:33:28.000000000 -0500
|
333 |
|
|
@@ -73,10 +73,10 @@
|
334 |
|
|
GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
|
335 |
|
|
GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
|
336 |
|
|
supporting both 32-bit and 64-bit compilation. */
|
337 |
|
|
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
|
338 |
|
|
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
|
339 |
|
|
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
|
340 |
|
|
-#define UCLIBC_DYNAMIC_LINKERX32 "/tools/lib/ldx32-uClibc.so.0"
|
341 |
|
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
342 |
|
|
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
|
343 |
|
|
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
|
344 |
|
|
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
|
345 |
|
|
#define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
|
346 |
|
|
#define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
|
347 |
|
|
#define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
|
348 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
|
349 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h 2016-09-13 10:23:45.890099248 -0400
|
350 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
|
351 |
|
|
@@ -67,7 +67,7 @@
|
352 |
|
|
%{shared:-shared} \
|
353 |
|
|
%{symbolic:-Bsymbolic} \
|
354 |
|
|
%{rdynamic:-export-dynamic} \
|
355 |
|
|
- -dynamic-linker /tools/lib/ld-linux.so.2"
|
356 |
|
|
+ -dynamic-linker /lib/ld-linux.so.2"
|
357 |
|
|
|
358 |
|
|
#define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
|
359 |
|
|
|
360 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
|
361 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/m68k/linux.h 2016-09-13 10:23:45.890099248 -0400
|
362 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h 2015-01-05 07:33:28.000000000 -0500
|
363 |
|
|
@@ -71,7 +71,7 @@
|
364 |
|
|
When the -shared link option is used a final link is not being
|
365 |
|
|
done. */
|
366 |
|
|
|
367 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
368 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
369 |
|
|
|
370 |
|
|
#undef LINK_SPEC
|
371 |
|
|
#define LINK_SPEC "-m m68kelf %{shared} \
|
372 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
|
373 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h 2016-09-13 10:23:45.890099248 -0400
|
374 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
|
375 |
|
|
@@ -28,7 +28,7 @@
|
376 |
|
|
#undef TLS_NEEDS_GOT
|
377 |
|
|
#define TLS_NEEDS_GOT 1
|
378 |
|
|
|
379 |
|
|
-#define DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
380 |
|
|
+#define DYNAMIC_LINKER "/lib/ld.so.1"
|
381 |
|
|
#undef SUBTARGET_EXTRA_SPECS
|
382 |
|
|
#define SUBTARGET_EXTRA_SPECS \
|
383 |
|
|
{ "dynamic_linker", DYNAMIC_LINKER }
|
384 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
|
385 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/mips/linux.h 2016-09-13 10:23:45.890099248 -0400
|
386 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h 2015-01-05 07:33:28.000000000 -0500
|
387 |
|
|
@@ -22,20 +22,20 @@
|
388 |
|
|
#define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
|
389 |
|
|
|
390 |
|
|
#define GLIBC_DYNAMIC_LINKER32 \
|
391 |
|
|
- "%{mnan=2008:/tools/lib/ld-linux-mipsn8.so.1;:/tools/lib/ld.so.1}"
|
392 |
|
|
+ "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}"
|
393 |
|
|
#define GLIBC_DYNAMIC_LINKER64 \
|
394 |
|
|
- "%{mnan=2008:/tools/lib64/ld-linux-mipsn8.so.1;:/tools/lib64/ld.so.1}"
|
395 |
|
|
+ "%{mnan=2008:/lib64/ld-linux-mipsn8.so.1;:/lib64/ld.so.1}"
|
396 |
|
|
#define GLIBC_DYNAMIC_LINKERN32 \
|
397 |
|
|
- "%{mnan=2008:/tools/lib32/ld-linux-mipsn8.so.1;:/tools/lib32/ld.so.1}"
|
398 |
|
|
+ "%{mnan=2008:/lib32/ld-linux-mipsn8.so.1;:/lib32/ld.so.1}"
|
399 |
|
|
|
400 |
|
|
#undef UCLIBC_DYNAMIC_LINKER32
|
401 |
|
|
#define UCLIBC_DYNAMIC_LINKER32 \
|
402 |
|
|
- "%{mnan=2008:/tools/lib/ld-uClibc-mipsn8.so.0;:/tools/lib/ld-uClibc.so.0}"
|
403 |
|
|
+ "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}"
|
404 |
|
|
#undef UCLIBC_DYNAMIC_LINKER64
|
405 |
|
|
#define UCLIBC_DYNAMIC_LINKER64 \
|
406 |
|
|
- "%{mnan=2008:/tools/lib/ld64-uClibc-mipsn8.so.0;:/tools/lib/ld64-uClibc.so.0}"
|
407 |
|
|
+ "%{mnan=2008:/lib/ld64-uClibc-mipsn8.so.0;:/lib/ld64-uClibc.so.0}"
|
408 |
|
|
#define UCLIBC_DYNAMIC_LINKERN32 \
|
409 |
|
|
- "%{mnan=2008:/tools/lib32/ld-uClibc-mipsn8.so.0;:/tools/lib32/ld-uClibc.so.0}"
|
410 |
|
|
+ "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
|
411 |
|
|
|
412 |
|
|
#define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
|
413 |
|
|
#define GNU_USER_DYNAMIC_LINKERN32 \
|
414 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
|
415 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h 2016-09-13 10:23:45.890099248 -0400
|
416 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h 2015-01-05 07:33:28.000000000 -0500
|
417 |
|
|
@@ -32,7 +32,7 @@
|
418 |
|
|
#undef ASM_SPEC
|
419 |
|
|
#define ASM_SPEC ""
|
420 |
|
|
|
421 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
422 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
423 |
|
|
|
424 |
|
|
#undef LINK_SPEC
|
425 |
|
|
#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
|
426 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
|
427 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-09-13 10:23:45.890099248 -0400
|
428 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h 2015-09-24 20:04:26.000000000 -0400
|
429 |
|
|
@@ -37,7 +37,7 @@
|
430 |
|
|
/* Define this for shared library support because it isn't in the main
|
431 |
|
|
linux.h file. */
|
432 |
|
|
|
433 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
434 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
435 |
|
|
|
436 |
|
|
#undef LINK_SPEC
|
437 |
|
|
#define LINK_SPEC "\
|
438 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
|
439 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h 2016-09-13 10:23:45.890099248 -0400
|
440 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h 2015-03-09 19:18:57.000000000 -0400
|
441 |
|
|
@@ -357,14 +357,14 @@
|
442 |
|
|
#undef LINK_OS_DEFAULT_SPEC
|
443 |
|
|
#define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
|
444 |
|
|
|
445 |
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
|
446 |
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
447 |
|
|
#ifdef LINUX64_DEFAULT_ABI_ELFv2
|
448 |
|
|
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/tools/lib64/ld64.so.1;:/tools/lib64/ld64.so.2}"
|
449 |
|
|
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"
|
450 |
|
|
#else
|
451 |
|
|
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/tools/lib64/ld64.so.2;:/tools/lib64/ld64.so.1}"
|
452 |
|
|
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"
|
453 |
|
|
#endif
|
454 |
|
|
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
|
455 |
|
|
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
|
456 |
|
|
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
|
457 |
|
|
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
|
458 |
|
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
459 |
|
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
460 |
|
|
#elif DEFAULT_LIBC == LIBC_GLIBC
|
461 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
|
462 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h 2016-09-13 10:23:45.890099248 -0400
|
463 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h 2015-09-24 09:46:45.000000000 -0400
|
464 |
|
|
@@ -757,8 +757,8 @@
|
465 |
|
|
|
466 |
|
|
#define LINK_START_LINUX_SPEC ""
|
467 |
|
|
|
468 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
469 |
|
|
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
|
470 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
471 |
|
|
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
472 |
|
|
#if DEFAULT_LIBC == LIBC_UCLIBC
|
473 |
|
|
#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
|
474 |
|
|
#elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
|
475 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
|
476 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/s390/linux.h 2016-09-13 10:23:45.890099248 -0400
|
477 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h 2015-05-11 03:14:10.000000000 -0400
|
478 |
|
|
@@ -60,8 +60,8 @@
|
479 |
|
|
#define MULTILIB_DEFAULTS { "m31" }
|
480 |
|
|
#endif
|
481 |
|
|
|
482 |
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
|
483 |
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64.so.1"
|
484 |
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
|
485 |
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
|
486 |
|
|
|
487 |
|
|
#undef LINK_SPEC
|
488 |
|
|
#define LINK_SPEC \
|
489 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
|
490 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/sh/linux.h 2016-09-13 10:23:45.890099248 -0400
|
491 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
|
492 |
|
|
@@ -43,7 +43,7 @@
|
493 |
|
|
|
494 |
|
|
#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
|
495 |
|
|
|
496 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
497 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
498 |
|
|
|
499 |
|
|
#undef SUBTARGET_LINK_EMUL_SUFFIX
|
500 |
|
|
#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
|
501 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
|
502 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h 2016-09-13 10:23:45.890099248 -0400
|
503 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h 2015-01-05 07:33:28.000000000 -0500
|
504 |
|
|
@@ -84,8 +84,8 @@
|
505 |
|
|
When the -shared link option is used a final link is not being
|
506 |
|
|
done. */
|
507 |
|
|
|
508 |
|
|
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
|
509 |
|
|
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux.so.2"
|
510 |
|
|
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
|
511 |
|
|
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
|
512 |
|
|
|
513 |
|
|
#ifdef SPARC_BI_ARCH
|
514 |
|
|
|
515 |
|
|
@@ -193,7 +193,7 @@
|
516 |
|
|
#else /* !SPARC_BI_ARCH */
|
517 |
|
|
|
518 |
|
|
#undef LINK_SPEC
|
519 |
|
|
-#define LINK_SPEC "-m elf64_sparc -Y P,%R/tools/lib64 %{shared:-shared} \
|
520 |
|
|
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
|
521 |
|
|
%{!shared: \
|
522 |
|
|
%{!static: \
|
523 |
|
|
%{rdynamic:-export-dynamic} \
|
524 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
|
525 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-09-13 10:23:45.890099248 -0400
|
526 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h 2015-01-05 07:33:28.000000000 -0500
|
527 |
|
|
@@ -83,7 +83,7 @@
|
528 |
|
|
When the -shared link option is used a final link is not being
|
529 |
|
|
done. */
|
530 |
|
|
|
531 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
|
532 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
|
533 |
|
|
|
534 |
|
|
#undef LINK_SPEC
|
535 |
|
|
#define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
|
536 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
|
537 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/vax/linux.h 2016-09-13 10:23:45.890099248 -0400
|
538 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h 2015-01-05 07:33:28.000000000 -0500
|
539 |
|
|
@@ -41,7 +41,7 @@
|
540 |
|
|
%{!shared: \
|
541 |
|
|
%{!static: \
|
542 |
|
|
%{rdynamic:-export-dynamic} \
|
543 |
|
|
- -dynamic-linker /tools/lib/ld.so.1} \
|
544 |
|
|
+ -dynamic-linker /lib/ld.so.1} \
|
545 |
|
|
%{static:-static}}"
|
546 |
|
|
|
547 |
|
|
#undef WCHAR_TYPE
|
548 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
|
549 |
171 |
dgisselq |
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h 2016-09-13 10:23:45.890099248 -0400
|
550 |
102 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h 2015-01-05 07:33:28.000000000 -0500
|
551 |
|
|
@@ -44,7 +44,7 @@
|
552 |
|
|
%{mlongcalls:--longcalls} \
|
553 |
|
|
%{mno-longcalls:--no-longcalls}"
|
554 |
|
|
|
555 |
|
|
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
|
556 |
|
|
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
|
557 |
|
|
|
558 |
|
|
#undef LINK_SPEC
|
559 |
|
|
#define LINK_SPEC \
|
560 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/netbsd.h gcc-5.3.0-zip/gcc/config/zip/netbsd.h
|
561 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/netbsd.h 1969-12-31 19:00:00.000000000 -0500
|
562 |
|
|
+++ gcc-5.3.0-zip/gcc/config/zip/netbsd.h 2016-01-30 15:04:14.796899050 -0500
|
563 |
|
|
@@ -0,0 +1,82 @@
|
564 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
565 |
|
|
+//
|
566 |
|
|
+// Filename: netbsd.h
|
567 |
|
|
+//
|
568 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
569 |
|
|
+//
|
570 |
|
|
+// Purpose:
|
571 |
|
|
+//
|
572 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
573 |
|
|
+// Gisselquist Technology, LLC
|
574 |
|
|
+//
|
575 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
576 |
|
|
+//
|
577 |
|
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
578 |
|
|
+//
|
579 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
580 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
581 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
582 |
|
|
+// your option) any later version.
|
583 |
|
|
+//
|
584 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
585 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
586 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
587 |
|
|
+// for more details.
|
588 |
|
|
+//
|
589 |
|
|
+// You should have received a copy of the GNU General Public License along
|
590 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
591 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
592 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
593 |
|
|
+//
|
594 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
595 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
596 |
|
|
+//
|
597 |
|
|
+//
|
598 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
599 |
|
|
+#ifndef ZIP_NETBSD_H
|
600 |
|
|
+#define ZIP_NETBSD_H
|
601 |
|
|
+
|
602 |
|
|
+/* Define default target values. */
|
603 |
|
|
+
|
604 |
|
|
+#undef MACHINE_TYPE
|
605 |
|
|
+#define MACHINE_TYPE "NetBSD/Zip ELF"
|
606 |
|
|
+
|
607 |
|
|
+#undef TARGET_OS_CPP_BUILTINS
|
608 |
|
|
+#define TARGET_OS_CPP_BUILTINS() \
|
609 |
|
|
+ do { NETBSD_OS_CPP_BUILTINS_ELF(); \
|
610 |
|
|
+ builtin_define("__ZIPCPU__"); \
|
611 |
|
|
+ builtin_assert("cpu=zip"); \
|
612 |
|
|
+ builtin_assert("machine=zip"); \
|
613 |
|
|
+ } while(0);
|
614 |
|
|
+
|
615 |
|
|
+#undef CPP_SPEC
|
616 |
|
|
+#define CPP_SPEC NETBSD_CPP_SPEC
|
617 |
|
|
+
|
618 |
|
|
+#undef STARTFILE_SPEC
|
619 |
|
|
+#define STARTFILE_SPEC NETBSD_STARTFILE_SPEC
|
620 |
|
|
+
|
621 |
|
|
+#undef ENDFILE_SPEC
|
622 |
|
|
+#define ENDFILE_SPEC NETBSD_ENDFILE_SPEC
|
623 |
|
|
+
|
624 |
|
|
+#undef LIB_SPEC
|
625 |
|
|
+#define LIB_SPEC NETBSD_LIB_SPEC
|
626 |
|
|
+
|
627 |
|
|
+#undef TARGET_VERSION
|
628 |
|
|
+#define TARGET_VERSION fprintf(stderr, " (%s)", MACHINE_TYPE);
|
629 |
|
|
+
|
630 |
|
|
+/* Make gcc agree with <machine/ansi.h> */
|
631 |
|
|
+
|
632 |
|
|
+#undef WCHAR_TYPE
|
633 |
|
|
+#define WCHAR_TYPE "int"
|
634 |
|
|
+
|
635 |
|
|
+#undef WCHAR_TYPE_SIZE
|
636 |
|
|
+#define WCHAR_TYPE_SIZE 32
|
637 |
|
|
+
|
638 |
|
|
+#undef WINT_TYPE
|
639 |
|
|
+#define WINT_TYPE "int"
|
640 |
|
|
+
|
641 |
|
|
+/* Clean up after the generic Zip/ELF configuration. */
|
642 |
|
|
+#undef MD_EXEC_PREFIX
|
643 |
|
|
+#undef MD_STARTFILE_PREFIX
|
644 |
|
|
+
|
645 |
|
|
+#endif /* ZIP_NETBSD_H */
|
646 |
171 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/notes.txt gcc-5.3.0-zip/gcc/config/zip/notes.txt
|
647 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/notes.txt 1969-12-31 19:00:00.000000000 -0500
|
648 |
|
|
+++ gcc-5.3.0-zip/gcc/config/zip/notes.txt 2016-08-17 23:00:25.714139174 -0400
|
649 |
|
|
@@ -0,0 +1,6 @@
|
650 |
|
|
+signum:
|
651 |
|
|
+ CMP 0,%1
|
652 |
|
|
+ LDILO.GT 1,%1
|
653 |
|
|
+ LDILO.LT -1,%1
|
654 |
|
|
+
|
655 |
|
|
+
|
656 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/t-zip gcc-5.3.0-zip/gcc/config/zip/t-zip
|
657 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/t-zip 1969-12-31 19:00:00.000000000 -0500
|
658 |
|
|
+++ gcc-5.3.0-zip/gcc/config/zip/t-zip 2016-02-04 19:00:59.939652587 -0500
|
659 |
|
|
@@ -0,0 +1,47 @@
|
660 |
|
|
+################################################################################
|
661 |
|
|
+##
|
662 |
|
|
+## Filename: t-zip
|
663 |
|
|
+##
|
664 |
|
|
+## Project: Zip CPU backend for the GNU Compiler Collection
|
665 |
|
|
+##
|
666 |
|
|
+## Purpose:
|
667 |
|
|
+##
|
668 |
|
|
+## Creator: Dan Gisselquist, Ph.D.
|
669 |
|
|
+## Gisselquist Technology, LLC
|
670 |
|
|
+##
|
671 |
|
|
+################################################################################
|
672 |
|
|
+##
|
673 |
|
|
+## Copyright (C) 2016, Gisselquist Technology, LLC
|
674 |
|
|
+##
|
675 |
|
|
+## This program is free software (firmware): you can redistribute it and/or
|
676 |
|
|
+## modify it under the terms of the GNU General Public License as published
|
677 |
|
|
+## by the Free Software Foundation, either version 3 of the License, or (at
|
678 |
|
|
+## your option) any later version.
|
679 |
|
|
+##
|
680 |
|
|
+## This program is distributed in the hope that it will be useful, but WITHOUT
|
681 |
|
|
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
682 |
|
|
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
683 |
|
|
+## for more details.
|
684 |
|
|
+##
|
685 |
|
|
+## You should have received a copy of the GNU General Public License along
|
686 |
|
|
+## with this program. (It's in the $(ROOT)/doc directory, run make with no
|
687 |
|
|
+## target there if the PDF file isn't present.) If not, see
|
688 |
|
|
+## <http://www.gnu.org/licenses/> for a copy.
|
689 |
|
|
+##
|
690 |
|
|
+## License: GPL, v3, as defined and found on www.gnu.org,
|
691 |
|
|
+## http://www.gnu.org/licenses/gpl.html
|
692 |
|
|
+##
|
693 |
|
|
+##
|
694 |
|
|
+################################################################################
|
695 |
|
|
+
|
696 |
|
|
+FPBIT = fp-bit.c
|
697 |
|
|
+DPBIT = dp-bit.c
|
698 |
|
|
+
|
699 |
|
|
+# dp-bit.c: $(srcdir)/config/fp-bit.c
|
700 |
|
|
+ # cat $(srcdir)/config/fp-bit.c > dp-bit.c
|
701 |
|
|
+#
|
702 |
|
|
+# fp-bit.c: $(srcdir)/config/fp-bit.c
|
703 |
|
|
+ # echo '#define FLOAT" > fp-bit.c
|
704 |
|
|
+ # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
705 |
|
|
+
|
706 |
|
|
+
|
707 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
|
708 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip.c 1969-12-31 19:00:00.000000000 -0500
|
709 |
171 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c 2016-09-13 10:06:40.979536485 -0400
|
710 |
|
|
@@ -0,0 +1,2151 @@
|
711 |
102 |
dgisselq |
+////////////////////////////////////////////////////////////////////////////////
|
712 |
|
|
+//
|
713 |
|
|
+// Filename: zip.c
|
714 |
|
|
+//
|
715 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
716 |
|
|
+//
|
717 |
|
|
+// Purpose:
|
718 |
|
|
+//
|
719 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
720 |
|
|
+// Gisselquist Technology, LLC
|
721 |
|
|
+//
|
722 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
723 |
|
|
+//
|
724 |
|
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
725 |
|
|
+//
|
726 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
727 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
728 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
729 |
|
|
+// your option) any later version.
|
730 |
|
|
+//
|
731 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
732 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
733 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
734 |
|
|
+// for more details.
|
735 |
|
|
+//
|
736 |
|
|
+// You should have received a copy of the GNU General Public License along
|
737 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
738 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
739 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
740 |
|
|
+//
|
741 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
742 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
743 |
|
|
+//
|
744 |
|
|
+//
|
745 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
746 |
|
|
+#include "config.h"
|
747 |
|
|
+#include "system.h"
|
748 |
|
|
+#include "coretypes.h"
|
749 |
|
|
+#include "tm.h"
|
750 |
|
|
+#include "rtl.h"
|
751 |
|
|
+#include "dominance.h"
|
752 |
|
|
+#include "cfg.h"
|
753 |
|
|
+#include "cfgrtl.h"
|
754 |
|
|
+#include "cfganal.h"
|
755 |
|
|
+#include "lcm.h"
|
756 |
|
|
+#include "cfgbuild.h"
|
757 |
|
|
+#include "cfgcleanup.h"
|
758 |
|
|
+#include "predict.h"
|
759 |
|
|
+#include "basic-block.h"
|
760 |
|
|
+#include "df.h"
|
761 |
|
|
+#include "hashtab.h"
|
762 |
|
|
+#include "hash-set.h"
|
763 |
|
|
+#include "machmode.h"
|
764 |
|
|
+#include "symtab.h"
|
765 |
|
|
+#include "rtlhash.h"
|
766 |
|
|
+#include "tree.h"
|
767 |
|
|
+#include "regs.h"
|
768 |
|
|
+#include "hard-reg-set.h"
|
769 |
|
|
+#include "real.h"
|
770 |
|
|
+#include "insn-config.h"
|
771 |
|
|
+#include "conditions.h"
|
772 |
|
|
+#include "output.h"
|
773 |
|
|
+#include "insn-attr.h"
|
774 |
|
|
+#include "flags.h"
|
775 |
|
|
+#include "expr.h"
|
776 |
|
|
+#include "function.h"
|
777 |
|
|
+#include "recog.h"
|
778 |
|
|
+#include "toplev.h"
|
779 |
|
|
+#include "ggc.h"
|
780 |
|
|
+#include "builtins.h"
|
781 |
|
|
+#include "calls.h"
|
782 |
|
|
+#include "langhooks.h"
|
783 |
|
|
+#include "optabs.h"
|
784 |
|
|
+#include "explow.h"
|
785 |
|
|
+#include "emit-rtl.h"
|
786 |
122 |
dgisselq |
+#include "ifcvt.h"
|
787 |
102 |
dgisselq |
+
|
788 |
|
|
+// #include "tmp_p.h"
|
789 |
|
|
+#include "target.h"
|
790 |
|
|
+#include "target-def.h"
|
791 |
|
|
+// #include "tm-constrs.h"
|
792 |
122 |
dgisselq |
+#include "tm-preds.h"
|
793 |
102 |
dgisselq |
+
|
794 |
|
|
+#include "diagnostic.h"
|
795 |
|
|
+// #include "integrate.h"
|
796 |
|
|
+
|
797 |
|
|
+// static int zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
|
798 |
|
|
+// static bool zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
|
799 |
|
|
+static bool zip_return_in_memory(const_tree, const_tree);
|
800 |
|
|
+static bool zip_frame_pointer_required(void);
|
801 |
|
|
+
|
802 |
|
|
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
|
803 |
|
|
+ const_tree type, bool named);
|
804 |
|
|
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
|
805 |
|
|
+
|
806 |
|
|
+static void zip_asm_trampoline_template(FILE *);
|
807 |
|
|
+static void zip_trampoline_init(rtx, tree, rtx);
|
808 |
|
|
+static void zip_init_builtins(void);
|
809 |
|
|
+static tree zip_builtin_decl(unsigned, bool);
|
810 |
|
|
+// static void zip_asm_output_anchor(rtx x);
|
811 |
|
|
+ void zip_asm_output_def(FILE *s, const char *n, const char *v);
|
812 |
|
|
+static rtx zip_expand_builtin(tree exp, rtx target, rtx subtarget,
|
813 |
|
|
+ enum machine_mode tmode, int ignore);
|
814 |
|
|
+static bool zip_scalar_mode_supported_p(enum machine_mode mode);
|
815 |
|
|
+static bool zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
|
816 |
|
|
+static int zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
|
817 |
|
|
+static bool zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
|
818 |
|
|
+static unsigned HOST_WIDE_INT zip_const_anchor = 0x20000;
|
819 |
122 |
dgisselq |
+static HOST_WIDE_INT zip_min_opb_imm = -0x20000;
|
820 |
|
|
+static HOST_WIDE_INT zip_max_opb_imm = 0x1ffff;
|
821 |
142 |
dgisselq |
+static HOST_WIDE_INT zip_min_anchor_offset = -0x2000;
|
822 |
|
|
+static HOST_WIDE_INT zip_max_anchor_offset = 0x1fff;
|
823 |
102 |
dgisselq |
+static HOST_WIDE_INT zip_min_mov_offset = -0x1000;
|
824 |
|
|
+static HOST_WIDE_INT zip_max_mov_offset = 0x0fff;
|
825 |
|
|
+static int zip_sched_issue_rate(void) { return 1; }
|
826 |
|
|
+static bool zip_legitimate_address_p(machine_mode, rtx, bool);
|
827 |
|
|
+static bool zip_legitimate_move_operand_p(machine_mode, rtx, bool);
|
828 |
|
|
+ void zip_debug_rtx_pfx(const char *, const_rtx x);
|
829 |
|
|
+ void zip_debug_rtx(const_rtx x);
|
830 |
|
|
+static void zip_override_options(void);
|
831 |
|
|
+static bool zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
|
832 |
|
|
+static int zip_memory_move_cost(machine_mode, reg_class_t, bool);
|
833 |
111 |
dgisselq |
+static rtx zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
|
834 |
117 |
dgisselq |
+static bool zip_cannot_modify_jumps_p(void);
|
835 |
122 |
dgisselq |
+#ifdef HAVE_cc0
|
836 |
|
|
+ void zip_update_cc_notice(rtx exp, rtx_insn *insn);
|
837 |
|
|
+#error "We're not supposed to have CC0 anymore"
|
838 |
|
|
+#else
|
839 |
|
|
+static bool zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
|
840 |
|
|
+#endif
|
841 |
102 |
dgisselq |
+
|
842 |
|
|
+
|
843 |
103 |
dgisselq |
+#define ALL_DEBUG_OFF false
|
844 |
102 |
dgisselq |
+#define ALL_DEBUG_ON false
|
845 |
|
|
+
|
846 |
|
|
+enum ZIP_BUILTIN_ID_CODE {
|
847 |
|
|
+ ZIP_BUILTIN_RTU,
|
848 |
|
|
+ ZIP_BUILTIN_HALT,
|
849 |
|
|
+ ZIP_BUILTIN_IDLE,
|
850 |
|
|
+ ZIP_BUILTIN_SYSCALL,
|
851 |
|
|
+ ZIP_BUILTIN_SAVE_CONTEXT,
|
852 |
|
|
+ ZIP_BUILTIN_RESTORE_CONTEXT,
|
853 |
|
|
+ ZIP_BUILTIN_BITREV,
|
854 |
|
|
+ ZIP_BUILTIN_CC,
|
855 |
117 |
dgisselq |
+ ZIP_BUILTIN_UCC,
|
856 |
171 |
dgisselq |
+ ZIP_BUILTIN_BUSY,
|
857 |
102 |
dgisselq |
+ ZIP_BUILTIN_MAX
|
858 |
|
|
+};
|
859 |
|
|
+
|
860 |
|
|
+static GTY (()) tree zip_builtins[(int)ZIP_BUILTIN_MAX];
|
861 |
|
|
+static enum insn_code zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
|
862 |
|
|
+
|
863 |
|
|
+
|
864 |
|
|
+#include "gt-zip.h"
|
865 |
|
|
+
|
866 |
|
|
+/* The Global 'targetm' Variable. */
|
867 |
|
|
+struct gcc_target targetm = TARGET_INITIALIZER;
|
868 |
|
|
+
|
869 |
|
|
+
|
870 |
|
|
+enum reg_class zip_reg_class(int);
|
871 |
|
|
+
|
872 |
|
|
+#define LOSE_AND_RETURN(msgid, x) \
|
873 |
|
|
+ do { \
|
874 |
|
|
+ zip_operand_lossage(msgid, x); \
|
875 |
|
|
+ return; \
|
876 |
|
|
+ } while(0)
|
877 |
|
|
+
|
878 |
|
|
+/* Per-function machine data. */
|
879 |
|
|
+struct GTY(()) machine_function
|
880 |
|
|
+{
|
881 |
|
|
+ /* number of pretented arguments for varargs */
|
882 |
|
|
+ int pretend_size;
|
883 |
|
|
+
|
884 |
|
|
+ /* Number of bytes saved on the stack for local variables. */
|
885 |
|
|
+ int local_vars_size;
|
886 |
|
|
+
|
887 |
|
|
+ /* Number of bytes saved on stack for register save area */
|
888 |
|
|
+ int saved_reg_size;
|
889 |
|
|
+ int save_ret;
|
890 |
|
|
+
|
891 |
|
|
+ int sp_fp_offset;
|
892 |
|
|
+ bool fp_needed;
|
893 |
|
|
+ int size_for_adjusting_sp;
|
894 |
|
|
+};
|
895 |
|
|
+
|
896 |
|
|
+/* Allocate a chunk of memory for per-function machine-dependent data. */
|
897 |
|
|
+
|
898 |
|
|
+static struct machine_function *
|
899 |
|
|
+zip_init_machine_status(void) {
|
900 |
|
|
+ return ggc_cleared_alloc<machine_function>();
|
901 |
|
|
+}
|
902 |
|
|
+
|
903 |
|
|
+static void
|
904 |
|
|
+zip_override_options(void)
|
905 |
|
|
+{
|
906 |
|
|
+ init_machine_status = zip_init_machine_status;
|
907 |
|
|
+}
|
908 |
|
|
+
|
909 |
|
|
+enum reg_class
|
910 |
|
|
+zip_reg_class(int regno)
|
911 |
|
|
+{
|
912 |
|
|
+ if (is_ZIP_GENERAL_REG(regno)) {
|
913 |
|
|
+ return GENERAL_REGS;
|
914 |
|
|
+ } else if (is_ZIP_REG(regno)) {
|
915 |
|
|
+ return ALL_REGS;
|
916 |
|
|
+ } return NO_REGS;
|
917 |
|
|
+}
|
918 |
|
|
+
|
919 |
|
|
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
|
920 |
|
|
+static bool
|
921 |
|
|
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
|
922 |
|
|
+ const HOST_WIDE_INT size = int_size_in_bytes(type);
|
923 |
|
|
+ return (size == -1)||(size > UNITS_PER_WORD);
|
924 |
|
|
+}
|
925 |
|
|
+
|
926 |
|
|
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
|
927 |
|
|
+ * insn. Formatted output isn't easily implemented, since we use output operand
|
928 |
|
|
+ * lossage to output the actual message and handle the categorization of the
|
929 |
|
|
+ * error. */
|
930 |
|
|
+
|
931 |
|
|
+static void
|
932 |
|
|
+zip_operand_lossage(const char *msgid, rtx op) {
|
933 |
|
|
+ fprintf(stderr, "Operand lossage??\n");
|
934 |
|
|
+ debug_rtx(op);
|
935 |
|
|
+ zip_debug_rtx(op);
|
936 |
|
|
+ output_operand_lossage("%s", msgid);
|
937 |
|
|
+}
|
938 |
|
|
+
|
939 |
|
|
+/* The PRINT_OPERAND_ADDRESS worker. */
|
940 |
|
|
+void
|
941 |
|
|
+zip_print_operand_address(FILE *file, rtx x) {
|
942 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
943 |
|
|
+
|
944 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
945 |
|
|
+ switch(GET_CODE(x)) {
|
946 |
|
|
+ case REG:
|
947 |
127 |
dgisselq |
+ gcc_assert(is_ZIP_REG(REGNO(x)));
|
948 |
171 |
dgisselq |
+ gcc_assert(REGNO(x) < 16);
|
949 |
102 |
dgisselq |
+ fprintf(file, "(%s)", reg_names[REGNO(x)]);
|
950 |
|
|
+ break;
|
951 |
|
|
+ case SYMBOL_REF:
|
952 |
|
|
+ fprintf(file, "%s", XSTR(x,0));
|
953 |
|
|
+ break;
|
954 |
|
|
+ case LABEL_REF:
|
955 |
|
|
+ x = LABEL_REF_LABEL(x);
|
956 |
|
|
+ case CODE_LABEL:
|
957 |
|
|
+ { char buf[256];
|
958 |
|
|
+ ASM_GENERATE_INTERNAL_LABEL(buf, "L", CODE_LABEL_NUMBER(x));
|
959 |
|
|
+#ifdef ASM_OUTPUT_LABEL_REF
|
960 |
|
|
+ ASM_OUTPUT_LABEL_REF(file, buf);
|
961 |
|
|
+#else
|
962 |
|
|
+ assemble_name(file, buf);
|
963 |
|
|
+#endif
|
964 |
|
|
+ }
|
965 |
|
|
+ break;
|
966 |
|
|
+ case PLUS:
|
967 |
111 |
dgisselq |
+ if (!REG_P(XEXP(x, 0))) {
|
968 |
|
|
+ fprintf(stderr, "Unsupported address construct\n");
|
969 |
|
|
+ zip_debug_rtx(x);
|
970 |
102 |
dgisselq |
+ abort();
|
971 |
127 |
dgisselq |
+ } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0))));
|
972 |
171 |
dgisselq |
+ gcc_assert(REGNO(XEXP(x,0))<16);
|
973 |
127 |
dgisselq |
+ if (CONST_INT_P(XEXP(x, 1))) {
|
974 |
102 |
dgisselq |
+ if (INTVAL(XEXP(x,1))!=0) {
|
975 |
|
|
+ fprintf(file, "%ld(%s)",
|
976 |
135 |
dgisselq |
+ (long)INTVAL(XEXP(x, 1)),
|
977 |
102 |
dgisselq |
+ reg_names[REGNO(XEXP(x, 0))]);
|
978 |
|
|
+ } else {
|
979 |
|
|
+ fprintf(file, "(%s)",
|
980 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
981 |
|
|
+ }
|
982 |
|
|
+ } else if (GET_CODE(XEXP(x,1)) == SYMBOL_REF) {
|
983 |
|
|
+ fprintf(file, "%s(%s)", XSTR(x,0),
|
984 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
985 |
|
|
+ } else if ((GET_CODE(XEXP(x, 1)) == MINUS)
|
986 |
|
|
+ && (GET_CODE(XEXP(XEXP(x, 1), 0))==SYMBOL_REF)
|
987 |
|
|
+ && (GET_CODE(XEXP(XEXP(x, 1), 1))==SYMBOL_REF)) {
|
988 |
|
|
+ fprintf(file, "%s-%s(%s)",
|
989 |
|
|
+ XSTR(XEXP(XEXP(x, 1),0),0),
|
990 |
|
|
+ XSTR(XEXP(XEXP(x, 1),1),0),
|
991 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
992 |
|
|
+ } else
|
993 |
|
|
+ fprintf(file, "#INVALID(%s)",
|
994 |
|
|
+ reg_names[REGNO(XEXP(x, 0))]);
|
995 |
|
|
+ /*
|
996 |
|
|
+ else if (GET_CODE(XEXP(addr, 1)) == LABEL)
|
997 |
|
|
+ fprintf(file, "%s(%s)",
|
998 |
|
|
+ GET_CODE(XEXP(addr, 1)),
|
999 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1000 |
|
|
+ else if ((GET_CODE(XEXP(addr, 1)) == MINUS)
|
1001 |
|
|
+ && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 0))==LABEL)
|
1002 |
|
|
+ && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 1))==LABEL)) {
|
1003 |
|
|
+ fprintf(file, "%s-%s(%s)",
|
1004 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1005 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1006 |
|
|
+ reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
|
1007 |
|
|
+ }
|
1008 |
|
|
+ */
|
1009 |
|
|
+ break;
|
1010 |
|
|
+ // We don't support direct memory addressing within our
|
1011 |
|
|
+ // instruction set, even though the instructions themselves
|
1012 |
|
|
+ // would support direct memory addressing of the lower 18 bits
|
1013 |
|
|
+ // of memory space.
|
1014 |
|
|
+ case MEM:
|
1015 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
1016 |
|
|
+ zip_print_operand_address(file, XEXP(x, 0));
|
1017 |
|
|
+ break;
|
1018 |
111 |
dgisselq |
+ case CONST_INT:
|
1019 |
135 |
dgisselq |
+ fprintf(file, "%ld",(long)INTVAL(x));
|
1020 |
111 |
dgisselq |
+ break;
|
1021 |
102 |
dgisselq |
+ default:
|
1022 |
111 |
dgisselq |
+ fprintf(stderr, "Unknown address format\n");
|
1023 |
|
|
+ zip_debug_rtx(x);
|
1024 |
102 |
dgisselq |
+ abort(); break;
|
1025 |
|
|
+ // output_addr_const(file, x);
|
1026 |
|
|
+ break;
|
1027 |
|
|
+ }
|
1028 |
|
|
+}
|
1029 |
|
|
+
|
1030 |
|
|
+/* The PRINT_OPERAND worker. */
|
1031 |
|
|
+
|
1032 |
|
|
+void
|
1033 |
|
|
+zip_print_operand(FILE *file, rtx x, int code)
|
1034 |
|
|
+{
|
1035 |
|
|
+ rtx operand = x;
|
1036 |
|
|
+ int rgoff = 0;
|
1037 |
|
|
+
|
1038 |
|
|
+ // fprintf(file, "Print Operand!\n");
|
1039 |
|
|
+
|
1040 |
|
|
+ /* New code entries should just be added to the switch below. If
|
1041 |
|
|
+ * handling is finished, just return. If handling was just a
|
1042 |
|
|
+ * modification of the operand, the modified operand should be put in
|
1043 |
|
|
+ * "operand", and then do a break to let default handling
|
1044 |
|
|
+ * (zero-modifier) output the operand.
|
1045 |
|
|
+ */
|
1046 |
|
|
+ switch(code) {
|
1047 |
|
|
+ case 0:
|
1048 |
|
|
+ /* No code, print as usual. */
|
1049 |
|
|
+ break;
|
1050 |
|
|
+ case 'L':
|
1051 |
|
|
+ /* Lower of two registers, print one up */
|
1052 |
|
|
+ rgoff = 1;
|
1053 |
|
|
+ break;
|
1054 |
|
|
+ case 'R':
|
1055 |
|
|
+ case 'H':
|
1056 |
|
|
+ /* Higher of a register pair, print normal */
|
1057 |
|
|
+ break;
|
1058 |
|
|
+
|
1059 |
|
|
+ default:
|
1060 |
|
|
+ LOSE_AND_RETURN("invalid operand modifier letter", x);
|
1061 |
|
|
+ }
|
1062 |
|
|
+
|
1063 |
|
|
+ /* Print an operand as without a modifier letter. */
|
1064 |
|
|
+ switch (GET_CODE(operand)) {
|
1065 |
|
|
+ case REG:
|
1066 |
|
|
+ if (REGNO(operand)+rgoff >= FIRST_PSEUDO_REGISTER)
|
1067 |
|
|
+ internal_error("internal error: bad register: %d", REGNO(operand));
|
1068 |
|
|
+ fprintf(file, "%s", reg_names[REGNO(operand)+rgoff]);
|
1069 |
|
|
+ return;
|
1070 |
|
|
+ case SCRATCH:
|
1071 |
|
|
+ LOSE_AND_RETURN("Need a scratch register", x);
|
1072 |
|
|
+ return;
|
1073 |
|
|
+
|
1074 |
|
|
+ case CODE_LABEL:
|
1075 |
|
|
+ case LABEL_REF:
|
1076 |
|
|
+ case SYMBOL_REF:
|
1077 |
|
|
+ case PLUS:
|
1078 |
|
|
+ PRINT_OPERAND_ADDRESS(file, operand);
|
1079 |
|
|
+ return;
|
1080 |
|
|
+ case MEM:
|
1081 |
|
|
+ PRINT_OPERAND_ADDRESS(file, XEXP(operand, 0));
|
1082 |
|
|
+ return;
|
1083 |
|
|
+
|
1084 |
|
|
+ default:
|
1085 |
|
|
+ /* No need to handle all strange variants, let
|
1086 |
|
|
+ * output_addr_const do it for us.
|
1087 |
|
|
+ */
|
1088 |
|
|
+ if (CONSTANT_P(operand)) {
|
1089 |
|
|
+ output_addr_const(file, operand);
|
1090 |
|
|
+ return;
|
1091 |
|
|
+ }
|
1092 |
|
|
+
|
1093 |
|
|
+ LOSE_AND_RETURN("unexpected operand", x);
|
1094 |
|
|
+ }
|
1095 |
|
|
+}
|
1096 |
|
|
+
|
1097 |
|
|
+static bool
|
1098 |
|
|
+zip_frame_pointer_required(void)
|
1099 |
|
|
+{
|
1100 |
|
|
+ // This should really depend upon whether we have variable sized
|
1101 |
|
|
+ // arguments in our frame or not. Once this fails, let's look
|
1102 |
|
|
+ // at what the problem was and then whether or not we can detect
|
1103 |
|
|
+ // it.
|
1104 |
|
|
+ //
|
1105 |
|
|
+ // Use a GCC global to determine our answer
|
1106 |
103 |
dgisselq |
+ if (cfun->calls_alloca)
|
1107 |
|
|
+ return true;
|
1108 |
102 |
dgisselq |
+ return (frame_pointer_needed);
|
1109 |
|
|
+/*
|
1110 |
|
|
+*/
|
1111 |
|
|
+}
|
1112 |
|
|
+
|
1113 |
|
|
+/* Determine whether or not a register needs to be saved on the stack or not.
|
1114 |
|
|
+ */
|
1115 |
|
|
+static bool
|
1116 |
|
|
+zip_save_reg(int regno) {
|
1117 |
|
|
+ if (regno == 0)
|
1118 |
|
|
+ return ((!crtl->is_leaf)
|
1119 |
|
|
+ ||((df_regs_ever_live_p(0))&&(!call_used_regs[0])));
|
1120 |
|
|
+ else if ((regno == zip_GOT)&&(!ZIP_PIC))
|
1121 |
|
|
+ return ((df_regs_ever_live_p(regno))
|
1122 |
|
|
+ &&(!call_used_regs[regno]));
|
1123 |
|
|
+ else if (regno == zip_FP)
|
1124 |
|
|
+ return((zip_frame_pointer_required())||((df_regs_ever_live_p(regno))
|
1125 |
|
|
+ &&(!call_used_regs[regno])));
|
1126 |
|
|
+ else if (regno < zip_FP)
|
1127 |
|
|
+ return ((df_regs_ever_live_p(regno))
|
1128 |
|
|
+ &&(!call_used_regs[regno]));
|
1129 |
|
|
+ return false;
|
1130 |
|
|
+}
|
1131 |
|
|
+
|
1132 |
|
|
+/* Compute the size of the local area and the size to be adjusted by the
|
1133 |
|
|
+ * prologue and epilogue.
|
1134 |
|
|
+ *
|
1135 |
|
|
+ * Here's what we are looking at (top is the current, bottom is the last ...)
|
1136 |
|
|
+ *
|
1137 |
|
|
+ * Stack Pointer ->
|
1138 |
124 |
dgisselq |
+ * Outgoing arguments
|
1139 |
102 |
dgisselq |
+ * Local variables (could be variable size)
|
1140 |
|
|
+ * Frame Pointer -> (= Stack Pointer + sp_fp_offset)
|
1141 |
|
|
+ * Saved return address, if saved
|
1142 |
|
|
+ * Other Saved registers
|
1143 |
|
|
+ * Saved frame pointer (if used)
|
1144 |
|
|
+ * Saved R12, if used
|
1145 |
|
|
+ * (Stack pointer is not saved)
|
1146 |
171 |
dgisselq |
+ * (PRETEND-ARGS)
|
1147 |
102 |
dgisselq |
+ * Original stack pointer -> (= Stack_Pointer +size_for_adjusting_sp)
|
1148 |
|
|
+ * Called arguments (not passed in registers)
|
1149 |
|
|
+ * Return arguments (not R1, args.pretend_args_size)
|
1150 |
|
|
+ * (Prior function's stack frame ... )
|
1151 |
|
|
+ *
|
1152 |
|
|
+ */
|
1153 |
|
|
+static void
|
1154 |
|
|
+zip_compute_frame(void) {
|
1155 |
|
|
+ int regno;
|
1156 |
|
|
+ int args_size;
|
1157 |
124 |
dgisselq |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
1158 |
102 |
dgisselq |
+
|
1159 |
171 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
|
1160 |
102 |
dgisselq |
+ // gcc_assert(crtl);
|
1161 |
|
|
+ gcc_assert(cfun);
|
1162 |
|
|
+ gcc_assert(cfun->machine);
|
1163 |
|
|
+
|
1164 |
|
|
+ args_size=(ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
|
1165 |
|
|
+
|
1166 |
|
|
+ if(crtl->args.pretend_args_size > 0) {
|
1167 |
|
|
+ args_size += crtl->args.pretend_args_size;
|
1168 |
171 |
dgisselq |
+ if (dbg) fprintf(stderr, "%s pretend_args_size : %d\n", current_function_name(),
|
1169 |
|
|
+ crtl->args.pretend_args_size);
|
1170 |
102 |
dgisselq |
+ cfun->machine->pretend_size = crtl->args.pretend_args_size;
|
1171 |
|
|
+ }
|
1172 |
|
|
+
|
1173 |
|
|
+ cfun->machine->local_vars_size = get_frame_size();
|
1174 |
|
|
+
|
1175 |
|
|
+ // Save callee-saved registers.
|
1176 |
|
|
+ cfun->machine->saved_reg_size = 0;
|
1177 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1178 |
|
|
+ if (zip_save_reg(regno))
|
1179 |
|
|
+ cfun->machine->saved_reg_size ++;
|
1180 |
|
|
+ }
|
1181 |
|
|
+
|
1182 |
|
|
+ cfun->machine->fp_needed = (zip_frame_pointer_required());
|
1183 |
|
|
+
|
1184 |
|
|
+ if ((cfun->machine->fp_needed)&&
|
1185 |
|
|
+ (!df_regs_ever_live_p(zip_FP))) {
|
1186 |
|
|
+ cfun->machine->saved_reg_size ++;
|
1187 |
|
|
+ }
|
1188 |
|
|
+
|
1189 |
171 |
dgisselq |
+ cfun->machine->sp_fp_offset = crtl->outgoing_args_size
|
1190 |
|
|
+ + cfun->machine->local_vars_size;
|
1191 |
102 |
dgisselq |
+ cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
|
1192 |
|
|
+ + cfun->machine->saved_reg_size
|
1193 |
|
|
+ + args_size;
|
1194 |
124 |
dgisselq |
+ if(dbg) {
|
1195 |
171 |
dgisselq |
+ fprintf(stderr, "\t---- STACK PTR ----\n");
|
1196 |
|
|
+ fprintf(stderr, "\tOUTGOIN-SIZE: %d\n",
|
1197 |
|
|
+ crtl->outgoing_args_size);
|
1198 |
124 |
dgisselq |
+ fprintf(stderr, "\tLOCALS-SIZE : %d\n",
|
1199 |
|
|
+ cfun->machine->local_vars_size);
|
1200 |
171 |
dgisselq |
+ fprintf(stderr, "\t---- FRAME PTR ----%s\n",
|
1201 |
|
|
+ cfun->machine->fp_needed?"":" (Eliminated)");
|
1202 |
124 |
dgisselq |
+ fprintf(stderr, "\tREGISTERS : %d\n",
|
1203 |
|
|
+ cfun->machine->saved_reg_size);
|
1204 |
171 |
dgisselq |
+ fprintf(stderr, "\tPRETEND SIZE: %d\n",
|
1205 |
|
|
+ crtl->args.pretend_args_size);
|
1206 |
|
|
+ fprintf(stderr, "\t---- ARG PTR (Original SP, should be eliminated) ----\n");
|
1207 |
|
|
+ fprintf(stderr, "\t----\n");
|
1208 |
|
|
+ fprintf(stderr, "\tARGS-SIZE : %d\n", args_size);
|
1209 |
124 |
dgisselq |
+ fprintf(stderr, "\tSP_FP_OFFSET: %d\n",
|
1210 |
|
|
+ cfun->machine->sp_fp_offset);
|
1211 |
|
|
+ fprintf(stderr, "\tSP-ADJUSTMNT: %d\n",
|
1212 |
|
|
+ cfun->machine->size_for_adjusting_sp);
|
1213 |
|
|
+ }
|
1214 |
102 |
dgisselq |
+}
|
1215 |
|
|
+
|
1216 |
|
|
+void
|
1217 |
|
|
+zip_expand_prologue(void) {
|
1218 |
|
|
+ rtx insn;
|
1219 |
|
|
+
|
1220 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
1221 |
|
|
+ zip_compute_frame();
|
1222 |
|
|
+
|
1223 |
124 |
dgisselq |
+ if (dbg) fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
|
1224 |
127 |
dgisselq |
+ if (dbg) fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
|
1225 |
|
|
+ cfun->machine->sp_fp_offset);
|
1226 |
102 |
dgisselq |
+ if (cfun->machine->size_for_adjusting_sp != 0) {
|
1227 |
138 |
dgisselq |
+ insn = emit_insn(gen_subsi3_reg_clobber(stack_pointer_rtx,
|
1228 |
102 |
dgisselq |
+ stack_pointer_rtx,
|
1229 |
|
|
+ gen_int_mode(cfun->machine->size_for_adjusting_sp,
|
1230 |
|
|
+ SImode)));
|
1231 |
|
|
+ // cfun->machine->sp_fp_offset
|
1232 |
|
|
+
|
1233 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1234 |
|
|
+ }
|
1235 |
|
|
+
|
1236 |
|
|
+ {
|
1237 |
|
|
+ int offset = 0, regno;
|
1238 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1239 |
|
|
+ if (zip_save_reg(regno)) {
|
1240 |
127 |
dgisselq |
+ if (dbg) fprintf(stderr,
|
1241 |
|
|
+ "PROLOGUE: Saving R%d in %d+%d(SP)\n",
|
1242 |
|
|
+ regno, cfun->machine->sp_fp_offset,
|
1243 |
|
|
+ offset);
|
1244 |
124 |
dgisselq |
+ insn=emit_insn(gen_movsi_sto_off(
|
1245 |
|
|
+ stack_pointer_rtx,
|
1246 |
|
|
+ GEN_INT(cfun->machine->sp_fp_offset
|
1247 |
|
|
+ +offset++),
|
1248 |
102 |
dgisselq |
+ gen_rtx_REG(SImode, regno)));
|
1249 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1250 |
|
|
+ }
|
1251 |
|
|
+ }
|
1252 |
103 |
dgisselq |
+ if (dbg) fprintf(stderr, "%d registers saved%s\n", offset,
|
1253 |
|
|
+ (crtl->saves_all_registers)?", should be all of them":", less than all");
|
1254 |
102 |
dgisselq |
+ }
|
1255 |
|
|
+
|
1256 |
|
|
+ if (cfun->machine->fp_needed) {
|
1257 |
|
|
+ if (dbg) zip_debug_rtx(stack_pointer_rtx);
|
1258 |
|
|
+ if (dbg) zip_debug_rtx(frame_pointer_rtx);
|
1259 |
|
|
+ insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
|
1260 |
124 |
dgisselq |
+ stack_pointer_rtx,
|
1261 |
|
|
+ GEN_INT(cfun->machine->sp_fp_offset)));
|
1262 |
102 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1263 |
103 |
dgisselq |
+ if (dbg) fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
|
1264 |
102 |
dgisselq |
+ }
|
1265 |
|
|
+}
|
1266 |
|
|
+
|
1267 |
|
|
+bool
|
1268 |
|
|
+zip_use_return_insn(void)
|
1269 |
|
|
+{
|
1270 |
|
|
+ if ((!reload_completed)||(cfun->machine->fp_needed)
|
1271 |
|
|
+ ||(get_frame_size()!=0)) {
|
1272 |
|
|
+ // If R0 ever gets pushed to the stack, then we cannot
|
1273 |
|
|
+ // use a master return from anywhere. We need to clean up the
|
1274 |
|
|
+ // stack first.
|
1275 |
|
|
+ if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
|
1276 |
|
|
+ &&(!call_used_regs[0]))) {
|
1277 |
|
|
+ return false;
|
1278 |
|
|
+ }
|
1279 |
|
|
+ }
|
1280 |
|
|
+ zip_compute_frame();
|
1281 |
|
|
+ return (cfun->machine->size_for_adjusting_sp == 0);
|
1282 |
|
|
+}
|
1283 |
|
|
+
|
1284 |
|
|
+/* As per the notes in M68k.c, quote the function epilogue should not depend
|
1285 |
|
|
+ * upon the current stack pointer. It should use the frame poitner only,
|
1286 |
|
|
+ * if there is a frame pointer. This is mandatory because of alloca; we also
|
1287 |
|
|
+ * take advantage of it to omit stack adjustments before returning ...
|
1288 |
|
|
+ *
|
1289 |
|
|
+ * Let's see if we can use their approach here.
|
1290 |
|
|
+ *
|
1291 |
|
|
+ * We can't. Consider our choices:
|
1292 |
|
|
+ * LOD (FP),R0
|
1293 |
|
|
+ * LOD 1(FP),R4
|
1294 |
|
|
+ * LOD 2(FP),R5
|
1295 |
|
|
+ * LOD 3(FP),R6
|
1296 |
|
|
+ * LOD 4(FP),FP
|
1297 |
|
|
+ * ... Then what is the stack pointer?
|
1298 |
|
|
+ * or
|
1299 |
|
|
+ * LOD (FP),R0
|
1300 |
|
|
+ * LOD 1(FP),R4
|
1301 |
|
|
+ * LOD 2(FP),R5
|
1302 |
|
|
+ * LOD 3(FP),R6
|
1303 |
|
|
+ * MOV FP,SP
|
1304 |
|
|
+ * LOD 4(SP),FP
|
1305 |
|
|
+ * ... Which suffers unnecessary pipeline stalls, and certainly doesn't
|
1306 |
|
|
+ * exploit our pipeline memory function
|
1307 |
|
|
+ * or
|
1308 |
|
|
+ * MOV FP,SP
|
1309 |
|
|
+ * LOD (SP),R0
|
1310 |
|
|
+ * LOD 1(SP),R4
|
1311 |
|
|
+ * LOD 2(SP),R5
|
1312 |
|
|
+ * LOD 3(SP),R6
|
1313 |
|
|
+ * LOD 4(SP),FP
|
1314 |
|
|
+ * Which will be our choice. Note that we do use the stack pointer, eventually.
|
1315 |
|
|
+ *
|
1316 |
|
|
+ */
|
1317 |
|
|
+void
|
1318 |
|
|
+zip_expand_epilogue(void) {
|
1319 |
|
|
+ int regno, offset;
|
1320 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
1321 |
138 |
dgisselq |
+ rtx insn;
|
1322 |
102 |
dgisselq |
+
|
1323 |
|
|
+ zip_compute_frame();
|
1324 |
|
|
+
|
1325 |
|
|
+ if (dbg) fprintf(stderr, "EPILOG::\n");
|
1326 |
|
|
+ if (cfun->machine->fp_needed) {
|
1327 |
124 |
dgisselq |
+ // This is done special--if you can't trust the stack pointer
|
1328 |
|
|
+ // enough so that you must have a frame pointer, then you can't
|
1329 |
|
|
+ // trust its offset enough to restore from it. Hence, we start
|
1330 |
|
|
+ // by moving the frame pointer to the stack pointer to recover
|
1331 |
|
|
+ // the stack pointer back to a usable value.
|
1332 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
|
1333 |
138 |
dgisselq |
+ insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
|
1334 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1335 |
102 |
dgisselq |
+ }
|
1336 |
|
|
+
|
1337 |
|
|
+ if (cfun->machine->saved_reg_size != 0) {
|
1338 |
124 |
dgisselq |
+ if (cfun->machine->fp_needed)
|
1339 |
|
|
+ offset = 0;
|
1340 |
|
|
+ else
|
1341 |
|
|
+ offset = cfun->machine->sp_fp_offset;
|
1342 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
|
1343 |
|
|
+ for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
|
1344 |
|
|
+ if (zip_save_reg(regno)) {
|
1345 |
|
|
+ if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d\n", regno);
|
1346 |
138 |
dgisselq |
+ rtx reg = gen_rtx_REG(SImode, regno);
|
1347 |
|
|
+ insn = emit_insn(gen_movsi_lod_off(
|
1348 |
|
|
+ reg,
|
1349 |
124 |
dgisselq |
+ stack_pointer_rtx,
|
1350 |
|
|
+ GEN_INT(offset++)));
|
1351 |
138 |
dgisselq |
+ add_reg_note(insn, REG_CFA_RESTORE, reg);
|
1352 |
|
|
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1353 |
102 |
dgisselq |
+ }
|
1354 |
|
|
+ }
|
1355 |
|
|
+ }
|
1356 |
|
|
+
|
1357 |
124 |
dgisselq |
+ if (cfun->machine->fp_needed) {
|
1358 |
|
|
+ // Restore the stack pointer back to the original, the
|
1359 |
|
|
+ // difference being the difference from the frame pointer
|
1360 |
|
|
+ // to the original stack
|
1361 |
138 |
dgisselq |
+ insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
|
1362 |
|
|
+ stack_pointer_rtx,
|
1363 |
124 |
dgisselq |
+ GEN_INT(cfun->machine->size_for_adjusting_sp
|
1364 |
|
|
+ -cfun->machine->sp_fp_offset)));
|
1365 |
138 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1366 |
124 |
dgisselq |
+ } else {
|
1367 |
|
|
+ // else now the difference is between the stack pointer and
|
1368 |
|
|
+ // the original stack pointer.
|
1369 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
|
1370 |
|
|
+ cfun->machine->size_for_adjusting_sp);
|
1371 |
138 |
dgisselq |
+ insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
|
1372 |
|
|
+ stack_pointer_rtx,
|
1373 |
124 |
dgisselq |
+ GEN_INT(cfun->machine->size_for_adjusting_sp)));
|
1374 |
138 |
dgisselq |
+ RTX_FRAME_RELATED_P(insn) = 1;
|
1375 |
102 |
dgisselq |
+ }
|
1376 |
|
|
+ if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
|
1377 |
|
|
+
|
1378 |
138 |
dgisselq |
+ // The return RTX is not allowed to be frame related
|
1379 |
|
|
+ insn = emit_jump_insn(ret_rtx);
|
1380 |
|
|
+ // RTX_FRAME_RELATED_P(insn) = 1;
|
1381 |
102 |
dgisselq |
+}
|
1382 |
|
|
+
|
1383 |
|
|
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
|
1384 |
|
|
+ *
|
1385 |
|
|
+ * We currently only support calculating the return address for the current
|
1386 |
|
|
+ * frame.
|
1387 |
|
|
+ */
|
1388 |
|
|
+
|
1389 |
|
|
+/*
|
1390 |
|
|
+rtx
|
1391 |
|
|
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
|
1392 |
|
|
+{
|
1393 |
|
|
+ if (count)
|
1394 |
|
|
+ return NULL_RTX;
|
1395 |
|
|
+
|
1396 |
|
|
+ zip_compute_frame();
|
1397 |
|
|
+
|
1398 |
|
|
+ // saved return address for current function is at fp - 1
|
1399 |
|
|
+ if (cfun->machine->save_ret)
|
1400 |
|
|
+ return gen_rtx_MEM(Pmode, plus_constant(frame_pointer_rtx,
|
1401 |
|
|
+ -UNITS_PER_WORD));
|
1402 |
|
|
+ return get_hard_reg_initial_val(Pmode, RETURN_ADDRESS_REGNUM);
|
1403 |
|
|
+}
|
1404 |
|
|
+*/
|
1405 |
|
|
+
|
1406 |
|
|
+/* Implements the macro INITIAL_ELIMINATION_OFFSET,
|
1407 |
|
|
+ * return the OFFSET.
|
1408 |
|
|
+ */
|
1409 |
|
|
+int
|
1410 |
|
|
+zip_initial_elimination_offset(int from, int to) {
|
1411 |
|
|
+ int ret = 0;
|
1412 |
|
|
+ zip_compute_frame();
|
1413 |
|
|
+
|
1414 |
171 |
dgisselq |
+/*
|
1415 |
102 |
dgisselq |
+ if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
|
1416 |
|
|
+ ret = cfun->machine->sp_fp_offset;
|
1417 |
117 |
dgisselq |
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
|
1418 |
171 |
dgisselq |
+ // Since the ARG_POINTER_REGNUM is defined to be identical
|
1419 |
|
|
+ // to the FRAME_POINTER_REGNUM, this "if" will never ever
|
1420 |
|
|
+ // get called.
|
1421 |
117 |
dgisselq |
+ ret = cfun->machine->sp_fp_offset;
|
1422 |
102 |
dgisselq |
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
|
1423 |
171 |
dgisselq |
+ // Since we define ARG_POINTER_REGNUM to be FRAME_POINTER_REGNUM
|
1424 |
|
|
+ // we're asked for the offset between the frame pointer and
|
1425 |
|
|
+ // itself. The result had better be zero.
|
1426 |
|
|
+ //
|
1427 |
117 |
dgisselq |
+ ret = 0;
|
1428 |
102 |
dgisselq |
+ } else {
|
1429 |
|
|
+ abort();
|
1430 |
|
|
+ }
|
1431 |
171 |
dgisselq |
+*/
|
1432 |
102 |
dgisselq |
+
|
1433 |
171 |
dgisselq |
+ // Let's try using an ARG_POINTER != FRAME_POINTER
|
1434 |
|
|
+ if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
|
1435 |
|
|
+ ret = cfun->machine->sp_fp_offset;
|
1436 |
|
|
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
|
1437 |
|
|
+ // Since the ARG_POINTER_REGNUM is defined to be identical
|
1438 |
|
|
+ // to the FRAME_POINTER_REGNUM, this "if" will never ever
|
1439 |
|
|
+ // get called.
|
1440 |
|
|
+ ret = cfun->machine->size_for_adjusting_sp;
|
1441 |
|
|
+ } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
|
1442 |
|
|
+ ret = cfun->machine->size_for_adjusting_sp
|
1443 |
|
|
+ - cfun->machine->sp_fp_offset;
|
1444 |
|
|
+ } else {
|
1445 |
|
|
+ abort();
|
1446 |
|
|
+ }
|
1447 |
|
|
+
|
1448 |
102 |
dgisselq |
+ return ret;
|
1449 |
|
|
+}
|
1450 |
|
|
+
|
1451 |
|
|
+/*
|
1452 |
|
|
+ * Code taken from m68k ...
|
1453 |
|
|
+ */
|
1454 |
|
|
+static bool
|
1455 |
|
|
+zip_can_eliminate(int from, int to)
|
1456 |
|
|
+{
|
1457 |
|
|
+ // fprintf(stderr, "CAN_ELIMINATE::QUERYING(%d,%d)\n", from, to);
|
1458 |
|
|
+ if ((from == zip_FP)&&(to == zip_SP))
|
1459 |
|
|
+ return !cfun->machine->fp_needed;
|
1460 |
|
|
+ return true;
|
1461 |
|
|
+}
|
1462 |
|
|
+
|
1463 |
|
|
+/*
|
1464 |
|
|
+static void
|
1465 |
|
|
+zip_basic_check(void)
|
1466 |
|
|
+{
|
1467 |
|
|
+ gcc_assert(mode_base_align[SImode]==4);
|
1468 |
|
|
+ if ((BITS_PER_UNIT != 32)
|
1469 |
|
|
+ ||(GET_MODE_SIZE(SImode)!=1)
|
1470 |
|
|
+ ||(GET_MODE_SIZE(DImode)!=1)
|
1471 |
|
|
+ ||(HARD_REGNO_NREGS(0,SImode)!=1)) {
|
1472 |
|
|
+ printf("SIZEOF(SIMode) == %d\n", GET_MODE_SIZE(SImode));
|
1473 |
|
|
+ printf("BITS_PER_UNIT == %d\n", BITS_PER_UNIT);
|
1474 |
|
|
+ gcc_assert(BITS_PER_UNIT==32);
|
1475 |
|
|
+ gcc_assert(GET_MODE_SIZE(SImode)==1);
|
1476 |
|
|
+ gcc_assert(HARD_REGNO_NREGS(0,SImode)==1);
|
1477 |
|
|
+ }
|
1478 |
|
|
+}
|
1479 |
|
|
+*/
|
1480 |
|
|
+
|
1481 |
|
|
+#define zip_basic_check()
|
1482 |
|
|
+
|
1483 |
171 |
dgisselq |
+/* Compute the number of word sized registers needed to hold a function
|
1484 |
102 |
dgisselq |
+ * argument of mode INT_MODE and tree type TYPE.
|
1485 |
|
|
+ */
|
1486 |
|
|
+int
|
1487 |
|
|
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
|
1488 |
|
|
+ int size;
|
1489 |
|
|
+
|
1490 |
|
|
+ zip_basic_check();
|
1491 |
|
|
+
|
1492 |
|
|
+ if (targetm.calls.must_pass_in_stack(mode, type))
|
1493 |
|
|
+ return 0;
|
1494 |
|
|
+
|
1495 |
|
|
+ if ((type)&&(mode == BLKmode))
|
1496 |
|
|
+ size = int_size_in_bytes(type);
|
1497 |
|
|
+ else
|
1498 |
|
|
+ size = GET_MODE_SIZE(mode);
|
1499 |
|
|
+
|
1500 |
|
|
+ return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
|
1501 |
|
|
+}
|
1502 |
|
|
+
|
1503 |
|
|
+static void
|
1504 |
|
|
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
|
1505 |
|
|
+ const_tree type, bool named ATTRIBUTE_UNUSED) {
|
1506 |
|
|
+ CUMULATIVE_ARGS *cum;
|
1507 |
|
|
+ int nreg;
|
1508 |
|
|
+
|
1509 |
|
|
+ zip_basic_check();
|
1510 |
|
|
+
|
1511 |
|
|
+ cum = get_cumulative_args(ca);
|
1512 |
|
|
+ nreg = zip_num_arg_regs(mode, type);
|
1513 |
|
|
+ if (((*cum)+nreg) > NUM_ARG_REGS)
|
1514 |
|
|
+ (*cum) = NUM_ARG_REGS;
|
1515 |
|
|
+ else
|
1516 |
|
|
+ (*cum) += nreg;
|
1517 |
|
|
+}
|
1518 |
|
|
+
|
1519 |
|
|
+static rtx
|
1520 |
|
|
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
|
1521 |
|
|
+ const_tree type ATTRIBUTE_UNUSED, bool named) {
|
1522 |
|
|
+ CUMULATIVE_ARGS *cum;
|
1523 |
|
|
+
|
1524 |
|
|
+ zip_basic_check();
|
1525 |
|
|
+
|
1526 |
|
|
+
|
1527 |
|
|
+ if (!named)
|
1528 |
|
|
+ return NULL_RTX;
|
1529 |
|
|
+ //if (targetm.calls.must_pass_in_stack(mode, type))
|
1530 |
|
|
+ //return NULL_RTX;
|
1531 |
|
|
+ cum = get_cumulative_args(ca);
|
1532 |
|
|
+
|
1533 |
|
|
+ if ((*cum) >= NUM_ARG_REGS)
|
1534 |
|
|
+ return NULL_RTX;
|
1535 |
|
|
+ return
|
1536 |
|
|
+ gen_rtx_REG(mode, (*cum)+1);
|
1537 |
|
|
+}
|
1538 |
|
|
+
|
1539 |
122 |
dgisselq |
+void zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
|
1540 |
|
|
+ bool preserve_op0)
|
1541 |
|
|
+{
|
1542 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
1543 |
102 |
dgisselq |
+
|
1544 |
122 |
dgisselq |
+ if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
|
1545 |
|
|
+ if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
|
1546 |
|
|
+ if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
|
1547 |
|
|
+ if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
|
1548 |
|
|
+
|
1549 |
|
|
+ if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
|
1550 |
|
|
+ rtx tem = *op0;
|
1551 |
|
|
+ *op0 = *op1;
|
1552 |
|
|
+ *op1 = tem;
|
1553 |
|
|
+ *code = (int)swap_condition((enum rtx_code)*code);
|
1554 |
|
|
+ }
|
1555 |
|
|
+
|
1556 |
|
|
+ if ((*code == LE)||(*code == LEU)||(*code == GTU)) {
|
1557 |
|
|
+ int offset = 1; // (*code == GTU) ? 1 : -1;
|
1558 |
|
|
+ bool swap = false;
|
1559 |
|
|
+
|
1560 |
|
|
+ if (CONST_INT_P(*op1)) {
|
1561 |
|
|
+ *op1 = GEN_INT(INTVAL(*op1)+offset);
|
1562 |
|
|
+ swap = true;
|
1563 |
|
|
+ } else if (REG_P(*op1)) {
|
1564 |
138 |
dgisselq |
+ *op1 = plus_constant(GET_MODE(*op1), *op1, offset, true);
|
1565 |
122 |
dgisselq |
+ swap = true;
|
1566 |
|
|
+ } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
|
1567 |
|
|
+ *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
|
1568 |
|
|
+ INTVAL(XEXP(*op1,1))+offset);
|
1569 |
|
|
+ swap = true;
|
1570 |
|
|
+ } if (swap) {
|
1571 |
|
|
+ if (*code == LE)
|
1572 |
|
|
+ (*code)= LT;
|
1573 |
|
|
+ else if (*code == LEU)
|
1574 |
|
|
+ (*code)= LTU;
|
1575 |
|
|
+ else // (*code == GTU)
|
1576 |
|
|
+ (*code) = GEU;
|
1577 |
|
|
+ }
|
1578 |
|
|
+ }
|
1579 |
|
|
+}
|
1580 |
|
|
+
|
1581 |
|
|
+static bool
|
1582 |
|
|
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
|
1583 |
|
|
+ *a = zip_CC;
|
1584 |
|
|
+ *b = INVALID_REGNUM;
|
1585 |
|
|
+ return true;
|
1586 |
|
|
+}
|
1587 |
|
|
+
|
1588 |
|
|
+
|
1589 |
102 |
dgisselq |
+/* totally buggy - we can't return pointers to nested functions */
|
1590 |
|
|
+static void
|
1591 |
|
|
+zip_asm_trampoline_template(FILE *f) {
|
1592 |
|
|
+ // Whereas at one time I thought I wouldn't need it, now I know I
|
1593 |
|
|
+ // need this trampoline function, although it is for a completely
|
1594 |
|
|
+ // different purpose than the one I was familiar with.
|
1595 |
138 |
dgisselq |
+ fprintf(f, "\tbrev\t0,r1\n");
|
1596 |
|
|
+ fprintf(f, "\tldilo\t0,r1\n");
|
1597 |
102 |
dgisselq |
+ fprintf(f, "\tjmp r1\n");
|
1598 |
|
|
+}
|
1599 |
|
|
+
|
1600 |
|
|
+/* Worker function for TARGET_TRAMPOLINE_INIT. */
|
1601 |
|
|
+static void
|
1602 |
|
|
+zip_trampoline_init(rtx m_tramp ATTRIBUTE_UNUSED,
|
1603 |
|
|
+ tree fndecl ATTRIBUTE_UNUSED,
|
1604 |
|
|
+ rtx chain_value ATTRIBUTE_UNUSED) {
|
1605 |
|
|
+// #warning "This needs to be filled out"
|
1606 |
|
|
+ abort();
|
1607 |
|
|
+}
|
1608 |
|
|
+
|
1609 |
|
|
+static tree
|
1610 |
|
|
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
|
1611 |
|
|
+ tree type)
|
1612 |
|
|
+{
|
1613 |
|
|
+ tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
|
1614 |
|
|
+ zip_basic_check();
|
1615 |
|
|
+
|
1616 |
|
|
+ if(t) {
|
1617 |
|
|
+ zip_builtins[code] = t;
|
1618 |
|
|
+ zip_builtins_icode[code] = icode;
|
1619 |
|
|
+ }
|
1620 |
|
|
+
|
1621 |
|
|
+ return t;
|
1622 |
|
|
+
|
1623 |
|
|
+}
|
1624 |
|
|
+
|
1625 |
|
|
+void zip_init_builtins(void) {
|
1626 |
|
|
+ zip_basic_check();
|
1627 |
|
|
+
|
1628 |
|
|
+ tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
|
1629 |
|
|
+#ifdef HAVE_zip_rtu
|
1630 |
|
|
+ def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
|
1631 |
|
|
+#endif
|
1632 |
|
|
+#ifdef HAVE_zip_halt
|
1633 |
|
|
+ def_builtin("zip_halt", CODE_FOR_zip_halt, ZIP_BUILTIN_HALT, void_ftype_void);
|
1634 |
|
|
+#endif
|
1635 |
171 |
dgisselq |
+#ifdef HAVE_zip_busy
|
1636 |
|
|
+ def_builtin("zip_busy", CODE_FOR_zip_busy, ZIP_BUILTIN_BUSY, void_ftype_void);
|
1637 |
|
|
+#endif
|
1638 |
102 |
dgisselq |
+#ifdef HAVE_zip_idle
|
1639 |
|
|
+ def_builtin("zip_idle", CODE_FOR_zip_idle, ZIP_BUILTIN_IDLE, void_ftype_void);
|
1640 |
|
|
+#endif
|
1641 |
|
|
+
|
1642 |
|
|
+#ifdef HAVE_zip_syscall
|
1643 |
|
|
+// Support int SYSCALL(callID, int a, int b, int c);
|
1644 |
|
|
+ def_builtin("zip_syscall", CODE_FOR_zip_syscall, ZIP_BUILTIN_SYSCALL,
|
1645 |
|
|
+ build_function_type_list(void_type_node, NULL_TREE));
|
1646 |
|
|
+#endif
|
1647 |
|
|
+
|
1648 |
|
|
+#ifdef HAVE_zip_save_context
|
1649 |
|
|
+ def_builtin("zip_save_context", CODE_FOR_zip_save_context, ZIP_BUILTIN_SAVE_CONTEXT,
|
1650 |
|
|
+ build_function_type_list(void_type_node, ptr_type_node, 0));
|
1651 |
|
|
+#endif
|
1652 |
|
|
+
|
1653 |
|
|
+#ifdef HAVE_zip_restore_context
|
1654 |
|
|
+ def_builtin("zip_restore_context", CODE_FOR_zip_restore_context, ZIP_BUILTIN_RESTORE_CONTEXT,
|
1655 |
|
|
+ build_function_type_list(void_type_node, ptr_type_node, 0));
|
1656 |
|
|
+#endif
|
1657 |
|
|
+
|
1658 |
|
|
+#ifdef HAVE_zip_bitrev
|
1659 |
|
|
+ def_builtin("zip_bitrev", CODE_FOR_zip_bitrev, ZIP_BUILTIN_BITREV,
|
1660 |
|
|
+ build_function_type_list(unsigned_type_node, unsigned_type_node,
|
1661 |
|
|
+ NULL_TREE));
|
1662 |
|
|
+#endif
|
1663 |
|
|
+
|
1664 |
|
|
+#ifdef HAVE_zip_cc
|
1665 |
|
|
+ def_builtin("zip_cc", CODE_FOR_zip_cc, ZIP_BUILTIN_CC,
|
1666 |
|
|
+ build_function_type_list(unsigned_type_node, NULL_TREE));
|
1667 |
|
|
+#endif
|
1668 |
|
|
+
|
1669 |
117 |
dgisselq |
+#ifdef HAVE_zip_ucc
|
1670 |
|
|
+ def_builtin("zip_ucc", CODE_FOR_zip_ucc, ZIP_BUILTIN_UCC,
|
1671 |
|
|
+ build_function_type_list(unsigned_type_node, NULL_TREE));
|
1672 |
|
|
+#endif
|
1673 |
|
|
+
|
1674 |
102 |
dgisselq |
+}
|
1675 |
|
|
+
|
1676 |
|
|
+static tree
|
1677 |
|
|
+zip_builtin_decl(unsigned zip_builtin_code, bool initialize_p ATTRIBUTE_UNUSED)
|
1678 |
|
|
+{
|
1679 |
|
|
+ if (zip_builtin_code >= ZIP_BUILTIN_MAX)
|
1680 |
|
|
+ return error_mark_node;
|
1681 |
|
|
+
|
1682 |
|
|
+ return zip_builtins[zip_builtin_code];
|
1683 |
|
|
+}
|
1684 |
|
|
+
|
1685 |
|
|
+static rtx
|
1686 |
|
|
+zip_expand_builtin(tree exp, rtx target,
|
1687 |
|
|
+ rtx subtarget ATTRIBUTE_UNUSED,
|
1688 |
|
|
+ machine_mode tmode ATTRIBUTE_UNUSED,
|
1689 |
|
|
+ int ignore ATTRIBUTE_UNUSED) {
|
1690 |
|
|
+
|
1691 |
|
|
+ tree fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
|
1692 |
|
|
+ bool nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
|
1693 |
|
|
+ enum ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
|
1694 |
|
|
+ enum insn_code icode = zip_builtins_icode[code];
|
1695 |
|
|
+ rtx pat, op[5];
|
1696 |
|
|
+ call_expr_arg_iterator iter;
|
1697 |
|
|
+ tree arg;
|
1698 |
|
|
+
|
1699 |
|
|
+ if ((code == ZIP_BUILTIN_SAVE_CONTEXT)
|
1700 |
|
|
+ ||(code == ZIP_BUILTIN_RESTORE_CONTEXT)) {
|
1701 |
|
|
+ arg = first_call_expr_arg(exp, &iter);
|
1702 |
|
|
+ if (arg == error_mark_node)
|
1703 |
|
|
+ return NULL_RTX;
|
1704 |
|
|
+ op[0] = expand_normal(arg);
|
1705 |
|
|
+ if (GET_CODE(op[0]) != REG)
|
1706 |
|
|
+ op[0] = force_reg(Pmode, op[0]);
|
1707 |
|
|
+ pat = GEN_FCN(icode)(op[0]);
|
1708 |
|
|
+ } else if (code == ZIP_BUILTIN_BITREV) {
|
1709 |
|
|
+ arg = first_call_expr_arg(exp, &iter);
|
1710 |
|
|
+ if (arg == error_mark_node) {
|
1711 |
|
|
+ return NULL_RTX;
|
1712 |
|
|
+ }
|
1713 |
|
|
+ op[0] = expand_normal(arg);
|
1714 |
|
|
+ if (!target)
|
1715 |
|
|
+ target = gen_reg_rtx(SImode);
|
1716 |
|
|
+ pat = GEN_FCN(icode)(target, op[0]);
|
1717 |
117 |
dgisselq |
+ } else if ((code == ZIP_BUILTIN_CC)||(code == ZIP_BUILTIN_UCC)) {
|
1718 |
102 |
dgisselq |
+ if (!target)
|
1719 |
|
|
+ target = gen_reg_rtx(SImode);
|
1720 |
|
|
+ pat = GEN_FCN(icode)(target);
|
1721 |
|
|
+ } else // RTU, HALT, IDLE
|
1722 |
|
|
+ pat = GEN_FCN(icode)();
|
1723 |
|
|
+ if (!pat)
|
1724 |
|
|
+ return NULL_RTX;
|
1725 |
|
|
+ emit_insn(pat);
|
1726 |
|
|
+ return (nonvoid ? target : const0_rtx);
|
1727 |
|
|
+}
|
1728 |
|
|
+
|
1729 |
|
|
+static bool
|
1730 |
|
|
+zip_scalar_mode_supported_p(enum machine_mode mode) {
|
1731 |
|
|
+ zip_basic_check();
|
1732 |
|
|
+
|
1733 |
|
|
+ return ((mode)==SImode)||((mode)==DImode); // ||((mode)==SFmode);
|
1734 |
|
|
+}
|
1735 |
|
|
+
|
1736 |
|
|
+static bool
|
1737 |
|
|
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode) {
|
1738 |
|
|
+ return ((mode)==SFmode)||((mode)==DFmode);
|
1739 |
|
|
+}
|
1740 |
|
|
+
|
1741 |
|
|
+static int
|
1742 |
|
|
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
|
1743 |
|
|
+ enum machine_mode mode ATTRIBUTE_UNUSED,
|
1744 |
|
|
+ addr_space_t as ATTRIBUTE_UNUSED, bool spd ATTRIBUTE_UNUSED) {
|
1745 |
|
|
+ return 1;
|
1746 |
|
|
+}
|
1747 |
|
|
+
|
1748 |
|
|
+static bool
|
1749 |
|
|
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
|
1750 |
|
|
+ addr_space_t as ATTRIBUTE_UNUSED) {
|
1751 |
|
|
+ return false;
|
1752 |
|
|
+}
|
1753 |
|
|
+
|
1754 |
|
|
+/*
|
1755 |
|
|
+static void
|
1756 |
|
|
+zip_asm_output_anchor(rtx x) {
|
1757 |
|
|
+ printf("ANCHOR: OP(%d)\n", GET_CODE(x));
|
1758 |
|
|
+}
|
1759 |
|
|
+*/
|
1760 |
|
|
+
|
1761 |
|
|
+static void
|
1762 |
|
|
+zip_debug_print(const char *pfx, int lvl, const char *str) {
|
1763 |
|
|
+ int i;
|
1764 |
|
|
+ i = lvl;
|
1765 |
|
|
+ if ((true)||(lvl == 0))
|
1766 |
|
|
+ fprintf(stderr, "%s", pfx);
|
1767 |
|
|
+ else
|
1768 |
|
|
+ i += strlen(pfx);
|
1769 |
|
|
+ while(i-->0)
|
1770 |
|
|
+ fprintf(stderr, " ");
|
1771 |
|
|
+ fprintf(stderr, "%s\n", str);
|
1772 |
|
|
+}
|
1773 |
|
|
+
|
1774 |
|
|
+static void
|
1775 |
|
|
+zip_debug_print_m(const char *pfx, int lvl, const char *str, enum machine_mode m) {
|
1776 |
|
|
+ int i;
|
1777 |
|
|
+
|
1778 |
|
|
+ i = lvl;
|
1779 |
|
|
+ if ((true)||(lvl == 0))
|
1780 |
|
|
+ fprintf(stderr, "%s", pfx);
|
1781 |
|
|
+ else
|
1782 |
|
|
+ i = lvl+strlen(pfx);
|
1783 |
|
|
+ while(i-->0)
|
1784 |
|
|
+ fprintf(stderr, " ");
|
1785 |
|
|
+ switch(m) {
|
1786 |
|
|
+ case VOIDmode:
|
1787 |
|
|
+ fprintf(stderr, "%s:V\n", str);
|
1788 |
|
|
+ break;
|
1789 |
|
|
+ case BLKmode:
|
1790 |
|
|
+ fprintf(stderr, "%s:BLK\n", str);
|
1791 |
|
|
+ break;
|
1792 |
|
|
+ case BImode:
|
1793 |
|
|
+ fprintf(stderr, "%s:BI\n", str);
|
1794 |
|
|
+ break;
|
1795 |
|
|
+#ifdef HAVE_QImode
|
1796 |
|
|
+ case QImode:
|
1797 |
|
|
+ fprintf(stderr, "%s:QI\n", str);
|
1798 |
|
|
+ break;
|
1799 |
|
|
+#endif
|
1800 |
|
|
+#ifdef HAVE_HImode
|
1801 |
|
|
+ case HImode:
|
1802 |
|
|
+ fprintf(stderr, "%s:HI\n", str);
|
1803 |
|
|
+ break;
|
1804 |
|
|
+#endif
|
1805 |
|
|
+ case SImode:
|
1806 |
|
|
+ fprintf(stderr, "%s:SI\n", str);
|
1807 |
|
|
+ break;
|
1808 |
122 |
dgisselq |
+ case CCmode:
|
1809 |
|
|
+ fprintf(stderr, "%s:CC\n", str);
|
1810 |
|
|
+ break;
|
1811 |
102 |
dgisselq |
+ case DImode:
|
1812 |
|
|
+ fprintf(stderr, "%s:DI\n", str);
|
1813 |
|
|
+ break;
|
1814 |
|
|
+ default:
|
1815 |
|
|
+ fprintf(stderr, "%s:?\n", str);
|
1816 |
|
|
+ }
|
1817 |
|
|
+}
|
1818 |
|
|
+
|
1819 |
|
|
+static void
|
1820 |
|
|
+zip_debug_rtx_1(const char *pfx, const_rtx x, int lvl) {
|
1821 |
|
|
+ if (x == NULL_RTX) {
|
1822 |
|
|
+ zip_debug_print(pfx, lvl, "(NULL-RTX)");
|
1823 |
|
|
+ return;
|
1824 |
|
|
+ } else if (GET_CODE(x) > NUM_RTX_CODE) {
|
1825 |
|
|
+ char buf[64];
|
1826 |
|
|
+ sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
|
1827 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
1828 |
117 |
dgisselq |
+ gcc_assert(0 && "Bad RTX Code");
|
1829 |
102 |
dgisselq |
+ return;
|
1830 |
|
|
+ } switch(GET_CODE(x)) { // rtl.def
|
1831 |
122 |
dgisselq |
+ case PARALLEL:
|
1832 |
|
|
+ zip_debug_print(pfx, lvl, "(PARALLEL");
|
1833 |
|
|
+ for(int j=0; j<XVECLEN(x,0);j++)
|
1834 |
|
|
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
|
1835 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1836 |
|
|
+ debug_rtx(x);
|
1837 |
|
|
+ break;
|
1838 |
102 |
dgisselq |
+ case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
|
1839 |
122 |
dgisselq |
+ case SEQUENCE:
|
1840 |
|
|
+ zip_debug_print(pfx, lvl, "(SEQUENCE");
|
1841 |
|
|
+ for(int j=0; j<XVECLEN(x,0);j++)
|
1842 |
|
|
+ zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
|
1843 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1844 |
|
|
+ debug_rtx(x);
|
1845 |
|
|
+ break;
|
1846 |
102 |
dgisselq |
+ case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
|
1847 |
|
|
+ case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
|
1848 |
|
|
+ case INSN:
|
1849 |
|
|
+ zip_debug_print(pfx, lvl, "(INSN");
|
1850 |
|
|
+ /*
|
1851 |
|
|
+ { const rtx_insn *tmp_rtx;
|
1852 |
|
|
+ for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
|
1853 |
|
|
+ zip_debug_rtx_1(tmp_rtx, lvl+1);
|
1854 |
|
|
+ }}
|
1855 |
|
|
+ */
|
1856 |
|
|
+ zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
|
1857 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1858 |
117 |
dgisselq |
+ debug_rtx(x);
|
1859 |
102 |
dgisselq |
+ break;
|
1860 |
|
|
+ case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
|
1861 |
111 |
dgisselq |
+ zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
|
1862 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1863 |
|
|
+ /*
|
1864 |
102 |
dgisselq |
+ if (JUMP_LABEL(x)) {
|
1865 |
111 |
dgisselq |
+ if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
|
1866 |
|
|
+ char buf[64];
|
1867 |
|
|
+ sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
|
1868 |
|
|
+ zip_debug_print(pfx, lvl+1, buf);
|
1869 |
|
|
+ } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
|
1870 |
|
|
+ char buf[64];
|
1871 |
|
|
+ sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
|
1872 |
|
|
+ zip_debug_print(pfx, lvl+1, buf);
|
1873 |
|
|
+ } else
|
1874 |
|
|
+ zip_debug_print(pfx, lvl+1, "(w/Label))");
|
1875 |
102 |
dgisselq |
+ } else
|
1876 |
111 |
dgisselq |
+ zip_debug_print(pfx, lvl+1, "(NO label))");
|
1877 |
|
|
+ debug_rtx(x);
|
1878 |
|
|
+ */
|
1879 |
102 |
dgisselq |
+ break;
|
1880 |
|
|
+ case CALL:
|
1881 |
|
|
+ zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
|
1882 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
|
1883 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
|
1884 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1885 |
|
|
+ break;
|
1886 |
|
|
+ case CALL_INSN: zip_debug_print(pfx, lvl, "(CALL-INSN");
|
1887 |
|
|
+ debug_rtx(x);
|
1888 |
|
|
+ break;
|
1889 |
|
|
+ case BARRIER: zip_debug_print(pfx, lvl, "(BARRIER)"); break;
|
1890 |
|
|
+ case RETURN: zip_debug_print(pfx, lvl, "(RETURN)"); break;
|
1891 |
|
|
+ case NOTE:
|
1892 |
|
|
+ { char buf[128];
|
1893 |
|
|
+ sprintf(buf, "(NOTE %s)", GET_REG_NOTE_NAME(GET_MODE(x)));
|
1894 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
1895 |
|
|
+ }break;
|
1896 |
|
|
+ case COND_EXEC: zip_debug_print(pfx, lvl, "(COND_EXEC)");
|
1897 |
|
|
+ debug_rtx(x);
|
1898 |
|
|
+ break;
|
1899 |
|
|
+ case ASM_INPUT: zip_debug_print(pfx, lvl, "(ASM INPUT)"); break;
|
1900 |
|
|
+ case ASM_OPERANDS: zip_debug_print(pfx, lvl, "(ASM OPERANDS)"); break;
|
1901 |
|
|
+ case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
|
1902 |
|
|
+ case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
|
1903 |
|
|
+ case CODE_LABEL:
|
1904 |
|
|
+ {
|
1905 |
|
|
+ char buf[64];
|
1906 |
111 |
dgisselq |
+ sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
|
1907 |
102 |
dgisselq |
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
|
1908 |
|
|
+ } break;
|
1909 |
|
|
+ case SET:
|
1910 |
|
|
+ zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
|
1911 |
117 |
dgisselq |
+ zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
|
1912 |
|
|
+ zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
|
1913 |
102 |
dgisselq |
+ zip_debug_print(pfx, lvl, ")");
|
1914 |
117 |
dgisselq |
+ debug_rtx(x);
|
1915 |
102 |
dgisselq |
+ break;
|
1916 |
122 |
dgisselq |
+ case REG: {
|
1917 |
127 |
dgisselq |
+ char buf[25], mstr[4];
|
1918 |
|
|
+ mstr[0] = '\0';
|
1919 |
|
|
+ if (GET_MODE(x) == SImode)
|
1920 |
|
|
+ strcpy(mstr, ":SI");
|
1921 |
|
|
+ else if (GET_MODE(x) == DImode)
|
1922 |
|
|
+ strcpy(mstr, ":DI");
|
1923 |
|
|
+ else if (GET_MODE(x) == VOIDmode)
|
1924 |
|
|
+ strcpy(mstr, ":V");
|
1925 |
102 |
dgisselq |
+ if (REGNO(x) == zip_PC)
|
1926 |
127 |
dgisselq |
+ sprintf(buf, "(PC%s)", mstr);
|
1927 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_CC)
|
1928 |
127 |
dgisselq |
+ sprintf(buf, "(CC%s)", mstr);
|
1929 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_SP)
|
1930 |
127 |
dgisselq |
+ sprintf(buf, "(SP%s)", mstr);
|
1931 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_FP)
|
1932 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s FP)", mstr);
|
1933 |
102 |
dgisselq |
+ else if (REGNO(x) == zip_GOT)
|
1934 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s GBL)", mstr);
|
1935 |
102 |
dgisselq |
+ else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
|
1936 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s RTN-VL)", mstr);
|
1937 |
102 |
dgisselq |
+ else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
|
1938 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s RTN-AD)", mstr);
|
1939 |
122 |
dgisselq |
+ else
|
1940 |
127 |
dgisselq |
+ sprintf(buf, "(REG%s %d)", mstr, REGNO(x));
|
1941 |
|
|
+ if (mstr[0])
|
1942 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
1943 |
|
|
+ else
|
1944 |
|
|
+ zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
|
1945 |
102 |
dgisselq |
+ } break;
|
1946 |
|
|
+ case IF_THEN_ELSE: // 51
|
1947 |
|
|
+ zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
|
1948 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
1949 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
1950 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,2),lvl+1);
|
1951 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1952 |
|
|
+ break;
|
1953 |
|
|
+ case PC:
|
1954 |
|
|
+ zip_debug_print(pfx, lvl, "(PC)");
|
1955 |
|
|
+ break;
|
1956 |
|
|
+ case CC0:
|
1957 |
|
|
+ zip_debug_print(pfx, lvl, "(CC0)");
|
1958 |
|
|
+ break;
|
1959 |
|
|
+ case COMPARE:
|
1960 |
127 |
dgisselq |
+ zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x));
|
1961 |
102 |
dgisselq |
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
1962 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
1963 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1964 |
|
|
+ break;
|
1965 |
111 |
dgisselq |
+ case CONST:
|
1966 |
|
|
+ zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
|
1967 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
1968 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1969 |
|
|
+ break;
|
1970 |
102 |
dgisselq |
+ case CONST_INT:
|
1971 |
|
|
+ { char buf[25];
|
1972 |
|
|
+ if (GET_MODE(x)==SImode)
|
1973 |
135 |
dgisselq |
+ sprintf(buf, "(CONST_INT:SI %ld)", (long)INTVAL(x));
|
1974 |
102 |
dgisselq |
+ else if (GET_MODE(x)==VOIDmode)
|
1975 |
135 |
dgisselq |
+ sprintf(buf, "(CONST_INT:V %ld)", (long)INTVAL(x));
|
1976 |
102 |
dgisselq |
+ else
|
1977 |
135 |
dgisselq |
+ sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
|
1978 |
102 |
dgisselq |
+ zip_debug_print(pfx, lvl, buf);
|
1979 |
|
|
+ } break;
|
1980 |
|
|
+ case LABEL_REF:
|
1981 |
122 |
dgisselq |
+ { char buf[256];
|
1982 |
111 |
dgisselq |
+ sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
|
1983 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
1984 |
|
|
+ }
|
1985 |
102 |
dgisselq |
+ break;
|
1986 |
|
|
+ case SYMBOL_REF:
|
1987 |
|
|
+ {
|
1988 |
|
|
+ char buf[64];
|
1989 |
|
|
+ sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
|
1990 |
|
|
+ // fprintf(file, "%s", XSTR(x,0));
|
1991 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
1992 |
|
|
+ }
|
1993 |
|
|
+ break;
|
1994 |
|
|
+ case MEM:
|
1995 |
|
|
+ zip_debug_print_m(pfx, lvl, "(MEM", GET_MODE(x));
|
1996 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
1997 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
1998 |
|
|
+ break;
|
1999 |
|
|
+ /*
|
2000 |
|
|
+ case VALUE:
|
2001 |
|
|
+ {
|
2002 |
|
|
+ char buf[64];
|
2003 |
|
|
+ sprintf(buf, "(VALUE: %d)", INTVAL(XEXP,0));
|
2004 |
|
|
+ zip_debug_print_m(pfx, lvl, "buf", GET_MODE(x));
|
2005 |
|
|
+ }
|
2006 |
|
|
+ break;
|
2007 |
|
|
+ */
|
2008 |
|
|
+ case PLUS:
|
2009 |
|
|
+ zip_debug_print_m(pfx, lvl, "(PLUS", GET_MODE(x));
|
2010 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2011 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2012 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2013 |
|
|
+ break;
|
2014 |
|
|
+ case MINUS:
|
2015 |
|
|
+ zip_debug_print_m(pfx, lvl, "(MINUS", GET_MODE(x));
|
2016 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2017 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2018 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2019 |
|
|
+ break;
|
2020 |
|
|
+ case AND:
|
2021 |
|
|
+ zip_debug_print_m(pfx, lvl, "(AND", GET_MODE(x));
|
2022 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2023 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2024 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2025 |
|
|
+ break;
|
2026 |
|
|
+ case IOR:
|
2027 |
|
|
+ zip_debug_print_m(pfx, lvl, "(OR", GET_MODE(x));
|
2028 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2029 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2030 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2031 |
|
|
+ break;
|
2032 |
|
|
+ case XOR:
|
2033 |
|
|
+ zip_debug_print_m(pfx, lvl, "(XOR", GET_MODE(x));
|
2034 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2035 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2036 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2037 |
|
|
+ break;
|
2038 |
|
|
+ case MULT:
|
2039 |
|
|
+ zip_debug_print_m(pfx, lvl, "(MULT", GET_MODE(x));
|
2040 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2041 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2042 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2043 |
|
|
+ break;
|
2044 |
|
|
+ case EQ: //
|
2045 |
|
|
+ zip_debug_print_m(pfx, lvl, "(EQ", GET_MODE(x));
|
2046 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2047 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2048 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2049 |
|
|
+ break;
|
2050 |
|
|
+ case NE: //
|
2051 |
|
|
+ zip_debug_print_m(pfx, lvl, "(NE", GET_MODE(x));
|
2052 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2053 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2054 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2055 |
|
|
+ break;
|
2056 |
|
|
+ case GE: //
|
2057 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GE", GET_MODE(x));
|
2058 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2059 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2060 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2061 |
|
|
+ break;
|
2062 |
|
|
+ case GT: //
|
2063 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GT", GET_MODE(x));
|
2064 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2065 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2066 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2067 |
|
|
+ break;
|
2068 |
|
|
+ case LE: //
|
2069 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LE", GET_MODE(x));
|
2070 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2071 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2072 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2073 |
|
|
+ break;
|
2074 |
|
|
+ case LT: //
|
2075 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LT", GET_MODE(x));
|
2076 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2077 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2078 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2079 |
|
|
+ break;
|
2080 |
|
|
+ case GEU: //
|
2081 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GEU", GET_MODE(x));
|
2082 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2083 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2084 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2085 |
|
|
+ break;
|
2086 |
|
|
+ case GTU: //
|
2087 |
|
|
+ zip_debug_print_m(pfx, lvl, "(GTU", GET_MODE(x));
|
2088 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2089 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2090 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2091 |
|
|
+ break;
|
2092 |
|
|
+ case LEU: //
|
2093 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LEU", GET_MODE(x));
|
2094 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2095 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2096 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2097 |
|
|
+ break;
|
2098 |
|
|
+ case LTU: //
|
2099 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LTU", GET_MODE(x));
|
2100 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2101 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2102 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2103 |
|
|
+ break;
|
2104 |
|
|
+ case SCRATCH: //
|
2105 |
|
|
+ zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
|
2106 |
|
|
+ break;
|
2107 |
|
|
+ case SUBREG:
|
2108 |
|
|
+ { char buf[25];
|
2109 |
111 |
dgisselq |
+ if (REG_P(XEXP(x,0))) {
|
2110 |
|
|
+ sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
|
2111 |
|
|
+ SUBREG_BYTE(x));
|
2112 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2113 |
|
|
+ } else if (MEM_P(XEXP(x,0))) {
|
2114 |
|
|
+ sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
|
2115 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2116 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2117 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2118 |
|
|
+ } else {
|
2119 |
|
|
+ sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
|
2120 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2121 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2122 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2123 |
|
|
+ }}
|
2124 |
|
|
+ break;
|
2125 |
127 |
dgisselq |
+ case ASHIFT:
|
2126 |
|
|
+ zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x));
|
2127 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2128 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2129 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2130 |
|
|
+ break;
|
2131 |
|
|
+ case ASHIFTRT:
|
2132 |
|
|
+ zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x));
|
2133 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2134 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2135 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2136 |
|
|
+ break;
|
2137 |
|
|
+ case LSHIFTRT:
|
2138 |
|
|
+ zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
|
2139 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
|
2140 |
|
|
+ zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
|
2141 |
|
|
+ zip_debug_print(pfx, lvl, ")");
|
2142 |
|
|
+ break;
|
2143 |
102 |
dgisselq |
+ default:
|
2144 |
111 |
dgisselq |
+ { char buf[128];
|
2145 |
102 |
dgisselq |
+ sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
|
2146 |
|
|
+ zip_debug_print(pfx, lvl, buf);
|
2147 |
|
|
+ debug_rtx(x);
|
2148 |
|
|
+ } break;
|
2149 |
|
|
+ }
|
2150 |
|
|
+}
|
2151 |
|
|
+
|
2152 |
|
|
+void
|
2153 |
|
|
+zip_debug_rtx_pfx(const char *pfx, const_rtx x) {
|
2154 |
|
|
+ zip_debug_rtx_1(pfx, x, 0);
|
2155 |
|
|
+}
|
2156 |
|
|
+
|
2157 |
|
|
+void
|
2158 |
|
|
+zip_debug_rtx(const_rtx x) {
|
2159 |
|
|
+ zip_debug_rtx_pfx("", x);
|
2160 |
|
|
+}
|
2161 |
|
|
+
|
2162 |
|
|
+void
|
2163 |
142 |
dgisselq |
+zip_debug_ccode(int ccode) {
|
2164 |
|
|
+ switch(ccode) {
|
2165 |
|
|
+ case EQ: fprintf(stderr, "EQ"); break;
|
2166 |
|
|
+ case NE: fprintf(stderr, "NE"); break;
|
2167 |
|
|
+ case GT: fprintf(stderr, "GT"); break;
|
2168 |
|
|
+ case GE: fprintf(stderr, "GE"); break;
|
2169 |
|
|
+ case LT: fprintf(stderr, "LT"); break;
|
2170 |
|
|
+ case LE: fprintf(stderr, "LE"); break;
|
2171 |
|
|
+ case GTU: fprintf(stderr, "GTU"); break;
|
2172 |
|
|
+ case GEU: fprintf(stderr, "GEU"); break;
|
2173 |
|
|
+ case LTU: fprintf(stderr, "LTU"); break;
|
2174 |
|
|
+ case LEU: fprintf(stderr, "LEU"); break;
|
2175 |
|
|
+ default:
|
2176 |
|
|
+ fprintf(stderr, "%d", ccode); break;
|
2177 |
|
|
+ }
|
2178 |
|
|
+}
|
2179 |
|
|
+
|
2180 |
|
|
+void
|
2181 |
102 |
dgisselq |
+zip_debug_insn(rtx_insn *insn ATTRIBUTE_UNUSED) {
|
2182 |
|
|
+}
|
2183 |
|
|
+
|
2184 |
|
|
+void
|
2185 |
|
|
+zip_debug_bb(basic_block bb) {
|
2186 |
|
|
+ rtx_insn *insn;
|
2187 |
|
|
+
|
2188 |
|
|
+ fprintf(stderr, "************ BASIC-BLOCK ***************\n");
|
2189 |
|
|
+ FOR_BB_INSNS(bb, insn)
|
2190 |
|
|
+ {
|
2191 |
|
|
+ zip_debug_rtx(insn);
|
2192 |
|
|
+ }
|
2193 |
|
|
+}
|
2194 |
|
|
+
|
2195 |
|
|
+
|
2196 |
|
|
+static bool
|
2197 |
122 |
dgisselq |
+zip_legitimate_opb(rtx x, bool strict)
|
2198 |
102 |
dgisselq |
+{
|
2199 |
103 |
dgisselq |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2200 |
102 |
dgisselq |
+
|
2201 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
|
2202 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("Test: ", x);
|
2203 |
|
|
+
|
2204 |
|
|
+ if (NULL_RTX == x)
|
2205 |
|
|
+ return false;
|
2206 |
122 |
dgisselq |
+ else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
2207 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
|
2208 |
102 |
dgisselq |
+ return false;
|
2209 |
122 |
dgisselq |
+ } else if ((strict)&&(REG_P(x))) {
|
2210 |
|
|
+ if (REGNO(x)<zip_CC) {
|
2211 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
|
2212 |
|
|
+ return true;
|
2213 |
|
|
+ } else return false;
|
2214 |
|
|
+ } else if (register_operand(x, GET_MODE(x))) {
|
2215 |
|
|
+ // This also handles subregs
|
2216 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
|
2217 |
|
|
+ return true;
|
2218 |
111 |
dgisselq |
+ } else if ((CONST_INT_P(x))
|
2219 |
|
|
+ &&(INTVAL(x) >= zip_min_opb_imm)
|
2220 |
|
|
+ &&(INTVAL(x) <= zip_max_opb_imm)) {
|
2221 |
136 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", (long)zip_min_opb_imm, (long)INTVAL(x), (long)zip_max_opb_imm);
|
2222 |
111 |
dgisselq |
+ return true;
|
2223 |
122 |
dgisselq |
+ // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
|
2224 |
|
|
+ // return true;
|
2225 |
102 |
dgisselq |
+ } else if (GET_CODE(x) == PLUS) {
|
2226 |
|
|
+ // Is it a valid register?
|
2227 |
122 |
dgisselq |
+ if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) {
|
2228 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
|
2229 |
102 |
dgisselq |
+ (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
|
2230 |
|
|
+ return false;
|
2231 |
122 |
dgisselq |
+ } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
|
2232 |
102 |
dgisselq |
+ return false;
|
2233 |
|
|
+ } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
|
2234 |
|
|
+ &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
|
2235 |
|
|
+ &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
|
2236 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
|
2237 |
103 |
dgisselq |
+ // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
|
2238 |
|
|
+ // gcc_unreachable();
|
2239 |
102 |
dgisselq |
+ return true;
|
2240 |
|
|
+ } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
|
2241 |
122 |
dgisselq |
+ ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL)
|
2242 |
102 |
dgisselq |
+ ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
|
2243 |
|
|
+ // While we can technically support this, the problem
|
2244 |
|
|
+ // is that the symbol address could be anywhere, and we
|
2245 |
|
|
+ // have no way of recovering if it's outside of our
|
2246 |
|
|
+ // 14 allowable bits.
|
2247 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
|
2248 |
102 |
dgisselq |
+ return false;
|
2249 |
|
|
+ }
|
2250 |
|
|
+ }
|
2251 |
|
|
+
|
2252 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
|
2253 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx(x);
|
2254 |
|
|
+ return false;
|
2255 |
|
|
+}
|
2256 |
|
|
+
|
2257 |
|
|
+static bool
|
2258 |
|
|
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
|
2259 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2260 |
|
|
+
|
2261 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
|
2262 |
|
|
+ if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
|
2263 |
|
|
+
|
2264 |
122 |
dgisselq |
+ if (!zip_legitimate_opb(x, strict))
|
2265 |
102 |
dgisselq |
+ return false;
|
2266 |
122 |
dgisselq |
+ else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) {
|
2267 |
|
|
+ if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset)
|
2268 |
|
|
+ ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) {
|
2269 |
135 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %ld\n", (long)INTVAL(XEXP(x,1)));
|
2270 |
102 |
dgisselq |
+ return false;
|
2271 |
|
|
+ }
|
2272 |
|
|
+ }
|
2273 |
|
|
+
|
2274 |
122 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n");
|
2275 |
102 |
dgisselq |
+ if (dbg) zip_debug_rtx(x);
|
2276 |
122 |
dgisselq |
+ return true;
|
2277 |
102 |
dgisselq |
+}
|
2278 |
|
|
+
|
2279 |
|
|
+int
|
2280 |
|
|
+zip_pd_mov_operand(rtx op)
|
2281 |
|
|
+{
|
2282 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2283 |
|
|
+
|
2284 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
|
2285 |
|
|
+ return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
|
2286 |
|
|
+}
|
2287 |
|
|
+
|
2288 |
|
|
+int
|
2289 |
111 |
dgisselq |
+zip_pd_mvimm_operand(rtx op)
|
2290 |
|
|
+{
|
2291 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2292 |
|
|
+
|
2293 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
|
2294 |
|
|
+ if (!CONST_INT_P(op))
|
2295 |
|
|
+ return false;
|
2296 |
|
|
+ if (INTVAL(op) > zip_max_mov_offset)
|
2297 |
|
|
+ return false;
|
2298 |
|
|
+ if (INTVAL(op) < zip_min_mov_offset)
|
2299 |
|
|
+ return false;
|
2300 |
|
|
+ return true;
|
2301 |
|
|
+}
|
2302 |
|
|
+
|
2303 |
|
|
+int
|
2304 |
|
|
+zip_pd_imm_operand(rtx op)
|
2305 |
|
|
+{
|
2306 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2307 |
|
|
+
|
2308 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
|
2309 |
|
|
+ if (!CONST_INT_P(op))
|
2310 |
|
|
+ return false;
|
2311 |
|
|
+ if (INTVAL(op) > zip_max_anchor_offset)
|
2312 |
|
|
+ return false;
|
2313 |
|
|
+ if (INTVAL(op) < zip_min_anchor_offset)
|
2314 |
|
|
+ return false;
|
2315 |
|
|
+ return true;
|
2316 |
|
|
+}
|
2317 |
|
|
+
|
2318 |
|
|
+int
|
2319 |
102 |
dgisselq |
+zip_address_operand(rtx op)
|
2320 |
|
|
+{
|
2321 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2322 |
|
|
+
|
2323 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
|
2324 |
111 |
dgisselq |
+ if ((REG_P(op))&&(REGNO(op)==zip_CC))
|
2325 |
|
|
+ return false;
|
2326 |
|
|
+ else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
|
2327 |
|
|
+ &&(REGNO(XEXP(op,0))==zip_CC))
|
2328 |
|
|
+ return false;
|
2329 |
|
|
+ else
|
2330 |
|
|
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
|
2331 |
102 |
dgisselq |
+}
|
2332 |
|
|
+
|
2333 |
|
|
+int
|
2334 |
111 |
dgisselq |
+zip_pd_opb_operand(rtx op)
|
2335 |
102 |
dgisselq |
+{
|
2336 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2337 |
|
|
+
|
2338 |
111 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
|
2339 |
122 |
dgisselq |
+ return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
|
2340 |
102 |
dgisselq |
+}
|
2341 |
|
|
+
|
2342 |
|
|
+int
|
2343 |
|
|
+zip_ct_address_operand(rtx op)
|
2344 |
|
|
+{
|
2345 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2346 |
|
|
+
|
2347 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
|
2348 |
111 |
dgisselq |
+ return zip_legitimate_opb(op, !can_create_pseudo_p());
|
2349 |
102 |
dgisselq |
+}
|
2350 |
|
|
+
|
2351 |
|
|
+int
|
2352 |
|
|
+zip_const_address_operand(rtx x) {
|
2353 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2354 |
|
|
+
|
2355 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
|
2356 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
2357 |
127 |
dgisselq |
+ if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
|
2358 |
|
|
+ fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
|
2359 |
102 |
dgisselq |
+ return false;
|
2360 |
127 |
dgisselq |
+ }
|
2361 |
102 |
dgisselq |
+ if ((GET_CODE(x) == LABEL_REF)
|
2362 |
|
|
+ ||(GET_CODE(x) == CODE_LABEL)
|
2363 |
|
|
+ ||(GET_CODE(x) == SYMBOL_REF)) {
|
2364 |
127 |
dgisselq |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n");
|
2365 |
102 |
dgisselq |
+ return true;
|
2366 |
|
|
+ } else if (CONST_INT_P(x)) {
|
2367 |
127 |
dgisselq |
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n");
|
2368 |
102 |
dgisselq |
+ return true;
|
2369 |
|
|
+ } else if (GET_CODE(x) == PLUS) {
|
2370 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
|
2371 |
|
|
+ return ((zip_const_address_operand(XEXP(x,0)))
|
2372 |
|
|
+ &&(CONST_INT_P(XEXP(x,1))));
|
2373 |
|
|
+ } else if (GET_CODE(x) == MINUS) {
|
2374 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(MINUS)\n");
|
2375 |
|
|
+ return ((zip_const_address_operand(XEXP(x,0)))
|
2376 |
|
|
+ &&(zip_const_address_operand(XEXP(x,1))));
|
2377 |
|
|
+ }
|
2378 |
|
|
+
|
2379 |
|
|
+ if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> No\n");
|
2380 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
2381 |
|
|
+ return false;
|
2382 |
|
|
+}
|
2383 |
|
|
+
|
2384 |
|
|
+int
|
2385 |
|
|
+zip_ct_const_address_operand(rtx x) {
|
2386 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2387 |
|
|
+
|
2388 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
|
2389 |
|
|
+ return zip_const_address_operand(x);
|
2390 |
|
|
+}
|
2391 |
|
|
+
|
2392 |
|
|
+int
|
2393 |
|
|
+zip_pd_const_address_operand(rtx x) {
|
2394 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2395 |
|
|
+
|
2396 |
|
|
+ if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
|
2397 |
|
|
+ return zip_const_address_operand(x);
|
2398 |
|
|
+}
|
2399 |
|
|
+
|
2400 |
|
|
+
|
2401 |
|
|
+static bool
|
2402 |
|
|
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
|
2403 |
|
|
+{
|
2404 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2405 |
|
|
+
|
2406 |
|
|
+ if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
|
2407 |
|
|
+ if (dbg) zip_debug_rtx(x);
|
2408 |
|
|
+
|
2409 |
|
|
+ // Only insist the register be a valid register if strict is true
|
2410 |
111 |
dgisselq |
+ if (zip_legitimate_opb(x, strict))
|
2411 |
102 |
dgisselq |
+ return true;
|
2412 |
111 |
dgisselq |
+ // else if (zip_const_address_operand(x))
|
2413 |
|
|
+ // return true;
|
2414 |
102 |
dgisselq |
+
|
2415 |
|
|
+ return false;
|
2416 |
|
|
+}
|
2417 |
|
|
+
|
2418 |
111 |
dgisselq |
+static rtx
|
2419 |
|
|
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
|
2420 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2421 |
|
|
+
|
2422 |
|
|
+ if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
|
2423 |
|
|
+ if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
2424 |
|
|
+ return x;
|
2425 |
|
|
+
|
2426 |
|
|
+ if (GET_CODE(x)==PLUS) {
|
2427 |
|
|
+ if (!REG_P(XEXP(x,0)))
|
2428 |
|
|
+ XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
|
2429 |
|
|
+ if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
|
2430 |
|
|
+ &&(!CONST_INT_P(XEXP(x,1))))
|
2431 |
|
|
+ x = force_reg(GET_MODE(x),x);
|
2432 |
|
|
+ } else if (MEM_P(x))
|
2433 |
|
|
+ x = force_reg(GET_MODE(x),x);
|
2434 |
|
|
+
|
2435 |
|
|
+ if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
|
2436 |
|
|
+ return x;
|
2437 |
|
|
+}
|
2438 |
|
|
+
|
2439 |
102 |
dgisselq |
+void
|
2440 |
|
|
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
|
2441 |
|
|
+{
|
2442 |
|
|
+ assemble_name(stream, name);
|
2443 |
|
|
+ fprintf(stream, "\t.equ ");
|
2444 |
|
|
+ assemble_name(stream, value);
|
2445 |
|
|
+ fputc('\n', stream);
|
2446 |
|
|
+}
|
2447 |
|
|
+
|
2448 |
111 |
dgisselq |
+#define USE_SUBREG
|
2449 |
|
|
+#ifdef USE_SUBREG
|
2450 |
|
|
+#define SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
|
2451 |
|
|
+#define SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
|
2452 |
|
|
+#else
|
2453 |
|
|
+#define SREG_P(RTX) false
|
2454 |
|
|
+#define SMEM_P(RTX) false
|
2455 |
|
|
+#endif
|
2456 |
102 |
dgisselq |
+
|
2457 |
|
|
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
|
2458 |
103 |
dgisselq |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2459 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
|
2460 |
|
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
2461 |
|
|
+ if (dbg) zip_debug_rtx_pfx("REG", dst);
|
2462 |
|
|
+ switch(GET_CODE(condition)) {
|
2463 |
|
|
+ case EQ: return "LDI\t0,%0\n\tLDILO.Z\t1,%0";
|
2464 |
|
|
+ case NE: return "LDI\t0,%0\n\tLDILO.NZ\t1,%0";
|
2465 |
|
|
+ case LT: return "LDI\t0,%0\n\tLDILO.LT\t1,%0";
|
2466 |
|
|
+ case GT: return "LDI\t0,%0\n\tLDILO.GT\t1,%0";
|
2467 |
|
|
+ case LE: return "LDI\t1,%0\n\tLDILO.GT\t0,%0";
|
2468 |
|
|
+ case GE: return "LDI\t0,%0\n\tLDILO.GE\t1,%0";
|
2469 |
|
|
+ case LTU: return "LDI\t0,%0\n\tLDILO.C\t1,%0";
|
2470 |
|
|
+ case GTU: return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0";
|
2471 |
|
|
+ case LEU: return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0";
|
2472 |
|
|
+ case GEU: return "LDI\t1,%0\n\tLDILO.C\t0,%0";
|
2473 |
|
|
+ default:
|
2474 |
|
|
+ zip_debug_rtx(condition);
|
2475 |
|
|
+ internal_error("CSTORE Unsupported condition");
|
2476 |
|
|
+ return NULL;
|
2477 |
|
|
+ }
|
2478 |
|
|
+}
|
2479 |
|
|
+
|
2480 |
127 |
dgisselq |
+/*
|
2481 |
102 |
dgisselq |
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
|
2482 |
|
|
+ static char result[64] = "";
|
2483 |
|
|
+ switch(condition) {
|
2484 |
|
|
+ //
|
2485 |
|
|
+ // Result already exists in the iffalse register
|
2486 |
|
|
+ // Can't change it. Therefore, on the
|
2487 |
|
|
+ // condition ... move true register to the
|
2488 |
|
|
+ // destination
|
2489 |
|
|
+ //
|
2490 |
|
|
+ case EQ: sprintf(result, "%s.Z\t%%%d,%%0", op, opno); break;
|
2491 |
|
|
+ case NE: sprintf(result, "%s.NZ\t%%%d,%%0", op, opno); break;
|
2492 |
|
|
+ case LT: sprintf(result, "%s.LT\t%%%d,%%0", op, opno); break;
|
2493 |
|
|
+ case GT: sprintf(result, "%s.GT\t%%%d,%%0", op, opno); break;
|
2494 |
|
|
+ // .LE doesn't exist on Zip CPU--turn this into two instructions
|
2495 |
|
|
+ case LE: sprintf(result, "%s.LT\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
|
2496 |
|
|
+ case GE: sprintf(result, "%s.GE\t%%%d,%%0", op, opno); break;
|
2497 |
|
|
+ case LTU: sprintf(result, "%s.C\t%%%d,%%0", op, opno); break;
|
2498 |
|
|
+ //
|
2499 |
|
|
+ // .GTU doesn't exist on the Zip CPU either. We also note that
|
2500 |
|
|
+ // .C will never be set on an equal condition. Therefore, we
|
2501 |
|
|
+ // turn this into a XOR.NZ 2,CC, which will set the .C condition
|
2502 |
|
|
+ // as long as .Z wasn't true. We then undo this when we're
|
2503 |
|
|
+ // done. This is possible since none of these instructions
|
2504 |
|
|
+ // (LDI/MOV/Lod conditional, nor Xor conditional) will ever set
|
2505 |
|
|
+ // the condition codes.
|
2506 |
|
|
+ //
|
2507 |
|
|
+ // This is obviously not very optimal. Avoid this by all means
|
2508 |
|
|
+ // if you can
|
2509 |
|
|
+ case GTU: sprintf(result, "XOR.NZ\t2,CC\n%s.C\t%%%d,%%0\n\tXOR.NZ\t2,CC", op, opno); break;
|
2510 |
|
|
+ // .LEU doesn't exist on Zip CPU either--turn this into another
|
2511 |
|
|
+ // two instructions
|
2512 |
|
|
+ case LEU: sprintf(result, "%s.C\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
|
2513 |
|
|
+ //
|
2514 |
|
|
+ // .GEU doesn't exist on Zip CPU. Implementing it her is
|
2515 |
|
|
+ // painful. We can change the condition codes to make it so,
|
2516 |
|
|
+ // but the instruction requires the condition codes not be
|
2517 |
|
|
+ // changed. Hence, we must change them back if we do so.
|
2518 |
|
|
+ //
|
2519 |
|
|
+ // .C will be set on less than but not equal. Hence !.C will
|
2520 |
|
|
+ // be true on greater than or equal.
|
2521 |
|
|
+ case GEU: sprintf(result, "XOR\t2,CC\n%s.C\t%%%d,%%0\n\tXOR\t2,CC", op, opno); break;
|
2522 |
|
|
+ default:
|
2523 |
|
|
+ internal_error("MOVSICC(BINARY) Unsupported condition");
|
2524 |
|
|
+ return NULL;
|
2525 |
|
|
+ } return result;
|
2526 |
|
|
+}
|
2527 |
127 |
dgisselq |
+*/
|
2528 |
102 |
dgisselq |
+
|
2529 |
127 |
dgisselq |
+bool
|
2530 |
|
|
+zip_supported_condition(int c) {
|
2531 |
|
|
+ switch(c) {
|
2532 |
|
|
+ case NE: case LT: case EQ: case GT: case GE: case LTU:
|
2533 |
|
|
+ return true;
|
2534 |
|
|
+ break;
|
2535 |
|
|
+ default:
|
2536 |
|
|
+ break;
|
2537 |
|
|
+ } return false;
|
2538 |
102 |
dgisselq |
+}
|
2539 |
|
|
+
|
2540 |
127 |
dgisselq |
+bool
|
2541 |
|
|
+zip_signed_comparison(int c) {
|
2542 |
|
|
+ switch(c) {
|
2543 |
|
|
+ case NE: case LT: case EQ: case GT: case GE:
|
2544 |
|
|
+ return true;
|
2545 |
|
|
+ default:
|
2546 |
|
|
+ break;
|
2547 |
|
|
+ } return false;
|
2548 |
|
|
+}
|
2549 |
|
|
+
|
2550 |
142 |
dgisselq |
+bool
|
2551 |
127 |
dgisselq |
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
|
2552 |
142 |
dgisselq |
+ rtx_insn *insn;
|
2553 |
103 |
dgisselq |
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2554 |
102 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
|
2555 |
|
|
+ if (dbg) zip_debug_rtx_pfx("DST", dst);
|
2556 |
|
|
+ if (dbg) zip_debug_rtx_pfx("CND", condition);
|
2557 |
|
|
+ if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
|
2558 |
|
|
+ if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
|
2559 |
127 |
dgisselq |
+
|
2560 |
|
|
+ // Start with the condition
|
2561 |
|
|
+ rtx cmpa = XEXP(condition,0), cmpb=XEXP(condition,1);
|
2562 |
|
|
+ enum rtx_code cmpcode = GET_CODE(condition);
|
2563 |
|
|
+
|
2564 |
142 |
dgisselq |
+ // Want to always do the false expression, and only sometimes the
|
2565 |
|
|
+ // true expression. If, however, the false is a constant and the
|
2566 |
|
|
+ // true and destination are the same thing, this doesn't work.
|
2567 |
|
|
+ if (rtx_equal_p(dst, iftrue)) {
|
2568 |
|
|
+ // If the true value is the same as the destination already,
|
2569 |
|
|
+ // then swap so we only do the condition on true
|
2570 |
|
|
+ rtx tem = iffalse;
|
2571 |
|
|
+ iffalse = iftrue;
|
2572 |
|
|
+ iftrue = tem;
|
2573 |
|
|
+ cmpcode = reverse_condition(cmpcode);
|
2574 |
|
|
+ }
|
2575 |
|
|
+
|
2576 |
127 |
dgisselq |
+ //; Do we need to swap or adjust the condition?
|
2577 |
|
|
+ if (zip_supported_condition((int)cmpcode)) {
|
2578 |
|
|
+ // Keep everything as is
|
2579 |
142 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Condition is supported\n");
|
2580 |
127 |
dgisselq |
+ } else if ((zip_supported_condition(reverse_condition(cmpcode)))
|
2581 |
142 |
dgisselq |
+ &&(!MEM_P(iffalse))
|
2582 |
|
|
+ &&(!rtx_equal_p(dst,iffalse))) {
|
2583 |
127 |
dgisselq |
+ rtx tem = iffalse;
|
2584 |
|
|
+ iffalse = iftrue;
|
2585 |
|
|
+ iftrue = tem;
|
2586 |
|
|
+
|
2587 |
|
|
+ cmpcode = reverse_condition(cmpcode);
|
2588 |
|
|
+ } else if ((zip_supported_condition((int)swap_condition(cmpcode)))
|
2589 |
|
|
+ &&((REG_P(cmpb))||(can_create_pseudo_p()))) {
|
2590 |
|
|
+ rtx tem = cmpa;
|
2591 |
|
|
+ cmpa = cmpb;
|
2592 |
|
|
+ cmpa = tem;
|
2593 |
|
|
+ cmpcode = swap_condition(cmpcode);
|
2594 |
|
|
+
|
2595 |
|
|
+ if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode))
|
2596 |
|
|
+ &&(REG_P(XEXP(cmpa,0)))
|
2597 |
|
|
+ &&(CONST_INT_P(XEXP(cmpa,1)))
|
2598 |
|
|
+ &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) {
|
2599 |
|
|
+
|
2600 |
|
|
+ // If we were doing CMP x(Rb),Ra
|
2601 |
|
|
+ // and we just changed it to CMP Ra,x(Rb)
|
2602 |
|
|
+ // adjust it to CMP -x(Ra),Rb
|
2603 |
|
|
+ cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1)));
|
2604 |
|
|
+ cmpa = XEXP(cmpa,0);
|
2605 |
|
|
+ } else if (!REG_P(cmpa)) {
|
2606 |
|
|
+ // Otherwise, if we had anything else in Rb other than
|
2607 |
|
|
+ // a register ... such as a constant, then load it into
|
2608 |
|
|
+ // a register before comparing it. So
|
2609 |
|
|
+ // CMP x,Ra
|
2610 |
|
|
+ // became
|
2611 |
|
|
+ // CMP Ra,x
|
2612 |
|
|
+ // now becomes
|
2613 |
|
|
+ // LDI x,Rt
|
2614 |
|
|
+ // CMP Ra,Rt
|
2615 |
|
|
+ // (We already tested for can_create_pseudo_p() above..)
|
2616 |
|
|
+ tem = gen_reg_rtx(SImode);
|
2617 |
|
|
+ emit_move_insn(tem, cmpa);
|
2618 |
|
|
+ cmpa = tem;
|
2619 |
102 |
dgisselq |
+ }
|
2620 |
127 |
dgisselq |
+ } else {
|
2621 |
|
|
+ // Here's our last chance.
|
2622 |
|
|
+ // This will adjust for less than equal types of stuff
|
2623 |
|
|
+ int cod = (int)cmpcode;
|
2624 |
|
|
+ zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false);
|
2625 |
|
|
+ cmpcode = (enum rtx_code)cod;
|
2626 |
102 |
dgisselq |
+ }
|
2627 |
|
|
+
|
2628 |
142 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Post-Modes\n");
|
2629 |
|
|
+ if (dbg) zip_debug_rtx_pfx("DST-P: ", dst);
|
2630 |
|
|
+ if (dbg) zip_debug_rtx_pfx("CND-P: ", condition);
|
2631 |
|
|
+ if (dbg) zip_debug_rtx_pfx("TRU-P: ", iftrue);
|
2632 |
|
|
+ if (dbg) zip_debug_rtx_pfx("FAL-P: ", iffalse);
|
2633 |
|
|
+
|
2634 |
|
|
+ if (!zip_supported_condition((int)cmpcode)) {
|
2635 |
|
|
+ if (dbg) {
|
2636 |
|
|
+ fprintf(stderr, "ZIP::MOVSICC -- Unsupported condition: ");
|
2637 |
|
|
+ zip_debug_ccode(cmpcode);
|
2638 |
|
|
+ fprintf(stderr, "\n");
|
2639 |
|
|
+ }
|
2640 |
|
|
+ return false;
|
2641 |
|
|
+ }
|
2642 |
127 |
dgisselq |
+ gcc_assert(zip_supported_condition((int)cmpcode));
|
2643 |
|
|
+
|
2644 |
|
|
+ //; Always do the default move
|
2645 |
142 |
dgisselq |
+ bool conditionally_do_false = false;
|
2646 |
|
|
+ conditionally_do_false = (MEM_P(iffalse))
|
2647 |
|
|
+ &&(!rtx_equal_p(dst,iffalse))
|
2648 |
|
|
+ &&(zip_supported_condition(reverse_condition(cmpcode)));
|
2649 |
|
|
+ conditionally_do_false = conditionally_do_false || (rtx_equal_p(dst,iftrue));
|
2650 |
|
|
+ if ((conditionally_do_false)&&(!zip_supported_condition(reverse_condition(cmpcode)))) {
|
2651 |
|
|
+ if (dbg) {
|
2652 |
|
|
+ fprintf(stderr, "ZIP::MOVSICC -- Cant support the reverse condition: ");
|
2653 |
|
|
+ zip_debug_ccode(cmpcode);
|
2654 |
|
|
+ fprintf(stderr, "\n");
|
2655 |
|
|
+ }
|
2656 |
|
|
+ return false;
|
2657 |
|
|
+ }
|
2658 |
127 |
dgisselq |
+
|
2659 |
142 |
dgisselq |
+ if ((!rtx_equal_p(dst, iffalse))&&(!conditionally_do_false)) {
|
2660 |
|
|
+ if (dbg)
|
2661 |
|
|
+ fprintf(stderr, "ZIP::MOVSICC -- EMITTING MOVE FALSE->DST\n");
|
2662 |
|
|
+ insn = emit_move_insn(dst, iffalse);
|
2663 |
|
|
+ if (dbg) zip_debug_rtx_pfx("BARE-U: ", insn);
|
2664 |
|
|
+ }
|
2665 |
|
|
+
|
2666 |
127 |
dgisselq |
+ rtx cc_rtx = gen_rtx_REG(CCmode, zip_CC);
|
2667 |
|
|
+
|
2668 |
|
|
+ //; Now let's get our comparison right
|
2669 |
142 |
dgisselq |
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING COMPARISON\n");
|
2670 |
|
|
+ insn = emit_insn(gen_rtx_SET(VOIDmode, cc_rtx,
|
2671 |
127 |
dgisselq |
+ gen_rtx_COMPARE(CCmode, cmpa, cmpb)));
|
2672 |
142 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("BARE-C: ", insn);
|
2673 |
127 |
dgisselq |
+
|
2674 |
|
|
+ //; Finally, let's load the value on true
|
2675 |
142 |
dgisselq |
+ if (!rtx_equal_p(dst, iftrue)) {
|
2676 |
|
|
+ if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING BARE\n");
|
2677 |
|
|
+ insn=emit_insn(gen_movsicc_bare(dst,
|
2678 |
127 |
dgisselq |
+ gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX),
|
2679 |
|
|
+ iftrue, dst));
|
2680 |
142 |
dgisselq |
+ if (dbg) zip_debug_rtx_pfx("BARE-T: ", insn);
|
2681 |
|
|
+ }
|
2682 |
|
|
+
|
2683 |
|
|
+ if (conditionally_do_false) {
|
2684 |
|
|
+ gcc_assert(zip_supported_condition(reverse_condition(cmpcode)));
|
2685 |
|
|
+ insn=emit_insn(gen_movsicc_bare(dst,
|
2686 |
|
|
+ gen_rtx_fmt_ee(reverse_condition(cmpcode), SImode,
|
2687 |
|
|
+ NULL_RTX, NULL_RTX), iffalse, dst));
|
2688 |
|
|
+ if (dbg) zip_debug_rtx_pfx("BARE-F: ", insn);
|
2689 |
|
|
+ }
|
2690 |
|
|
+
|
2691 |
|
|
+ // Return true on success
|
2692 |
|
|
+ return true;
|
2693 |
102 |
dgisselq |
+}
|
2694 |
|
|
+
|
2695 |
|
|
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
|
2696 |
|
|
+ // We know upon entry that REG_P(dst) must be true
|
2697 |
|
|
+ if (!REG_P(dst))
|
2698 |
|
|
+ internal_error("%s","ADDSICC into something other than register");
|
2699 |
|
|
+ if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
|
2700 |
|
|
+ switch (GET_CODE(condition)) {
|
2701 |
|
|
+ case EQ: return "ADD.Z\t%3,%0";
|
2702 |
|
|
+ case NE: return "ADD.NZ\t%3,%0";
|
2703 |
|
|
+ case LT: return "ADD.LT\t%3,%0";
|
2704 |
|
|
+ case GT: return "ADD.GT\t%3,%0";
|
2705 |
|
|
+ case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
|
2706 |
|
|
+ case GE: return "ADD.GE\t%3,%0";
|
2707 |
|
|
+ case LTU: return "ADD.C\t%3,%0";
|
2708 |
|
|
+ case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
|
2709 |
|
|
+ case GEU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tXOR\t2,CC";
|
2710 |
|
|
+ // Can do a GEU comparison, and then undo on the Zero condition
|
2711 |
|
|
+ case GTU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tSUB.Z\t%3,%0\n\tXOR\t2,CC";
|
2712 |
|
|
+ default:
|
2713 |
|
|
+ internal_error("%s", "Zip/No usable addsi expansion");
|
2714 |
|
|
+ break;
|
2715 |
|
|
+ }
|
2716 |
|
|
+ } else {
|
2717 |
|
|
+ // MOV A+REG,REG
|
2718 |
|
|
+ switch (GET_CODE(condition)) {
|
2719 |
|
|
+ case EQ: return "MOV.Z\t%3+%2,%0";
|
2720 |
|
|
+ case NE: return "MOV.NZ\t%3+%2,%0";
|
2721 |
|
|
+ case LT: return "MOV.LT\t%3+%2,%0";
|
2722 |
|
|
+ case GT: return "MOV.GT\t%3+%2,%0";
|
2723 |
|
|
+ case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
2724 |
|
|
+ case GE: return "MOV.GE\t%3+%2,%0";
|
2725 |
|
|
+ case LTU: return "MOV.C\t%3+%2,%0";
|
2726 |
|
|
+ case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
|
2727 |
|
|
+ case GEU: return "XOR\t2,CC\n\tMOV.C\t%3+%2,%0\n\tXOR\t2,CC";
|
2728 |
|
|
+ // Can do a GEU comparison, and then undo on the Zero condition
|
2729 |
|
|
+ // EXCEPT: with a move instruction, what's there to undo? We
|
2730 |
|
|
+ // just clobbered our register!
|
2731 |
|
|
+ // case GTU: return "XOR\t2,CC\n\tMOV.C\t%3,%0\n\tSUB.Z\t%3,%0XOR\t2,CC";
|
2732 |
|
|
+ default:
|
2733 |
|
|
+ internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
|
2734 |
|
|
+ break;
|
2735 |
|
|
+ }
|
2736 |
|
|
+ }
|
2737 |
|
|
+
|
2738 |
|
|
+ return "BREAK";
|
2739 |
|
|
+}
|
2740 |
|
|
+
|
2741 |
103 |
dgisselq |
+static int zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
|
2742 |
102 |
dgisselq |
+ int rv = 14;
|
2743 |
|
|
+ if ((mode == DImode)||(mode == DFmode))
|
2744 |
|
|
+ rv += 2;
|
2745 |
|
|
+ return rv;
|
2746 |
|
|
+}
|
2747 |
|
|
+
|
2748 |
103 |
dgisselq |
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
|
2749 |
117 |
dgisselq |
+static bool zip_cannot_modify_jumps_p(void) {
|
2750 |
|
|
+ // Let's try their suggested approach, keeping us from modifying jumps
|
2751 |
|
|
+ // after reload. This should also allow our peephole2 optimizations
|
2752 |
|
|
+ // to adjust things back to what they need to be if necessary.
|
2753 |
|
|
+ return (reload_completed || reload_in_progress);
|
2754 |
|
|
+}
|
2755 |
122 |
dgisselq |
+
|
2756 |
|
|
+rtx_insn *zip_ifcvt_info;
|
2757 |
|
|
+
|
2758 |
|
|
+void
|
2759 |
|
|
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
|
2760 |
|
|
+ const bool dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
|
2761 |
|
|
+ if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
|
2762 |
|
|
+ if (*true_expr) switch(GET_CODE(*true_expr)) {
|
2763 |
|
|
+ case LE:
|
2764 |
|
|
+ case GTU:
|
2765 |
|
|
+ case GEU:
|
2766 |
|
|
+ case LEU:
|
2767 |
|
|
+ if (dbg) fprintf(stderr, "TRUE, missing expr\n");
|
2768 |
|
|
+ if (dbg) zip_debug_rtx(*true_expr);
|
2769 |
|
|
+ *true_expr = NULL_RTX;
|
2770 |
|
|
+ break;
|
2771 |
|
|
+ default: // LT, GT, GTE, LTU, NE, EQ
|
2772 |
|
|
+ break;
|
2773 |
|
|
+ }
|
2774 |
|
|
+
|
2775 |
|
|
+ if (*false_expr) switch(GET_CODE(*false_expr)) {
|
2776 |
|
|
+ case LE:
|
2777 |
|
|
+ case GTU:
|
2778 |
|
|
+ case GEU:
|
2779 |
|
|
+ case LEU:
|
2780 |
|
|
+ if (dbg) fprintf(stderr, "FALSE, missing expr\n");
|
2781 |
|
|
+ if (dbg) zip_debug_rtx(*false_expr);
|
2782 |
|
|
+ *false_expr = NULL_RTX;
|
2783 |
|
|
+ default:
|
2784 |
|
|
+ break;
|
2785 |
|
|
+ }
|
2786 |
|
|
+ if ((dbg)&&((!*true_expr)||(!*false_expr)))
|
2787 |
|
|
+ fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n");
|
2788 |
|
|
+}
|
2789 |
|
|
+
|
2790 |
|
|
+void
|
2791 |
142 |
dgisselq |
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
|
2792 |
122 |
dgisselq |
+/*
|
2793 |
142 |
dgisselq |
+if (!ceinfo->then_bb)
|
2794 |
|
|
+ return;
|
2795 |
|
|
+rtx_insn *insn;
|
2796 |
|
|
+FOR_BB_INSNS(ceinfo->then_bb, insn) {
|
2797 |
|
|
+ fprintf(stderr, "IFCVT -- INIT\n");
|
2798 |
|
|
+ zip_debug_rtx_pfx("INIT-BB", insn);
|
2799 |
122 |
dgisselq |
+}
|
2800 |
|
|
+*/
|
2801 |
|
|
+/*
|
2802 |
|
|
+ zip_ifcvt_info = NULL;
|
2803 |
|
|
+ rtx_insn *insn, *ifinsn = NULL;
|
2804 |
|
|
+ FOR_BB_INSNS(ceinfo->test_bb, insn) {
|
2805 |
|
|
+ rtx p;
|
2806 |
|
|
+ p = single_set(insn);
|
2807 |
|
|
+ if (!p) continue;
|
2808 |
|
|
+ if (SET_DEST(p)==pc_rtx) {
|
2809 |
|
|
+ ifinsn = insn;
|
2810 |
|
|
+ }
|
2811 |
|
|
+ if (!REG_P(SET_DEST(p)))
|
2812 |
|
|
+ continue;
|
2813 |
|
|
+ if (GET_MODE(SET_DEST(p))!=CCmode)
|
2814 |
|
|
+ continue;
|
2815 |
|
|
+ if (REGNO(SET_DEST(p))!=zip_CC)
|
2816 |
|
|
+ continue;
|
2817 |
|
|
+ zip_ifcvt_info = insn;
|
2818 |
|
|
+ }
|
2819 |
|
|
+
|
2820 |
|
|
+ if (zip_ifcvt_info)
|
2821 |
|
|
+ zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info);
|
2822 |
|
|
+ if (ifinsn)
|
2823 |
|
|
+ zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
|
2824 |
|
|
+*/
|
2825 |
|
|
+}
|
2826 |
|
|
+
|
2827 |
142 |
dgisselq |
+void
|
2828 |
|
|
+zip_ifcvt_modify_insn(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED,
|
2829 |
|
|
+ rtx pattern ATTRIBUTE_UNUSED,
|
2830 |
|
|
+ rtx_insn *insn ATTRIBUTE_UNUSED) {
|
2831 |
|
|
+ // zip_debug_rtx_pfx("MODIFY-INSN: ", insn);
|
2832 |
|
|
+}
|
2833 |
|
|
+
|
2834 |
|
|
+void
|
2835 |
|
|
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
|
2836 |
|
|
+/*
|
2837 |
|
|
+ fprintf(stderr, "IFCVT -- CANCEL\n");
|
2838 |
|
|
+ zip_ifcvt_info = NULL;
|
2839 |
|
|
+*/
|
2840 |
|
|
+}
|
2841 |
|
|
+
|
2842 |
|
|
+void
|
2843 |
|
|
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
|
2844 |
|
|
+/*
|
2845 |
|
|
+rtx_insn *insn;
|
2846 |
|
|
+FOR_BB_INSNS(ceinfo->test_bb, insn) {
|
2847 |
|
|
+ fprintf(stderr, "IFCVT -- FINAL\n");
|
2848 |
|
|
+ zip_debug_rtx_pfx("FINAL-TEST-BB", insn);
|
2849 |
|
|
+}
|
2850 |
|
|
+ zip_ifcvt_info = NULL;
|
2851 |
|
|
+*/
|
2852 |
|
|
+}
|
2853 |
|
|
+
|
2854 |
|
|
+
|
2855 |
127 |
dgisselq |
+int zip_insn_sets_cc(rtx_insn *insn) {
|
2856 |
|
|
+ return (get_attr_ccresult(insn)==CCRESULT_SET);
|
2857 |
|
|
+}
|
2858 |
|
|
+
|
2859 |
|
|
+int zip_is_conditional(rtx_insn *insn) {
|
2860 |
|
|
+ return (get_attr_conditional(insn)==CONDITIONAL_YES);
|
2861 |
|
|
+}
|
2862 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
|
2863 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip.h 1969-12-31 19:00:00.000000000 -0500
|
2864 |
171 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h 2016-09-13 10:05:21.871953479 -0400
|
2865 |
|
|
@@ -0,0 +1,4058 @@
|
2866 |
102 |
dgisselq |
+////////////////////////////////////////////////////////////////////////////////
|
2867 |
|
|
+//
|
2868 |
|
|
+// Filename: gcc/config/zip/zip.h
|
2869 |
|
|
+//
|
2870 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
2871 |
|
|
+//
|
2872 |
|
|
+// Purpose:
|
2873 |
|
|
+//
|
2874 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
2875 |
|
|
+// Gisselquist Technology, LLC
|
2876 |
|
|
+//
|
2877 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
2878 |
|
|
+//
|
2879 |
|
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
2880 |
|
|
+//
|
2881 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
2882 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
2883 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
2884 |
|
|
+// your option) any later version.
|
2885 |
|
|
+//
|
2886 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
2887 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
2888 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
2889 |
|
|
+// for more details.
|
2890 |
|
|
+//
|
2891 |
|
|
+// You should have received a copy of the GNU General Public License along
|
2892 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
2893 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
2894 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
2895 |
|
|
+//
|
2896 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
2897 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
2898 |
|
|
+//
|
2899 |
|
|
+//
|
2900 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
2901 |
|
|
+#ifndef GCC_ZIP_H
|
2902 |
|
|
+#define GCC_ZIP_H
|
2903 |
|
|
+
|
2904 |
|
|
+
|
2905 |
|
|
+//
|
2906 |
|
|
+//
|
2907 |
127 |
dgisselq |
+// Zip CPU configuration defines
|
2908 |
102 |
dgisselq |
+//
|
2909 |
|
|
+//
|
2910 |
|
|
+#define ZIP_USER 0 // Assume we are in supervisor mode
|
2911 |
|
|
+#define ZIP_MULTIPLY 1 // Assume we have multiply instructions
|
2912 |
|
|
+#define ZIP_DIVIDE 1 // Assume we have divide instructions
|
2913 |
|
|
+#define ZIP_FPU 0 // Assume we have no floating point instructions
|
2914 |
|
|
+#define ZIP_PIPELINED 1 // Assume our instructions are pipelined
|
2915 |
|
|
+#define ZIP_VLIW 1 // Assume we have the VLIW feature
|
2916 |
|
|
+#define ZIP_ATOMIC ((ZIP_PIPELINED)&&(ZIP_VLIW))
|
2917 |
|
|
+#define ZIP_PIC 0 // Attempting to produce PIC code, with GOT
|
2918 |
|
|
+#define ZIP_HAS_DI 1
|
2919 |
127 |
dgisselq |
+// Should we use the peephole optimizations?
|
2920 |
|
|
+#define ZIP_PEEPHOLE 1 // 0 means no peephole optimizations.
|
2921 |
138 |
dgisselq |
+// How about the new long multiply instruction set?
|
2922 |
|
|
+#define ZIP_LONGMPY 1 // 0 means use the old instruction set
|
2923 |
102 |
dgisselq |
+
|
2924 |
|
|
+// Zip has 16 registers in each user mode.
|
2925 |
|
|
+// Register 15 is the program counter (PC)
|
2926 |
|
|
+// Register 14 is the condition codes (CC)
|
2927 |
|
|
+// Register 13 is the stack pointer (SP)
|
2928 |
|
|
+// Register 12 (may be) the Global Offset Table pointer (GOT)
|
2929 |
|
|
+// Register 0 (may be) the return address pointer
|
2930 |
|
|
+// Registers 16-31 may only be used in supervisor mode.
|
2931 |
|
|
+#define is_ZIP_GENERAL_REG(REGNO) ((REGNO)<13)
|
2932 |
171 |
dgisselq |
+#define is_ZIP_REG(REGNO) ((REGNO)<33)
|
2933 |
102 |
dgisselq |
+
|
2934 |
171 |
dgisselq |
+#define zip_AP_PSEUDO 32
|
2935 |
103 |
dgisselq |
+#define zip_PC 15
|
2936 |
|
|
+#define zip_CC 14
|
2937 |
|
|
+#define zip_SP 13
|
2938 |
|
|
+#define zip_FP 12
|
2939 |
|
|
+#define zip_GOT 11
|
2940 |
171 |
dgisselq |
+// #define zip_AP 10 // We're using a PSEUDO REG instead
|
2941 |
103 |
dgisselq |
+#define zip_R1 1
|
2942 |
|
|
+#define zip_R0 0
|
2943 |
102 |
dgisselq |
+
|
2944 |
|
|
+#define ZIP_FIRST_ARG_REGNO 1
|
2945 |
|
|
+#define ZIP_LAST_ARG_REGNO 5
|
2946 |
111 |
dgisselq |
+#define NUM_ARG_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
2947 |
|
|
+#define MAX_PARM_REGS (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
|
2948 |
102 |
dgisselq |
+
|
2949 |
|
|
+/* The overall framework of an assembler file */
|
2950 |
|
|
+
|
2951 |
|
|
+#define ASM_COMMENT_START ";"
|
2952 |
|
|
+#define ASM_APP_ON ""
|
2953 |
|
|
+#define ASM_APP_OFF ""
|
2954 |
|
|
+
|
2955 |
|
|
+#define FILE_ASM_OP "\t.file\n"
|
2956 |
|
|
+
|
2957 |
|
|
+/* Output and Generation of Labels */
|
2958 |
|
|
+#define GLOBAL_ASM_OP "\t.global\t"
|
2959 |
|
|
+
|
2960 |
|
|
+#undef BITS_PER_UNIT
|
2961 |
|
|
+#define BITS_PER_UNIT (32)
|
2962 |
|
|
+
|
2963 |
|
|
+/* Assembler Commands for Alignment */
|
2964 |
|
|
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
2965 |
127 |
dgisselq |
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
|
2966 |
102 |
dgisselq |
+
|
2967 |
|
|
+
|
2968 |
|
|
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
|
2969 |
|
|
+ * for an instruction operand X. */
|
2970 |
|
|
+#define PRINT_OPERAND(STREAM, X, CODE) zip_print_operand(STREAM, X, CODE)
|
2971 |
|
|
+#define PRINT_OPERAND_ADDRESS(STREAM, X) zip_print_operand_address(STREAM, X)
|
2972 |
|
|
+
|
2973 |
|
|
+/* Passing arguments in registers */
|
2974 |
|
|
+#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO)==zip_R1)
|
2975 |
|
|
+
|
2976 |
|
|
+/* Define how to find the value returned by a function. VALTYPE is the data
|
2977 |
|
|
+ * type of the value (as a tree). If the precise function being called is known
|
2978 |
|
|
+ * FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */
|
2979 |
|
|
+#define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG(TYPE_MODE(VALTYPE), zip_R1)
|
2980 |
|
|
+
|
2981 |
|
|
+/* Define how to find the value returned by a library function assuming the
|
2982 |
|
|
+ * value has mode MODE.
|
2983 |
|
|
+ */
|
2984 |
|
|
+#define LIBCALL_VALUE(MODE) gen_rtx_REG(MODE, zip_R1)
|
2985 |
|
|
+
|
2986 |
|
|
+
|
2987 |
|
|
+/* STACK AND CALLING */
|
2988 |
|
|
+
|
2989 |
|
|
+
|
2990 |
|
|
+/* Define this macro as a C expression that is nonzero for registers that are
|
2991 |
|
|
+ * used by the epilogue or the return pattern. The stack and frame pointer
|
2992 |
|
|
+ * registers are already assumed to be used as needed.
|
2993 |
|
|
+ */
|
2994 |
|
|
+#define EPILOGUE_USES(R) (R == RETURN_ADDRESS_REGNUM)
|
2995 |
|
|
+
|
2996 |
|
|
+
|
2997 |
|
|
+/* The best alignment to use in cases where we have a choice. */
|
2998 |
127 |
dgisselq |
+#define FASTEST_ALIGNMENT BITS_PER_WORD
|
2999 |
102 |
dgisselq |
+
|
3000 |
|
|
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
|
3001 |
|
|
+ * largest integer machine mode that should actually be used. All integer
|
3002 |
|
|
+ * machine modes of this size and smaller can be used for structures and unions
|
3003 |
|
|
+ * with the appropriate sizes. If this macro is undefined,
|
3004 |
|
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
3005 |
|
|
+ *
|
3006 |
|
|
+ * ZipCPU -- The default looks good enough for us.
|
3007 |
|
|
+ */
|
3008 |
|
|
+
|
3009 |
|
|
+/* Generate Code for Profiling
|
3010 |
|
|
+ */
|
3011 |
|
|
+#define FUNCTION_PROFILER(FILE,LABELNO) (abort(), 0)
|
3012 |
|
|
+
|
3013 |
|
|
+
|
3014 |
|
|
+/* A C expression which is nonzero if register number NUM is suitable for use
|
3015 |
|
|
+ * as an index register in operand addresses.
|
3016 |
|
|
+ */
|
3017 |
|
|
+#define REGNO_OK_FOR_INDEX_P(NUM) 0
|
3018 |
|
|
+
|
3019 |
|
|
+
|
3020 |
|
|
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
|
3021 |
|
|
+ * (an RTX) is a legitimate memory address on the target machine for a memory
|
3022 |
|
|
+ * operand of mode MODE.
|
3023 |
|
|
+ */
|
3024 |
111 |
dgisselq |
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
|
3025 |
|
|
+// DRIVER_SELF_SPECS
|
3026 |
|
|
+// OPTION_DEFAULT_SPECS
|
3027 |
|
|
+// CPP_SPEC
|
3028 |
|
|
+// CPLUSPLUS_CPP_SPEC
|
3029 |
|
|
+// CC1_SPEC
|
3030 |
|
|
+// CC1PLUS_SPEC
|
3031 |
|
|
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
|
3032 |
|
|
+ * to pass to the assembler. It can also specify how to translate options you
|
3033 |
|
|
+ * give to GCC into options for GCC to pass to the assembler. See the file
|
3034 |
|
|
+ * 'sun3.h' for an example of this.
|
3035 |
|
|
+ *
|
3036 |
|
|
+ * Do not define thismacro if it does not need to do anything.
|
3037 |
|
|
+ */
|
3038 |
|
|
+// #undef ASM_SPEC
|
3039 |
|
|
+// ASM_FINAL_SPEC
|
3040 |
|
|
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
|
3041 |
|
|
+
|
3042 |
|
|
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
|
3043 |
|
|
+ * to pass to the linker. It can also specify how to translate options you give
|
3044 |
|
|
+ * to GCC into options for GCC to pass to the linker.
|
3045 |
|
|
+ *
|
3046 |
|
|
+ * Do not define this macro if it does not need to do anything.
|
3047 |
|
|
+ */
|
3048 |
|
|
+
|
3049 |
|
|
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC. The
|
3050 |
|
|
+ * difference between the two is that LIB_SPEC is used at the end of the
|
3051 |
|
|
+ * command given to the linker.
|
3052 |
|
|
+ *
|
3053 |
|
|
+ * If this macro is not defined, a default is provided that loads the standard
|
3054 |
|
|
+ * C library from the usual place. See 'gcc.c'.
|
3055 |
|
|
+ */
|
3056 |
|
|
+#undef LIB_SPEC
|
3057 |
|
|
+// #define LIB_SPEC "%{!g:-lc} %{g:-lg} -lzip"
|
3058 |
|
|
+#define LIB_SPEC ""
|
3059 |
|
|
+
|
3060 |
|
|
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
|
3061 |
|
|
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
|
3062 |
|
|
+ * line. This constant is placed both before and after the value of LIB_SPEC.
|
3063 |
|
|
+ *
|
3064 |
|
|
+ * If this macro is not defined, the GCC driver provides a default that passes
|
3065 |
|
|
+ * the string '-lgcc' to the linker.
|
3066 |
|
|
+ */
|
3067 |
|
|
+#undef LIBGCC_SPEC
|
3068 |
|
|
+#define LIBGCC_SPEC ""
|
3069 |
|
|
+
|
3070 |
|
|
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
|
3071 |
|
|
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
|
3072 |
|
|
+ * modified to refer to different versions of 'libgcc.a' depending on the
|
3073 |
|
|
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
|
3074 |
|
|
+ * and '-shared-libgcc'. On targets where these modifications are
|
3075 |
|
|
+ * inappropriate, define REAL_LIBGCC_SPEC instead. REAL_LIBGCC_SPEC tells the
|
3076 |
|
|
+ * driver how to place a reference to 'libgcc' on the link command line, but
|
3077 |
|
|
+ * unlike LIBGCC_SPEC, it is used unmodified.
|
3078 |
|
|
+ */
|
3079 |
|
|
+#define REAL_LIBGCC_SPEC ""
|
3080 |
|
|
+
|
3081 |
|
|
+// USE_LD_AS_NEEDED
|
3082 |
|
|
+// LINK_EH_SPEC
|
3083 |
|
|
+
|
3084 |
|
|
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC. The
|
3085 |
|
|
+ * difference between the two is that STARTFILE_SPEC is used at the very
|
3086 |
|
|
+ * beginning of the command given to the linker.
|
3087 |
|
|
+ *
|
3088 |
|
|
+ * If this macro is not defined, a default is provided that loads the standard
|
3089 |
|
|
+ * C startup file from the usual place. See 'gcc.c'
|
3090 |
|
|
+ */
|
3091 |
|
|
+#undef STARTFILE_SPEC
|
3092 |
|
|
+#define STARTFILE_SPEC ""
|
3093 |
|
|
+
|
3094 |
|
|
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC. The
|
3095 |
|
|
+ * difference between the two is that ENDFILE_SPEC is used at the very end
|
3096 |
|
|
+ * of the command given to the linker.
|
3097 |
|
|
+ *
|
3098 |
|
|
+ * Do not define this macro if it does not do anything.
|
3099 |
|
|
+ */
|
3100 |
|
|
+// #undef ENDFILE_SPEC
|
3101 |
|
|
+// #define ENDFILE_SPEC ""
|
3102 |
|
|
+
|
3103 |
|
|
+// THREAD_MODEL_SPEC
|
3104 |
|
|
+// SYSROOT_SUFFIX_SPEC
|
3105 |
|
|
+// SYSROOT_HEADERS_SUFFIX_SPEC
|
3106 |
|
|
+// EXTRA_SPECS
|
3107 |
|
|
+// LINK_LIBGCC_SPECIAL_1
|
3108 |
|
|
+// LINK_GCC_C_SEQUENCE_SPEC
|
3109 |
|
|
+// LINK_COMMAND_SPEC
|
3110 |
|
|
+// TARGET_ALWAYS_STRIP_DOTDOT
|
3111 |
|
|
+// MULTILIB_DEFAULTS
|
3112 |
|
|
+// RELATIVE_PREFIX_NOT_LINKDIR
|
3113 |
|
|
+// MD_EXEC_PREFIX
|
3114 |
|
|
+// STANDARD_STARTFILE_PREFIX
|
3115 |
|
|
+// STANDARD_STARTFILE_PREFIX_1
|
3116 |
|
|
+// STANDARD_STARTFILE_PREFIX_2
|
3117 |
|
|
+// MD_STARTFILE_PREFIX
|
3118 |
|
|
+// MD_STARTFILE_PREFIX_1
|
3119 |
|
|
+// INIT_ENVIRONMENT
|
3120 |
|
|
+// LOCAL_INCLUDE_DIR
|
3121 |
|
|
+#undef LOCAL_INCLUDE_DIR
|
3122 |
|
|
+
|
3123 |
|
|
+// NATIVE_SYSTEM_HEADER_COMPONENT
|
3124 |
|
|
+// INCLUDE_DEFAULTS
|
3125 |
|
|
+
|
3126 |
102 |
dgisselq |
+/* 17.03 Run-time Target Specification */
|
3127 |
|
|
+
|
3128 |
|
|
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
|
3129 |
|
|
+ * code that defines built-in preprocessor macros and assertions for the target
|
3130 |
|
|
+ * CPU, using the functions builtin_define, builtin_define_std, and
|
3131 |
|
|
+ * builtin_assert. When the front end calls this macro it provides a trailing
|
3132 |
|
|
+ * semicolon, and since it has finished command line option proccessing your
|
3133 |
|
|
+ * code can use those results freely.
|
3134 |
|
|
+ *
|
3135 |
|
|
+ * ZipCPU --- We should probably capture in this macro what capabilities the
|
3136 |
|
|
+ * command line parameters we've been given indicate that our CPU has. That
|
3137 |
|
|
+ * way, code can be adjusted depending upon the CPU's capabilities.
|
3138 |
|
|
+ */
|
3139 |
|
|
+#define TARGET_CPU_CPP_BUILTINS() \
|
3140 |
|
|
+ { builtin_define("__ZIPCPU__"); \
|
3141 |
|
|
+ if (ZIP_FPU) builtin_define("__ZIPFPU__"); \
|
3142 |
|
|
+ if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__"); \
|
3143 |
|
|
+ }
|
3144 |
|
|
+ // If (zip_param_has_fpu) builtin_define("__ZIPFPU__");
|
3145 |
|
|
+ // If (zip_param_has_div) builtin_define("__ZIPDIV__");
|
3146 |
|
|
+ // If (zip_param_has_mpy) builtin_define("__ZIPMPY__");
|
3147 |
|
|
+ // If (zip_param_has_lock) builtin_define("__ZIPLOCK__");
|
3148 |
|
|
+ // If (zip_param_supervisor) builtin_define("__ZIPUREGS__");
|
3149 |
|
|
+ // If (we support int64s) builtin_define("___int64_t_defined");
|
3150 |
|
|
+
|
3151 |
|
|
+/* TARGET_OS_CPP_BUILTINS() ... Similarly to TARGET_CPU_CPP_BUILTINS but this
|
3152 |
|
|
+ * macro is optional and is used for the target operating system instead.
|
3153 |
|
|
+ */
|
3154 |
|
|
+
|
3155 |
|
|
+/* Option macros: (we need to define these eventually ... )
|
3156 |
|
|
+ *
|
3157 |
|
|
+ * TARGET_HANDLE_OPTION
|
3158 |
|
|
+ * TARGET_HANDLE_C_OPTION
|
3159 |
|
|
+ * TARGET_OBJ_CONSTRUCT_STRING_OBJECT
|
3160 |
|
|
+ * TARGET_OBJ_DECLARE_UNRESOLVED_CLASS_REFERENCE
|
3161 |
|
|
+ * TARGET_OBJ_DECLARE_CLASS_DEFINITION
|
3162 |
|
|
+ * TARGET_STRING_OBJECT_REF_TYPE_P
|
3163 |
|
|
+ * TARGET_CHECK_STRING_OBJECT_FORMAT_ARG
|
3164 |
|
|
+ * TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE(VOID)
|
3165 |
|
|
+ * C_COMMON_OVERRIDE_OTPTIONS
|
3166 |
|
|
+ * TARGET_OPTION_OPTIMIZATION_TABLE
|
3167 |
|
|
+ * TARGET_OPTION_INIT_STRUCT
|
3168 |
|
|
+ * TARGET_OPTION_DEFAULT_PARAMS
|
3169 |
|
|
+ */
|
3170 |
|
|
+
|
3171 |
|
|
+/* SWITCHABLE_TARGET
|
3172 |
|
|
+ *
|
3173 |
|
|
+ * Zip CPU doesn't need this, so it defaults to zero. No need to change it
|
3174 |
|
|
+ * here.
|
3175 |
|
|
+ */
|
3176 |
|
|
+
|
3177 |
|
|
+/* TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(VOID) ... Returns true if the
|
3178 |
|
|
+ * target supports IEEE 754 floating-point exceptions and rounding modes, false
|
3179 |
|
|
+ * otherwise. This is intended to relate to the float and double types, but not
|
3180 |
|
|
+ * necessarily "long double". By default, returns true if the adddf3
|
3181 |
|
|
+ * instruction pattern is available and false otherwise, on the assumption that
|
3182 |
|
|
+ * hardware floating point supports exceptions and rounding modes but software
|
3183 |
|
|
+ * floating point does not.
|
3184 |
|
|
+ *
|
3185 |
|
|
+ * ZipCPU floating point is barely going to be functional, I doubt it will
|
3186 |
|
|
+ * support all of these bells and whistles when full functionality is even
|
3187 |
|
|
+ * achieved. Therefore, we won't support these modes. However, we can't just
|
3188 |
|
|
+ * set this to zero, so let's come back to this.
|
3189 |
|
|
+ */
|
3190 |
|
|
+// #warning "Wrong answer encoded to date"
|
3191 |
103 |
dgisselq |
+// #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
|
3192 |
102 |
dgisselq |
+// #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0
|
3193 |
|
|
+
|
3194 |
|
|
+/* 17.04 Defining data structures for per-function information */
|
3195 |
|
|
+
|
3196 |
|
|
+/* INIT_EXPANDERS ... Macro called to initialize any target specific
|
3197 |
|
|
+ * information. This macro is called once per function, before generation of
|
3198 |
|
|
+ * any RTL has begun. The intention is to allow the initialization of the
|
3199 |
|
|
+ * function pointer init_machine_status.
|
3200 |
|
|
+ */
|
3201 |
|
|
+// #warning "I may need to define this to handle function return addresses ..."
|
3202 |
|
|
+
|
3203 |
|
|
+/* 17.05 Storage Layout */
|
3204 |
|
|
+
|
3205 |
|
|
+/* Storage Layout */
|
3206 |
|
|
+#define BITS_BIG_ENDIAN 0 // MSB has highest number
|
3207 |
|
|
+#define BYTES_BIG_ENDIAN 1 // 1 if MSB is lowest number
|
3208 |
|
|
+#define WORDS_BIG_ENDIAN 1 // 1 if MSW is lowest number
|
3209 |
|
|
+#define FLOAT_WORDS_BIG_ENDIAN 1
|
3210 |
|
|
+#define BITS_PER_WORD 32
|
3211 |
|
|
+// #define MAX_BITS_PER_WORD // defaults to BITS_PER_WORD
|
3212 |
|
|
+#define UNITS_PER_WORD 1 // Storage units in a word, pwr of 2:1-8
|
3213 |
|
|
+#define MIN_UNITS_PER_WORD 1 // Default is UNITS_PER_WORD
|
3214 |
|
|
+/* POINTER_SIZE ... Width of a pointer in bits. You must specify a value no
|
3215 |
|
|
+ * wider than the width of Pmode. If it is not equal to the width of Pmode,
|
3216 |
|
|
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
|
3217 |
|
|
+ * default is BITS_PER_WORD.
|
3218 |
|
|
+ *
|
3219 |
|
|
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
|
3220 |
|
|
+ */
|
3221 |
|
|
+#define POINTER_SIZE 32 // Ptr width in bits
|
3222 |
|
|
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
|
3223 |
|
|
+ * should be extended from ptr_mode to either Pmode or word_mode. It is greater
|
3224 |
|
|
+ * than zero if pointers should be zero-extended, zero if they should be sign
|
3225 |
|
|
+ * extended, and negative if some other conversion is needed. In the last case,
|
3226 |
|
|
+ * the extension is done by the target's ptr_extend instruction.
|
3227 |
|
|
+ *
|
3228 |
|
|
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
|
3229 |
|
|
+ * the same width.
|
3230 |
|
|
+ *
|
3231 |
|
|
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
|
3232 |
|
|
+ * number of bits as SImode. Therefore, one might wish to convert between the
|
3233 |
|
|
+ * two. Hence, we specify how we would do that here.
|
3234 |
|
|
+ */
|
3235 |
127 |
dgisselq |
+#define POINTERS_EXTEND_UNSIGNED 1
|
3236 |
102 |
dgisselq |
+
|
3237 |
|
|
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
|
3238 |
|
|
+ * object whose type is type and which has he specified mode and signedness is
|
3239 |
|
|
+ * to be stored in a register. This macro is only called when type is a scalar
|
3240 |
|
|
+ * type.
|
3241 |
|
|
+ *
|
3242 |
|
|
+ * On most RISC machines, which only have operations that operate on a full
|
3243 |
|
|
+ * register, define this macro to set m to word_mode if m is an integer mode
|
3244 |
|
|
+ * narrower than BITS_PER_WORD. In most cases, only integer modes should be
|
3245 |
|
|
+ * widened because wider precision floating-point operations are usually more
|
3246 |
|
|
+ * expensive than their narrower counterparts.
|
3247 |
|
|
+ *
|
3248 |
|
|
+ * For most machines, the macro definition does not change unsigndep. However,
|
3249 |
|
|
+ * some machines, have instructions that preferentially handle either signed or
|
3250 |
|
|
+ * unsigned quantities of certain modes. For example, on the DEC Alpha, 32-bit
|
3251 |
|
|
+ * loads from memory and 32-bit add instructions sign-extend the result to
|
3252 |
|
|
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
|
3253 |
|
|
+ * is more efficient.
|
3254 |
|
|
+ *
|
3255 |
|
|
+ * Do not define this macro if it would never modify m.
|
3256 |
|
|
+ *
|
3257 |
|
|
+ * ZipCPU --- We need to always (if possible) promote everything to SImode where
|
3258 |
|
|
+ * we can handle things. HImode and QImode just don't make sense on this CPU.
|
3259 |
|
|
+ */
|
3260 |
|
|
+#define PROMOTE_MODE(M,U,T) if ((GET_MODE_CLASS(M)==MODE_INT)&&(GET_MODE_SIZE(M)<2)) (M)=SImode;
|
3261 |
|
|
+
|
3262 |
|
|
+// TARGET_PROMOTE_FUNCTION_MODE
|
3263 |
|
|
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
|
3264 |
|
|
+ * stack, in bits. All stack parameters receive at least this much alignment
|
3265 |
|
|
+ * regardless of data type. On most machines, this is the same as the size of
|
3266 |
|
|
+ * an integer.
|
3267 |
|
|
+ */
|
3268 |
|
|
+#define PARM_BOUNDARY 32
|
3269 |
|
|
+
|
3270 |
|
|
+/* STACK_BOUNDARY ... Define this macro to the minimum alignment enforced by
|
3271 |
|
|
+ * hardware for the stack pointer on this machine. The definition is a C
|
3272 |
|
|
+ * expression for the desired alignment (measured in bits). This value is used
|
3273 |
|
|
+ * as a default if PREFERRED_STACK_BOUNDARY is not defined. On most machines,
|
3274 |
|
|
+ * this should be the same as PARM_BOUNDARY.
|
3275 |
|
|
+ */
|
3276 |
|
|
+#define STACK_BOUNDARY PARM_BOUNDARY
|
3277 |
|
|
+
|
3278 |
|
|
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */
|
3279 |
127 |
dgisselq |
+#define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
|
3280 |
102 |
dgisselq |
+
|
3281 |
127 |
dgisselq |
+/* INCOMING_STACK_BOUNDARY ... Define this macro if the incoming stack boundary
|
3282 |
|
|
+ * may be different from PREFERRED_STACK_BOUNDARY. This macro must evaluate
|
3283 |
|
|
+ * to a value equal to or larger than STACK_BOUNDARY.
|
3284 |
102 |
dgisselq |
+ */
|
3285 |
127 |
dgisselq |
+#define INCOMING_STACK_BOUNDARY STACK_BOUNDARY
|
3286 |
102 |
dgisselq |
+
|
3287 |
|
|
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits.
|
3288 |
|
|
+ */
|
3289 |
|
|
+#define FUNCTION_BOUNDARY 32
|
3290 |
|
|
+
|
3291 |
|
|
+/* BIGGEST_ALIGNMENT ... Biggest alignment that any data type can require on
|
3292 |
|
|
+ * this machine, in bits. Note that this is not the biggest alignment that is
|
3293 |
|
|
+ * supported, just the biggest alignment that, when violated, may cause a fault.
|
3294 |
|
|
+ */
|
3295 |
|
|
+#define BIGGEST_ALIGNMENT 32
|
3296 |
|
|
+
|
3297 |
127 |
dgisselq |
+/* MALLOC_ABI_ALIGNMENT
|
3298 |
|
|
+ */
|
3299 |
|
|
+
|
3300 |
|
|
+/* ATTRIBUTE_ALIGNED_VALUE
|
3301 |
|
|
+ */
|
3302 |
|
|
+
|
3303 |
102 |
dgisselq |
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be
|
3304 |
|
|
+ * given to an object that can be referenced in one operation, without
|
3305 |
|
|
+ * disturbing any nearby object. Normally, this is BITS_PER_UNIT, but may be
|
3306 |
|
|
+ * larger on machines that don't have byte or halfword store operations.
|
3307 |
|
|
+ */
|
3308 |
|
|
+#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT
|
3309 |
|
|
+
|
3310 |
127 |
dgisselq |
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
|
3311 |
|
|
+ * field can require on this machine, in bits. If defined, this overrides
|
3312 |
|
|
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
|
3313 |
|
|
+ * alignment has been set by the __attribute__((aligned(n))) construct.
|
3314 |
|
|
+ */
|
3315 |
|
|
+#define BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT
|
3316 |
|
|
+
|
3317 |
|
|
+/* ADJUST_FIELD_ALIGN
|
3318 |
|
|
+ */
|
3319 |
|
|
+#define ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
|
3320 |
|
|
+
|
3321 |
|
|
+/* MAX_STACK_ALIGNMENT
|
3322 |
|
|
+ */
|
3323 |
|
|
+#define MAX_STACK_ALIGNMENT BITS_PER_WORD
|
3324 |
|
|
+
|
3325 |
|
|
+/* MAX_OFILE_ALIGNMENT
|
3326 |
|
|
+ */
|
3327 |
|
|
+
|
3328 |
|
|
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
|
3329 |
|
|
+ * the alignment for a variable in the static store. TYPE is the data type, and
|
3330 |
|
|
+ * BASIC-ALIGN is the alignment that the object would ordinarily have. The
|
3331 |
|
|
+ * value of this macro is used instead of that alignment to align the object.
|
3332 |
|
|
+ *
|
3333 |
|
|
+ * If this macro is not defined, then BASIC-ALIGN is used.
|
3334 |
|
|
+ *
|
3335 |
|
|
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is
|
3336 |
|
|
+ * broken. So we define it to be our fastest alignment, or 32-bits.
|
3337 |
|
|
+ */
|
3338 |
|
|
+#define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD
|
3339 |
|
|
+
|
3340 |
|
|
+
|
3341 |
|
|
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
|
3342 |
|
|
+ */
|
3343 |
|
|
+
|
3344 |
|
|
+/* CONSTANT_ALIGNMENT(CONST, BASIC-ALIGN) ... If defined, a C expression to
|
3345 |
|
|
+ * compute the alignment given to a constant that is being placed in memory.
|
3346 |
|
|
+ * CONST is the constant and BASIC-ALIGN is the alignment that the object
|
3347 |
|
|
+ * would ordinarily have. The value of this macro is used instead of that
|
3348 |
|
|
+ * alignment to align the object.
|
3349 |
|
|
+ *
|
3350 |
|
|
+ * If this macro is not defined, then BASIC-ALIGN is used.
|
3351 |
|
|
+ *
|
3352 |
|
|
+ * ZipCPU -- in hindsiht, if this macro is not defined then the compiler is
|
3353 |
|
|
+ * broken. We'll define it as above.
|
3354 |
|
|
+ *
|
3355 |
|
|
+ */
|
3356 |
|
|
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD
|
3357 |
|
|
+
|
3358 |
|
|
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
|
3359 |
|
|
+ */
|
3360 |
|
|
+#define LOCAL_ALIGNMENT(TYP,ALIGN) BITS_PER_WORD
|
3361 |
|
|
+
|
3362 |
|
|
+/* TARGET_VECTOR_ALIGNMENT
|
3363 |
|
|
+ */
|
3364 |
|
|
+
|
3365 |
|
|
+/* STACK_SLOT_ALIGNMENT
|
3366 |
|
|
+ */
|
3367 |
|
|
+#define STACK_SLOT_ALIGNMENT(T,M,B) BITS_PER_WORD
|
3368 |
|
|
+
|
3369 |
|
|
+/* LOCAL_DECL_ALIGNMEN(DECL)
|
3370 |
|
|
+ */
|
3371 |
|
|
+#define LOCAL_DECL_ALIGNMENT(DECL) BITS_PER_WORD
|
3372 |
|
|
+
|
3373 |
|
|
+/* MINIMUM_ALIGNMENT
|
3374 |
|
|
+ */
|
3375 |
|
|
+#define MINIMUM_ALIGNMENT(EXP,MOD,ALIGN) BITS_PER_WORD
|
3376 |
|
|
+
|
3377 |
|
|
+/* EMPTY_FIELD_BOUNDARY
|
3378 |
|
|
+ * Alignment of field after 'int : 0' in a structure.
|
3379 |
|
|
+ */
|
3380 |
|
|
+#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
|
3381 |
|
|
+
|
3382 |
|
|
+/* STRUCTURE_SIE_BOUNDARY
|
3383 |
|
|
+ * ZipCPU -- Every structures size must be a multiple of 32-bits.
|
3384 |
|
|
+ */
|
3385 |
|
|
+#define STRUCTURE_SIZE_BOUNDARY BITS_PER_WORD
|
3386 |
|
|
+
|
3387 |
102 |
dgisselq |
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
|
3388 |
|
|
+ * fail to work when given unaligned data. If instructions will merely go
|
3389 |
|
|
+ * slower in that case, define this macro as 0.
|
3390 |
125 |
dgisselq |
+ *
|
3391 |
|
|
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
|
3392 |
|
|
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
|
3393 |
|
|
+ * is easy, then there really are no instructions that will ever fail.
|
3394 |
102 |
dgisselq |
+ */
|
3395 |
125 |
dgisselq |
+#define STRICT_ALIGNMENT 0
|
3396 |
102 |
dgisselq |
+
|
3397 |
127 |
dgisselq |
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
|
3398 |
|
|
+ * other C compilers handle alignment of bit-fields and the structures that
|
3399 |
|
|
+ * contain them.
|
3400 |
|
|
+ *
|
3401 |
|
|
+ * The behavior is that the type written for a named bit-field (int, short, or
|
3402 |
|
|
+ * other integer type) imposes an alignment for the entire structure, as if the
|
3403 |
|
|
+ * structure really did contain an ordinary field of that type. In addition,
|
3404 |
|
|
+ * the bit-field is placed within the structure so that it would fit within
|
3405 |
|
|
+ * such a field, not crossing a boundary for it.
|
3406 |
|
|
+ *
|
3407 |
|
|
+ * Thus, no most machines, a named bit-field whose type is written as int would
|
3408 |
|
|
+ * not cross a four-byte boundary, and would force four-byte alignment for the
|
3409 |
|
|
+ * whole structure. (The alignment used may not be four bytes; it is controlled
|
3410 |
|
|
+ * by other alignment parameters.)
|
3411 |
|
|
+ *
|
3412 |
|
|
+ * An unnamed bit-field will not affect the alignment of the containing
|
3413 |
|
|
+ * structure.
|
3414 |
|
|
+ *
|
3415 |
|
|
+ * If the macro is defined, its definition should be a C expression, a non
|
3416 |
|
|
+ * zero value for the expression enables this behavior.
|
3417 |
|
|
+ * Look at the fundamental type that is used for a bit-field and use that to
|
3418 |
|
|
+ * impose alignment on the enclosing structure. struct s{int a:8}; should
|
3419 |
|
|
+ * have the same alignment as 'int', not 'char'.
|
3420 |
|
|
+ */
|
3421 |
|
|
+#undef PCC_BITFIELD_TYPE_MATTERS
|
3422 |
|
|
+#define PCC_BITFIELD_TYPE_MATTERS 0
|
3423 |
|
|
+
|
3424 |
102 |
dgisselq |
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the
|
3425 |
|
|
+ * largest integer machine mode that should actually be used. All integer
|
3426 |
|
|
+ * machine modes of this size or smaller can be used for structures and unions
|
3427 |
|
|
+ * with the appropriate sizes. If this macro is undefined,
|
3428 |
|
|
+ * GET_MODE_BITSIZE(DImode) is assumed.
|
3429 |
|
|
+ *
|
3430 |
|
|
+ * ZipCPU ... Get_MOD_BITSIZE(DImode) will be 64, and this is really not the
|
3431 |
|
|
+ * size on bits of the largest integer machine mode. However, that's the case
|
3432 |
|
|
+ * with most DI implementations: A long is two words, spliced together. We'd
|
3433 |
|
|
+ * like to support that eventually, but we need to get there. Hence, let's use
|
3434 |
|
|
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
|
3435 |
|
|
+ */
|
3436 |
|
|
+#if (ZIP_HAS_DI != 0)
|
3437 |
|
|
+#define MAX_FIXED_MODE_SIZE 64
|
3438 |
|
|
+#else
|
3439 |
|
|
+#define MAX_FIXED_MODE_SIZE 32
|
3440 |
|
|
+#endif
|
3441 |
|
|
+
|
3442 |
|
|
+
|
3443 |
|
|
+/* 17.06 Layout of Source Language Data Types */
|
3444 |
|
|
+
|
3445 |
|
|
+#undef CHAR_TYPE_SIZE
|
3446 |
|
|
+#undef SHORT_TYPE_SIZE
|
3447 |
|
|
+#undef INT_TYPE_SIZE
|
3448 |
|
|
+#undef LONG_TYPE_SIZE
|
3449 |
|
|
+#undef LONG_LONG_TYPE_SIZE
|
3450 |
|
|
+//
|
3451 |
|
|
+#define CHAR_TYPE_SIZE 32
|
3452 |
|
|
+#define SHORT_TYPE_SIZE 32
|
3453 |
|
|
+#define INT_TYPE_SIZE 32
|
3454 |
|
|
+#define LONG_TYPE_SIZE 32
|
3455 |
|
|
+#define LONG_LONG_TYPE_SIZE 64
|
3456 |
|
|
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
|
3457 |
|
|
+#undef FLOAT_TYPE_SIZE
|
3458 |
|
|
+#undef DOUBLE_TYPE_SIZE
|
3459 |
|
|
+#undef LONG_DOUBLE_TYPE_SIZE
|
3460 |
|
|
+#define FLOAT_TYPE_SIZE 32
|
3461 |
|
|
+#define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE // Zip CPU doesn't support dbls
|
3462 |
|
|
+#define LONG_DOUBLE_TYPE_SIZE 64 // This'll need to be done via emulation
|
3463 |
|
|
+// SHORT_FRAC_TYPE_SIZE
|
3464 |
|
|
+// LONG_FFRACT_TYPE_SIZE
|
3465 |
|
|
+// LONG_LONG_FRACT_TIME_SIZE
|
3466 |
|
|
+#undef SHORT_ACCUM_TYPE_SIZE
|
3467 |
|
|
+#undef ACCUM_TYPE_SIZE
|
3468 |
|
|
+#undef LONG_ACCUM_TYPE_SIZE
|
3469 |
|
|
+#define SHORT_ACCUM_TYPE_SIZE SHORT_TYPE_SIZE
|
3470 |
|
|
+#define ACCUM_TYPE_SIZE INT_TYPE_SIZE
|
3471 |
|
|
+#define LONG_ACCUM_TYPE_SIZE LONG_TYPE_SIZE
|
3472 |
|
|
+
|
3473 |
|
|
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
|
3474 |
|
|
+ * hook and should be defined if that hook is overriden to be true. It causes
|
3475 |
|
|
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
|
3476 |
|
|
+ * rather than the default __. A port which uses this macro should also arrange
|
3477 |
|
|
+ * to use t-gnu-prefix in the libgcc config.host.
|
3478 |
|
|
+ *
|
3479 |
|
|
+ * ZipCPU -- I see no reason to define and therefore change this behavior.
|
3480 |
|
|
+ */
|
3481 |
|
|
+
|
3482 |
|
|
+/* TARGET_FLT_EVAL_METHOD ... A C expression for the value for FLT_EVAL_METHOD
|
3483 |
|
|
+ * in float.h,, assuming, if applicable, that the floating-point control word
|
3484 |
|
|
+ * is in its default state. If you do not define this macro the value of
|
3485 |
|
|
+ * FLT_EVAL_METHOD will be zero.
|
3486 |
|
|
+ *
|
3487 |
|
|
+ * ZipCPU --- ???
|
3488 |
|
|
+ */
|
3489 |
|
|
+
|
3490 |
|
|
+/* WIDEST_HARDWARE_FP_SIZE ... A C expression for the size in bits of the widest
|
3491 |
|
|
+ * floating-point format supported by the hardware. If you define this macro,
|
3492 |
|
|
+ * you must specify a value less than or equal to the value of LONG_DOUBLE_...
|
3493 |
|
|
+ * If you do not define this macro, the value of LONG_DOUBLE_TYPE_SIZE is the
|
3494 |
|
|
+ * default.
|
3495 |
|
|
+ *
|
3496 |
|
|
+ * ZipCPU supports 32-bit IEEE floats--IF THE SUPPORT IS COMPILED IN! This
|
3497 |
|
|
+ * really needs to be determined, then, based upon a compile time parameter
|
3498 |
|
|
+ * where the one compiling the code states whether or not the H/W even has
|
3499 |
|
|
+ * floating point support.
|
3500 |
|
|
+ *
|
3501 |
|
|
+ * For now, we'll assume it does--but once we implement GCC parameters, we'll
|
3502 |
|
|
+ * need to change this.
|
3503 |
|
|
+ */
|
3504 |
|
|
+#undef WIDEST_HARDWARE_FP_SIZE
|
3505 |
|
|
+// #warning "Definition needs to change if no FPU present"
|
3506 |
|
|
+#define WIDEST_HARDWARE_FP_SIZE FLOAT_TYPE_SIZE
|
3507 |
|
|
+
|
3508 |
|
|
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
|
3509 |
|
|
+ * whether the type char should be signed or unsigned by default. The user
|
3510 |
|
|
+ * can always override this default with the options -fsigned-char and
|
3511 |
|
|
+ * -funsigned-char.
|
3512 |
|
|
+ *
|
3513 |
|
|
+ * ZipCPU--let's go with the default behavior.
|
3514 |
|
|
+ */
|
3515 |
|
|
+#define DEFAULT_SIGNED_CHAR 1
|
3516 |
|
|
+
|
3517 |
|
|
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
|
3518 |
103 |
dgisselq |
+ * the compiler should give an enum type only as many bytes as it takes to
|
3519 |
102 |
dgisselq |
+ * represent the range of possible values of that type. It should return
|
3520 |
|
|
+ * false if all enum types should be allocated like int.
|
3521 |
|
|
+ *
|
3522 |
|
|
+ * The default is to return false. This is what the ZipCPU needs, so we won't
|
3523 |
|
|
+ * override it.
|
3524 |
|
|
+ */
|
3525 |
|
|
+
|
3526 |
|
|
+/* SIZE_TYPE ... A C expression for a string describing the name of the data
|
3527 |
|
|
+ * type to use for size values. The typedef name size_t is defined using the
|
3528 |
|
|
+ * contents of the string.
|
3529 |
|
|
+ *
|
3530 |
|
|
+ * If you don't define this macro, the default is "long unsigned int". Since
|
3531 |
|
|
+ * on the ZipCPU this is a 32-bit number, and all ZipCPU values are 32-bits,
|
3532 |
|
|
+ * the default seems perfect for us.
|
3533 |
|
|
+ */
|
3534 |
|
|
+#define SIZE_TYPE "unsigned int"
|
3535 |
|
|
+
|
3536 |
|
|
+/* SIZETYPE ... GCC defines internal types () for expressions dealing with size.
|
3537 |
|
|
+ * This macro is a C expression for a string describing the name of the data
|
3538 |
|
|
+ * type from which the precision of sizetype is extracted. The string has the
|
3539 |
|
|
+ * same restrictions as SIZE_TYPE string. If you don't define this macro, the
|
3540 |
|
|
+ * default is SIZE_TYPE --- which seems good enough for us.
|
3541 |
|
|
+ */
|
3542 |
|
|
+
|
3543 |
|
|
+/* PTRDIFF_TYPE ... A C expression for a string describing the name of the data
|
3544 |
127 |
dgisselq |
+ * type to use for the result of subtracting two pointers. The typedef name
|
3545 |
102 |
dgisselq |
+ * ptrdiff_t is defined using the contents of the string. See SIZE_TYPE for
|
3546 |
|
|
+ * more information.
|
3547 |
|
|
+ *
|
3548 |
|
|
+ * The default is "long int" which for the ZipCPU is 32-bits---still good enough
|
3549 |
|
|
+ * for us.
|
3550 |
|
|
+ */
|
3551 |
|
|
+#define PTRDIFF_TYPE "int"
|
3552 |
|
|
+
|
3553 |
|
|
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
|
3554 |
|
|
+ * type to use for wide characters. The typedef name wchar_t is defined using
|
3555 |
|
|
+ * the contents of the string. If you don't define this macro, the default is
|
3556 |
|
|
+ * 'int'--good enough for ZipCPU.
|
3557 |
|
|
+ */
|
3558 |
|
|
+
|
3559 |
|
|
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
|
3560 |
|
|
+ * wide characters. This is used in cpp, which cannot make use of WCHAR_TYPE.
|
3561 |
|
|
+ */
|
3562 |
|
|
+#undef WCHAR_TYPE_SIZE
|
3563 |
|
|
+#define WCHAR_TYPE_SIZE 32
|
3564 |
|
|
+
|
3565 |
|
|
+/* WINT_TYPE ... A C expression for a string describing the name of the data
|
3566 |
|
|
+ * type to use for wide characters passed to printf and returned from getwc.
|
3567 |
|
|
+ * The typedef name wint_t is defined using the contents of the string. See
|
3568 |
|
|
+ *
|
3569 |
103 |
dgisselq |
+ * ZipCPU -- If you don't define this macro, the default is "unsigned int"--also
|
3570 |
|
|
+ * best for us again.
|
3571 |
102 |
dgisselq |
+ */
|
3572 |
|
|
+
|
3573 |
|
|
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
|
3574 |
|
|
+ * data type that can represent any value of any standard or extended signed
|
3575 |
|
|
+ * integer type. The typedef name intmax_t is defined using the contents of
|
3576 |
|
|
+ * the string.
|
3577 |
|
|
+ *
|
3578 |
|
|
+ * If you don't define this macro, the default is the first of "int", "long int"
|
3579 |
|
|
+ * or "long long int" that has as much precision as "long long int".
|
3580 |
|
|
+ */
|
3581 |
|
|
+
|
3582 |
|
|
+/* UINTMAX_TYPE ... same as INTMAX_TYPE, but for unsigned
|
3583 |
|
|
+ */
|
3584 |
|
|
+
|
3585 |
|
|
+#undef SIG_ATOMIC_TYPE
|
3586 |
|
|
+#if (ZIP_ATOMIC != 0)
|
3587 |
|
|
+#define SIG_ATOMIC_TYPE "int"
|
3588 |
|
|
+#else
|
3589 |
|
|
+#define SIG_ATOMIC_TYPE NULL // We have no atomic types, but registers
|
3590 |
|
|
+#endif
|
3591 |
|
|
+#undef INT8_TYPE
|
3592 |
|
|
+#define INT8_TYPE NULL // We have no 8-bit integer type
|
3593 |
|
|
+#undef INT16_TYPE
|
3594 |
|
|
+#define INT16_TYPE NULL
|
3595 |
|
|
+#undef INT32_TYPE
|
3596 |
|
|
+#define INT32_TYPE "int"
|
3597 |
|
|
+#undef UINT8_TYPE
|
3598 |
|
|
+#define UINT8_TYPE NULL
|
3599 |
|
|
+#undef UINT16_TYPE
|
3600 |
|
|
+#define UINT16_TYPE NULL
|
3601 |
|
|
+#undef UINT32_TYPE
|
3602 |
|
|
+#define UINT32_TYPE "unsigned int"
|
3603 |
|
|
+#undef INT_LEAST8_TYPE
|
3604 |
|
|
+#define INT_LEAST8_TYPE "int"
|
3605 |
|
|
+#undef INT_LEAST16_TYPE
|
3606 |
|
|
+#define INT_LEAST16_TYPE "int"
|
3607 |
|
|
+#undef INT_LEAST32_TYPE
|
3608 |
|
|
+#define INT_LEAST32_TYPE "int"
|
3609 |
|
|
+#undef UINT_LEAST8_TYPE
|
3610 |
|
|
+#define UINT_LEAST8_TYPE "unsigned int"
|
3611 |
|
|
+#undef UINT_LEAST16_TYPE
|
3612 |
|
|
+#define UINT_LEAST16_TYPE "unsigned int"
|
3613 |
|
|
+#undef UINT_LEAST32_TYPE
|
3614 |
|
|
+#define UINT_LEAST32_TYPE "unsigned int"
|
3615 |
|
|
+#undef INT_FAST8_TYPE
|
3616 |
|
|
+#define INT_FAST8_TYPE "int"
|
3617 |
|
|
+#undef INT_FAST16_TYPE
|
3618 |
|
|
+#define INT_FAST16_TYPE "int"
|
3619 |
|
|
+#undef INT_FAST32_TYPE
|
3620 |
|
|
+#define INT_FAST32_TYPE "int"
|
3621 |
|
|
+#undef UINT_FAST8_TYPE
|
3622 |
|
|
+#define UINT_FAST8_TYPE "unsigned int"
|
3623 |
|
|
+#undef UINT_FAST16_TYPE
|
3624 |
|
|
+#define UINT_FAST16_TYPE "unsigned int"
|
3625 |
|
|
+#undef UINT_FAST32_TYPE
|
3626 |
|
|
+#define UINT_FAST32_TYPE "unsigned int"
|
3627 |
|
|
+#undef INTPTR_TYPE
|
3628 |
|
|
+#define INTPTR_TYPE "unsigned int"
|
3629 |
|
|
+#undef UINTPTR_TYPE
|
3630 |
|
|
+#define UINTPTR_TYPE "unsigned int"
|
3631 |
|
|
+
|
3632 |
|
|
+#undef INT64_TYPE
|
3633 |
|
|
+#undef UINT64_TYPE
|
3634 |
|
|
+#undef INT_LEAST64_TYPE
|
3635 |
|
|
+#undef UINT_LEAST64_TYPE
|
3636 |
|
|
+#undef INT_FAST64_TYPE
|
3637 |
|
|
+#undef UINT_FAST64_TYPE
|
3638 |
|
|
+
|
3639 |
|
|
+#if (ZIP_HAS_DI != 0)
|
3640 |
|
|
+#define INT64_TYPE "long int"
|
3641 |
|
|
+#define UINT64_TYPE "long unsigned int"
|
3642 |
|
|
+#define INT_LEAST64_TYPE "long int"
|
3643 |
|
|
+#define UINT_LEAST64_TYPE "long unsigned int"
|
3644 |
|
|
+#define INT_FAST64_TYPE "long int"
|
3645 |
|
|
+#define UINT_FAST64_TYPE "long unsigned int"
|
3646 |
|
|
+#else
|
3647 |
|
|
+#define INT64_TYPE NULL
|
3648 |
|
|
+#define UINT64_TYPE NULL
|
3649 |
|
|
+#define INT_LEAST64_TYPE NULL
|
3650 |
|
|
+#define UINT_LEAST64_TYPE NULL
|
3651 |
|
|
+#define INT_FAST64_TYPE NULL
|
3652 |
|
|
+#define UINT_FAST64_TYPE NULL
|
3653 |
|
|
+#endif
|
3654 |
|
|
+
|
3655 |
|
|
+#define TARGET_PTRMEMFUNC_VBI_LOCATION ptrmemfunc_vbit_in_pfn
|
3656 |
|
|
+
|
3657 |
|
|
+
|
3658 |
|
|
+/* 17.07 Register Usage / Register definitions */
|
3659 |
|
|
+
|
3660 |
|
|
+/* FIRST_PSEUDO_REGISTER ... Number of hardware registers known to the compiler.
|
3661 |
|
|
+ * They receive numbers 0 through FIRST_PSEUDO_REGISTER-1; thus the first
|
3662 |
|
|
+ * pseudo register's numbrer really is assigned the number
|
3663 |
|
|
+ * FIRST_PSEUDO_REGISTER.
|
3664 |
|
|
+ *
|
3665 |
|
|
+ * ZipCPU---There are 16 registers in the ZipCPU, numbered 0-15 with the CC
|
3666 |
171 |
dgisselq |
+ * and PC register being numbered 14 and 15 respectively. The ZipCPU has
|
3667 |
|
|
+ * another 16 registers, identical to the first, but user mode registers. These
|
3668 |
|
|
+ * are number the same as the first (0-15) in user mode, but numbered (16-31)
|
3669 |
|
|
+ * in supervisor mode. In addition, we create a pretend argument pointer
|
3670 |
|
|
+ * register, zip_AP_PSEUDO, to refer to our arguments. This final register,
|
3671 |
|
|
+ * although it gets a valid number, will be eliminated in optimization.
|
3672 |
102 |
dgisselq |
+ */
|
3673 |
171 |
dgisselq |
+#define FIRST_PSEUDO_REGISTER (zip_AP_PSEUDO+1)
|
3674 |
102 |
dgisselq |
+
|
3675 |
|
|
+/* FIXED_REGISTERS ... An initializer that says which registers are used for
|
3676 |
|
|
+ * fixed purposes all throughout the compiled code and are therefore not
|
3677 |
|
|
+ * available for general allocation. These would include the stack pointer, the
|
3678 |
|
|
+ * frame pointer (except on machines where that can be used as a general
|
3679 |
|
|
+ * register when no frame pointer is needed), the program counter on machines
|
3680 |
|
|
+ * where that is considered one of the addressable registers, and any other
|
3681 |
|
|
+ * numbered register with a standard use.
|
3682 |
|
|
+ *
|
3683 |
|
|
+ * This information is expressed as a sequence of numbers, separated by commas,
|
3684 |
|
|
+ * and surrounded by braces. The nth number is 1 if register n is fixed, 0
|
3685 |
|
|
+ * otherwise.
|
3686 |
|
|
+ *
|
3687 |
|
|
+ * For the Zip CPU, we have three fixed registers that are not available for
|
3688 |
|
|
+ * general allocation:
|
3689 |
|
|
+ *
|
3690 |
|
|
+ * SP The stack pointer
|
3691 |
|
|
+ * CC The condition codes and CPU state register
|
3692 |
|
|
+ * PC The program counter
|
3693 |
|
|
+ *
|
3694 |
|
|
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset
|
3695 |
|
|
+ * table pointer) are registers that we hope will not be so fixed.
|
3696 |
171 |
dgisselq |
+ *
|
3697 |
|
|
+ * Okay, just updated this process. We now have more registers that are not
|
3698 |
|
|
+ * available for general allocation:
|
3699 |
|
|
+ * uR0-uPC User registers
|
3700 |
|
|
+ * PSEUDO-AP The pseudo arg pointer
|
3701 |
102 |
dgisselq |
+ */
|
3702 |
171 |
dgisselq |
+#define FIXED_REGISTERS { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1 }
|
3703 |
102 |
dgisselq |
+
|
3704 |
|
|
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register
|
3705 |
|
|
+ * that is clobbered (in general) by function calls as well as for fixed
|
3706 |
|
|
+ * registers. This macro therefore identifies the registers that are not
|
3707 |
|
|
+ * available for general allocation of values that must live across function
|
3708 |
|
|
+ * calls.
|
3709 |
|
|
+ *
|
3710 |
|
|
+ * If a register has 0 in CALL_USED_REGISTERS, the compiler automatically saves
|
3711 |
|
|
+ * it on function entry and restores it on function exit, if the register is
|
3712 |
|
|
+ * used within the function.
|
3713 |
|
|
+ *
|
3714 |
|
|
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any
|
3715 |
|
|
+ * register above R5.
|
3716 |
|
|
+ */
|
3717 |
171 |
dgisselq |
+#define CALL_USED_REGISTERS { 0,1,1,1, 1,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1 }
|
3718 |
102 |
dgisselq |
+
|
3719 |
|
|
+/* CALL_REALLY_USED_REGISTERS ... optional macro that, if not defined, defaults
|
3720 |
|
|
+ * to the value of CALL_USED_REGISTERS.
|
3721 |
|
|
+ */
|
3722 |
|
|
+
|
3723 |
|
|
+/* HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) ... A C expression that is nonzero
|
3724 |
|
|
+ * if it is not permissible to store a value of mode MODE in hard register REGNO
|
3725 |
|
|
+ * across a call without some part of it being clobbbered. For most machines,
|
3726 |
|
|
+ * this macro need not be defined. It is only required for machines that do
|
3727 |
103 |
dgisselq |
+ * not preserve the entire contents of a register across a call.
|
3728 |
102 |
dgisselq |
+ *
|
3729 |
127 |
dgisselq |
+ * ZipCPU--Always preserves the entire contents of those registers that are
|
3730 |
|
|
+ * preserved across calls, so this shouldnt need to be defined.
|
3731 |
102 |
dgisselq |
+ */
|
3732 |
127 |
dgisselq |
+// #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) (REGNO==0)
|
3733 |
102 |
dgisselq |
+
|
3734 |
|
|
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally
|
3735 |
|
|
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and
|
3736 |
|
|
+ * reg_class_contents, to take into account any dependence of these register
|
3737 |
|
|
+ * sets on target flags. The first three of these are of type char[]
|
3738 |
|
|
+ * (interpreted as Boolean vectors). global_regs is a const char *[] and
|
3739 |
|
|
+ * reg_class_contents is a HARD_REG_SET. Before the macro is called,
|
3740 |
|
|
+ * fixed_regs, call_used_regs, reg_class_contents, and reg_names have been
|
3741 |
|
|
+ * initialized from FIXED_REGISTERS, CALL_USED_REGISTERS, REG_CLASS_CONTENTS,
|
3742 |
|
|
+ * and REGISTER_NAMES, respectively. global_regs has been cleared, and any
|
3743 |
|
|
+ * -ffixed-reg, -fcall-used-reg, and -fcall-saved-reg command options have been
|
3744 |
|
|
+ * applied.
|
3745 |
|
|
+ *
|
3746 |
171 |
dgisselq |
+ * ZipCPU -- I may need to return and define this depending upon how the
|
3747 |
|
|
+ * GBL register allocation goes. But for now, we'll leave this at its default
|
3748 |
102 |
dgisselq |
+ * value.
|
3749 |
|
|
+ */
|
3750 |
|
|
+// #warning "Revisit me after FP and GBL allocation"
|
3751 |
|
|
+
|
3752 |
|
|
+/* INCOMING_REGNO(out) ... Define this macro if the target machine has register
|
3753 |
|
|
+ * windows. ...
|
3754 |
|
|
+ *
|
3755 |
|
|
+ * Zip CPU has no register windows.
|
3756 |
|
|
+ */
|
3757 |
|
|
+
|
3758 |
|
|
+/* OUTGOING_REGNO ... same thing.
|
3759 |
171 |
dgisselq |
+ * LOCAL_REGNO ... same thing.
|
3760 |
102 |
dgisselq |
+ */
|
3761 |
|
|
+
|
3762 |
|
|
+/* PC_REGNUM ... If the program counter has a register number, define this as
|
3763 |
|
|
+ * that register number. Otherwise do not define it.
|
3764 |
|
|
+ */
|
3765 |
|
|
+#define PC_REGNUM zip_PC
|
3766 |
|
|
+
|
3767 |
|
|
+
|
3768 |
|
|
+/* REG_ALLOC_ORDER ... If defined, an initializer for a vector of integers,
|
3769 |
|
|
+ * containing the number of hard registers in the order in which GCC should
|
3770 |
|
|
+ * prefer to use them (from most preferred to least.
|
3771 |
|
|
+ *
|
3772 |
103 |
dgisselq |
+ * If this macro is not defined, registers are used lowest numbered first (all
|
3773 |
102 |
dgisselq |
+ * else being equal).
|
3774 |
|
|
+ *
|
3775 |
|
|
+ * Since the default is the ZipCPU desired case, we won't define this here.
|
3776 |
|
|
+ */
|
3777 |
|
|
+
|
3778 |
|
|
+/* ADJUST_REG_ALLOC_ORDER ... on most machines it is not necessary to define
|
3779 |
|
|
+ * this macro, so we won't either.
|
3780 |
|
|
+ */
|
3781 |
|
|
+
|
3782 |
|
|
+/* HONOR_REG_ALLOC_ORDER ...
|
3783 |
|
|
+ */
|
3784 |
|
|
+
|
3785 |
|
|
+/* HONOR_REG_ALLOC_ORDER ... on most machines it is not necessary to define
|
3786 |
|
|
+ * this macro, so we won't either.
|
3787 |
|
|
+ */
|
3788 |
|
|
+
|
3789 |
|
|
+/* HARD_REGNO_NREGS(REGNO, MODE) ... A C expression for the number of
|
3790 |
|
|
+ * consecutive hard registers, starting at register number REGNO, required to
|
3791 |
|
|
+ * hold a value of mode MODE.
|
3792 |
|
|
+ *
|
3793 |
|
|
+ * On a machine where all registers are exactly one word, a suitable definition
|
3794 |
|
|
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
|
3795 |
|
|
+ *
|
3796 |
|
|
+ * On ZipCPU, we might do
|
3797 |
|
|
+ * ((((MODE)==DImode)||((MODE)==DFmode))?2:1)
|
3798 |
|
|
+ * but I think the default (above) code should work as well. Hence, let's stick
|
3799 |
|
|
+ * with the default, lest someone try to create larger modes (TImode, OImode,
|
3800 |
|
|
+ * XImode) and expect us to follow them properly some how.
|
3801 |
|
|
+ *
|
3802 |
|
|
+ * Okay, now in hind sight, we know that the default doesn't work for our
|
3803 |
|
|
+ * architecture, since GET_MODE_SIZE(SImode)=4, not 1. Thus, let's rearrange
|
3804 |
|
|
+ * this expression to work in bits rather than in bytes and we'll know more
|
3805 |
|
|
+ * of what we are doing.
|
3806 |
|
|
+ */
|
3807 |
|
|
+#undef HARD_REGNO_NREGS
|
3808 |
|
|
+#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
|
3809 |
|
|
+ / (UNITS_PER_WORD))
|
3810 |
|
|
+
|
3811 |
|
|
+/* HARD_REGNO_NREGS_HAS_PADDING(REGNO,MODE) ... A C expression that is nonzero
|
3812 |
|
|
+ * if a value of mode MODE, stored in memory, ends with padding that causes it
|
3813 |
|
|
+ * to take up more space than in registers starting at register number REGNO
|
3814 |
|
|
+ * (as determined by multiplying GCC's notion of the size of the register when
|
3815 |
|
|
+ * containing this mode by the number of registers returned by HARD_REGNO_NREGS)
|
3816 |
|
|
+ * By default this is zero.
|
3817 |
|
|
+ *
|
3818 |
|
|
+ * Zip CPU --- The default looks good enough to me.
|
3819 |
|
|
+ */
|
3820 |
|
|
+
|
3821 |
|
|
+/* HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE)
|
3822 |
|
|
+ *
|
3823 |
|
|
+ * ZipCPU ---
|
3824 |
|
|
+ */
|
3825 |
|
|
+
|
3826 |
|
|
+/* REGMODE_NATURAL_SIZE(MODE) -- Define this macro if the natural size of
|
3827 |
|
|
+ * registers that hold values of mode mode is not the word size. It is a C
|
3828 |
|
|
+ * expression that should give the natural size in bytes for the specified mode.
|
3829 |
|
|
+ * It is used by the register allocator to try to optimize its results.
|
3830 |
|
|
+ *
|
3831 |
|
|
+ * ZipCPU ---
|
3832 |
|
|
+ */
|
3833 |
|
|
+// #define REGMODE_NATURAL_SIZE(MODE) (((MODE)==DImode)?2:1)
|
3834 |
|
|
+
|
3835 |
|
|
+/* HARD_REGNO_MODE_OK ... A C expression that is nonzero if it is permissible
|
3836 |
103 |
dgisselq |
+ * to store a value of mode MODE in a hard register number REGNO (or in several
|
3837 |
102 |
dgisselq |
+ * registers starting with that one). For a machine where all registers are
|
3838 |
|
|
+ * equivalent, a suitable definition is '1'. You need not include code to check
|
3839 |
|
|
+ * for the numbers of fixed registers, because the allocation mechanism
|
3840 |
|
|
+ * considered them to be always occupied.
|
3841 |
|
|
+ *
|
3842 |
|
|
+ * ZipCPU --- As long as you are already avoiding the fixed registers, the
|
3843 |
|
|
+ * suitable default definition mentioned above should be sufficient.
|
3844 |
|
|
+ */
|
3845 |
|
|
+#undef HARD_REGNO_MODE_OK
|
3846 |
103 |
dgisselq |
+#define HARD_REGNO_MODE_OK(R,M) (R<zip_CC)
|
3847 |
102 |
dgisselq |
+
|
3848 |
|
|
+/* HARD_REGNO_RENAME_OK(FROM,TO) ... A C expression that is nonzero if it is
|
3849 |
|
|
+ * okay to rename a hard register FROM to another hard register TO. One common
|
3850 |
|
|
+ * use of this macro is to prevernt renaming of a register to another register
|
3851 |
|
|
+ * that is not saved by a prologue in an interrupt handler. The default is
|
3852 |
|
|
+ * always nonzero.
|
3853 |
|
|
+ *
|
3854 |
|
|
+ * ZipCPU --- The default looks good enough to us.
|
3855 |
|
|
+ */
|
3856 |
|
|
+#undef HARD_REGNO_RENAME_OK
|
3857 |
|
|
+#define HARD_REGNO_RENAME_OK(FROM,TO) ((is_ZIP_GENERAL_REG(FROM))&&(is_ZIP_GENERAL_REG(TO)))
|
3858 |
|
|
+
|
3859 |
|
|
+
|
3860 |
|
|
+/* MODES_TIABLE_P(M1, M2) ... A C expression that is nonzero if a value of mode
|
3861 |
|
|
+ * M1 is accessible in mode M2 without copying.
|
3862 |
|
|
+ *
|
3863 |
|
|
+ * ZipCPU --- well, that's true for us (although we support scant few modes) ...
|
3864 |
|
|
+ * so lets' set to one.
|
3865 |
|
|
+ */
|
3866 |
|
|
+#define MODES_TIEABLE_P(M1,M2) 1
|
3867 |
|
|
+
|
3868 |
|
|
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
|
3869 |
|
|
+ * This target hook should return true if it is OK to use a hard register
|
3870 |
|
|
+ * REGNO has a scratch register in peephole2. One common use of this macro is
|
3871 |
|
|
+ * to prevent using of a register that is not saved by a prologue in an
|
3872 |
|
|
+ * interrupt handler. The default version of this hook always returns true.
|
3873 |
|
|
+ *
|
3874 |
|
|
+ * ZipCPU --- the default works for us as well. If you are in an interrupt
|
3875 |
|
|
+ * context, you have an entirely new set of registers (the supervisor set), so
|
3876 |
|
|
+ * this is a non-issue.
|
3877 |
|
|
+ */
|
3878 |
|
|
+
|
3879 |
|
|
+/* AVOID_CCMODE_COPIES ... define this macro if the compiler should avoid
|
3880 |
|
|
+ * copies to/from CCmode register(s). You should only define this macro if
|
3881 |
|
|
+ * support for copying to/from CCmode is incomplete.
|
3882 |
|
|
+ *
|
3883 |
|
|
+ * ZipCPU --- CCmode register copies work like any other, so we'll keep with the
|
3884 |
|
|
+ * default definition.
|
3885 |
|
|
+ */
|
3886 |
|
|
+
|
3887 |
|
|
+/* STACK_REGS ... Define this if the machine has any stack-like registers.
|
3888 |
|
|
+ *
|
3889 |
|
|
+ * Zip CPU has no stack-like registers, as their definition is different from
|
3890 |
|
|
+ * the ZipCPU stack pointer register.
|
3891 |
|
|
+ */
|
3892 |
|
|
+
|
3893 |
127 |
dgisselq |
+// #define ZIP_REG_BYTE_SIZE 1
|
3894 |
102 |
dgisselq |
+
|
3895 |
|
|
+/* 17.08 Register Classes */
|
3896 |
|
|
+
|
3897 |
|
|
+/* enum reg_class ... An enumerate type that must be defined with all the
|
3898 |
|
|
+ * register class names as enumerated values. NO_REGS must be first. ALL_REGS
|
3899 |
|
|
+ * must be the last register class, followed by one more enumerated value,
|
3900 |
|
|
+ * LIM_REG_CLASSES, which is not a register class but rather tells how many
|
3901 |
|
|
+ * classes there are.
|
3902 |
|
|
+ *
|
3903 |
|
|
+ * ZipCPU --- We'll defined register 0-13 as general registers, 14-15 in
|
3904 |
|
|
+ * all_regs, and go from there.
|
3905 |
|
|
+ */
|
3906 |
|
|
+enum reg_class {
|
3907 |
|
|
+ NO_REGS, GENERAL_REGS,
|
3908 |
|
|
+ USER_REGS,
|
3909 |
|
|
+ ALL_REGS, LIM_REG_CLASSES
|
3910 |
|
|
+};
|
3911 |
|
|
+
|
3912 |
|
|
+/* N_REG_CLASSES ... the number of distinct register classes, defined as follows
|
3913 |
|
|
+ */
|
3914 |
|
|
+#define N_REG_CLASSES (int)LIM_REG_CLASSES
|
3915 |
|
|
+
|
3916 |
|
|
+/* REG_CLASS_NAMES ... An initializer containing the names of the register
|
3917 |
|
|
+ * classes as C string constants. These names are used in writing some of the
|
3918 |
|
|
+ * debugging dumps.
|
3919 |
|
|
+ */
|
3920 |
171 |
dgisselq |
+#define REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" }
|
3921 |
102 |
dgisselq |
+
|
3922 |
|
|
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register
|
3923 |
127 |
dgisselq |
+ * classes, as integers which are bit masks. The nth integer specifies the
|
3924 |
102 |
dgisselq |
+ * contents of class n. That way the integer mask is interpreted as that
|
3925 |
|
|
+ * register r is in the class if (mask&(1<<r)) is 1.
|
3926 |
|
|
+ *
|
3927 |
171 |
dgisselq |
+ * When the machine has more than 32 registers, an integer does not suffice.
|
3928 |
|
|
+ * Then the integers are replaced by sub-initializers, braced groupings
|
3929 |
|
|
+ * containing several integers. Each sub-initializer must be suitable as an
|
3930 |
|
|
+ * initializer for the type HARD_REG_SET which is defined in 'hard-reg-set.h'.
|
3931 |
|
|
+ * In this situation, the first integer in each subinitializer corresponds to
|
3932 |
|
|
+ * registers 0-31, the second integer to registers 32-634, and so on.
|
3933 |
102 |
dgisselq |
+ *
|
3934 |
|
|
+ * ZipCPU --- This is straight forward, three register classes, etc.
|
3935 |
|
|
+ */
|
3936 |
171 |
dgisselq |
+#define REG_CLASS_CONTENTS { { 0x000000000, 0}, {0x00003fff, 0}, {0x0ffff0000, 0}, {0x0ffffffff, 1} }
|
3937 |
102 |
dgisselq |
+
|
3938 |
|
|
+/* REGNO_REG_CLASS ... A C expression whose value is a register class
|
3939 |
|
|
+ * containing hard register REGNO. In general there is more than one such
|
3940 |
|
|
+ * class; Choose a class which is minimal, meaning that no smaller class also
|
3941 |
|
|
+ * contains the register.
|
3942 |
|
|
+ */
|
3943 |
171 |
dgisselq |
+#define REGNO_REG_CLASS(R) (is_ZIP_REG(R)?(((R)<=13)?GENERAL_REGS:ALL_REGS):NO_REGS)
|
3944 |
102 |
dgisselq |
+
|
3945 |
|
|
+/* BASE_REG_CLASS ... A macro whose definition is the name of the class to which
|
3946 |
|
|
+ * a valid base register must belong. A base register is one used in an address
|
3947 |
|
|
+ * which is the register value plus a displacement.
|
3948 |
|
|
+ */
|
3949 |
|
|
+#undef BASE_REG_CLASS
|
3950 |
|
|
+#define BASE_REG_CLASS GENERAL_REGS
|
3951 |
|
|
+
|
3952 |
|
|
+/* MODE_BASE_CLASS(MODE) ... This is a variation of the BASE_REG_CLASS macro
|
3953 |
|
|
+ * which allows the selection of a bse register in a mode dependent manner. If
|
3954 |
|
|
+ * mode is VOIDmode then it should return the same value as BASE_REG_CLASS.
|
3955 |
|
|
+ */
|
3956 |
|
|
+#undef MODE_BASE_CLASS
|
3957 |
|
|
+#define MODE_BASE_CLASS(MODE) GENERAL_REGS
|
3958 |
|
|
+
|
3959 |
|
|
+/* MODE_BASE_REG_REG_CLASS(MODE) ... A C expression whose value is the register
|
3960 |
|
|
+ * class to which a valid base register must belong in order to be used in a
|
3961 |
|
|
+ * base plus index register address. You should define this macro if base plus
|
3962 |
|
|
+ * index addresses have different requirements than other base register uses.
|
3963 |
|
|
+ *
|
3964 |
|
|
+ * Zip CPU does not support the base plus index addressing mode, thus ...
|
3965 |
|
|
+ */
|
3966 |
111 |
dgisselq |
+// #undef MODE_BASE_REG_REG_CLASS
|
3967 |
|
|
+// #define MODE_BASE_REG_REG_CLASS(MODE) NO_REGS
|
3968 |
102 |
dgisselq |
+
|
3969 |
|
|
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
|
3970 |
|
|
+ * which a valid index register must belong. An index register is one used in
|
3971 |
|
|
+ * an address where its value is either multiplied by a scale factor or added
|
3972 |
|
|
+ * to another register (as well as added to a displacement).
|
3973 |
|
|
+ *
|
3974 |
|
|
+ * ZipCPU -- Has no index registers.
|
3975 |
|
|
+ */
|
3976 |
|
|
+#undef INDEX_REG_CLASS
|
3977 |
|
|
+#define INDEX_REG_CLASS NO_REGS
|
3978 |
|
|
+
|
3979 |
|
|
+/* REGNO_OK_FOR_BASE_P(NUM) ... A C expression which is nonzero if register
|
3980 |
|
|
+ * number num is suitable for use as a base register in operand addresses.
|
3981 |
|
|
+ */
|
3982 |
|
|
+#undef REGNO_OK_FOR_BASE_P
|
3983 |
127 |
dgisselq |
+# define REGNO_OK_FOR_BASE_P(NUM) ((NUM>=FIRST_PSEUDO_REGISTER)||(NUM != zip_CC))
|
3984 |
102 |
dgisselq |
+
|
3985 |
|
|
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
|
3986 |
|
|
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
|
3987 |
111 |
dgisselq |
+ * memory reference in MODE. You should define this macro if the mode of the
|
3988 |
102 |
dgisselq |
+ * memory reference affects whether a register may be used as a base register.
|
3989 |
|
|
+ *
|
3990 |
|
|
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
|
3991 |
|
|
+ */
|
3992 |
|
|
+
|
3993 |
|
|
+/* REGNO_MODE_OK_FOR_REG_BASE_P(NUM, MODE) ... base plus index operand
|
3994 |
|
|
+ * addresses, accessing memory in mode mode.
|
3995 |
|
|
+ *
|
3996 |
|
|
+ * Use of this macro is deprecated.
|
3997 |
|
|
+ */
|
3998 |
|
|
+
|
3999 |
111 |
dgisselq |
+/* REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) ... A C expression which is
|
4000 |
102 |
dgisselq |
+ * nonzero if a register number N is suitable for use as a base register in
|
4001 |
|
|
+ * operand addresses, accessing memory in mode M in address space AS. This is
|
4002 |
|
|
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
|
4003 |
|
|
+ * the context in which the register appears in the memory reference.
|
4004 |
|
|
+ *
|
4005 |
|
|
+ * ZipCPU---We aren't specific in how we use our registers.
|
4006 |
|
|
+ */
|
4007 |
|
|
+#define REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) REGNO_OK_FOR_BASE_P(N)
|
4008 |
|
|
+
|
4009 |
|
|
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
|
4010 |
|
|
+ * num is suitable for use as an index register in opernad addressess. It may
|
4011 |
|
|
+ * be either a suitable hard register or a pseudo register that has been
|
4012 |
111 |
dgisselq |
+ * allocated such as a hard register.
|
4013 |
102 |
dgisselq |
+ *
|
4014 |
|
|
+ * ZipCPU has no index registers, therefore we declare this to be zero.
|
4015 |
|
|
+ */
|
4016 |
|
|
+#undef REGNO_OK_FOR_INDEX_P
|
4017 |
|
|
+#define REGNO_OK_FOR_INDEX_P(REGNO) 0
|
4018 |
|
|
+
|
4019 |
|
|
+/* TARGET_PREFERRED_RENAME_CLASS(RCLASS) ... A target hook that places
|
4020 |
|
|
+ * additional preference on the register class to use when it is necessary to
|
4021 |
|
|
+ * rename a register in class RCLASS to another class, or perhaps NO_REGS, if no
|
4022 |
|
|
+ * preferred register class is found or hook preferred_rename_class is not
|
4023 |
|
|
+ * implemented. SOmething returning a more restrictive class makes better code.
|
4024 |
|
|
+ * For example, on ARM, thumb-2 instructions using LO_REGS may be smaller than
|
4025 |
|
|
+ * instructions using GENERIC_REGS. By returning LO_REGS from
|
4026 |
|
|
+ * preferred_rename_class, code size can be reduced.
|
4027 |
|
|
+ */
|
4028 |
|
|
+// #undef TARGET_PREFERRED_RENAME_CLASS
|
4029 |
|
|
+// #define TARGET_PREFERRED_RENAME_CLASS(RCLASS) RCLASS
|
4030 |
|
|
+
|
4031 |
|
|
+/* TARGET_PREFERRED_RELOAD_CLASS(X,RC) ... A target hook that places additional
|
4032 |
|
|
+ * restri tions on the register class to use when it is necessary to copy value
|
4033 |
|
|
+ * X into a register in class RC. The value is a register class; rehaps RC, or
|
4034 |
|
|
+ * perhaps a smaller class.
|
4035 |
|
|
+ *
|
4036 |
|
|
+ * The default fversion of this hook always returns value of RC argument, which
|
4037 |
|
|
+ * sounds quite appropriate for the ZipCPU.
|
4038 |
|
|
+ */
|
4039 |
|
|
+
|
4040 |
|
|
+/* PREFERRED_RELOAD_CLASS(X,CLASS) ... A C expression that places additional
|
4041 |
|
|
+ * restrictions on the register class to use when it is necessary to copy
|
4042 |
|
|
+ * value X into a register in class CLASS. On many machines, the following
|
4043 |
|
|
+ * definition is safe: PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
|
4044 |
|
|
+ * Sometimes returning a more restrictive class makes better code. For example,
|
4045 |
|
|
+ * on the 68k, when x is an integer constant that is in range for a moveq
|
4046 |
|
|
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
|
4047 |
111 |
dgisselq |
+ * includes the data registers. Requiring a data register guarantees that a
|
4048 |
102 |
dgisselq |
+ * 'moveq' will be used.
|
4049 |
|
|
+ *
|
4050 |
|
|
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS. For
|
4051 |
|
|
+ * example, loading (sleep and !gie) into the CC register could halt the CPU.
|
4052 |
|
|
+ * Hence, we only allow loads into the GENERAL_REG class.
|
4053 |
|
|
+ */
|
4054 |
|
|
+#define PREFERRED_RELOAD_CLASS(X, CLASS) GENERAL_REGS
|
4055 |
|
|
+
|
4056 |
|
|
+/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS(RTX,RCLASS) ... Like TARGET_PREFERRED_..
|
4057 |
|
|
+ * RELOAD_CLASS, but for output instead of input reloads.
|
4058 |
|
|
+ *
|
4059 |
|
|
+ * ZipCPU --- there's gotta be a valid default behaviour for this.
|
4060 |
|
|
+ */
|
4061 |
|
|
+
|
4062 |
|
|
+/* LIMIT_RELOAD_CLASS(MODE, CL) ...
|
4063 |
|
|
+ *
|
4064 |
|
|
+ * Don't define this macro unless the target machine has limitations which
|
4065 |
|
|
+ * require the macro to do something nontrivial. ZipCPU doesn't, so we won't.
|
4066 |
|
|
+ */
|
4067 |
|
|
+
|
4068 |
|
|
+/* TARGET_SECONDARY_RELOAD
|
4069 |
|
|
+ * SECONDARY_ ...
|
4070 |
|
|
+ * Don't think we need these ...
|
4071 |
|
|
+ */
|
4072 |
|
|
+
|
4073 |
|
|
+/* CLASS_MAX_NREGS(CLASS,MODE) ... A C expression for the maximum number of
|
4074 |
|
|
+ * consecutive registers of class CLASS needed to hold a value of mode MODE.
|
4075 |
|
|
+ *
|
4076 |
|
|
+ * This is closely related to the macro HARD_REGNO_NREGS. In fact, the value
|
4077 |
|
|
+ * of the macro CLASS_MAX_REGS(CL,M) should be the maximum value of
|
4078 |
|
|
+ * HARD_REGNO_NREGS(REGNO,MODE) for all REGNO values in the class CLASS.
|
4079 |
|
|
+ *
|
4080 |
|
|
+ * This macro helps control the handling of multiple word values in the reload
|
4081 |
|
|
+ * pass.
|
4082 |
|
|
+ *
|
4083 |
|
|
+ * ZipCPU --- We'll just use HARDNO_REGNO_NREGS, since CLASS is independent for
|
4084 |
|
|
+ * us. We'll also choose register R0, since ... well, since it simply doesn't
|
4085 |
|
|
+ * matter. (HARD_REGNO_NREGS ignores this anyway)
|
4086 |
|
|
+ */
|
4087 |
|
|
+#define CLASS_MAX_NREGS(CLASS, MODE) HARD_REGNO_NREGS(0,MODE)
|
4088 |
|
|
+
|
4089 |
|
|
+/* CANNOT_CHANGE_MODE_CLASS
|
4090 |
|
|
+ * ???
|
4091 |
|
|
+ */
|
4092 |
|
|
+
|
4093 |
|
|
+/* TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
|
4094 |
|
|
+ */
|
4095 |
|
|
+
|
4096 |
|
|
+/* TARRGET_LRA_P
|
4097 |
|
|
+ * Default looks good.
|
4098 |
|
|
+ */
|
4099 |
|
|
+
|
4100 |
|
|
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
|
4101 |
111 |
dgisselq |
+ * priority number to which the register HARD_REGNO belongs to. The bigger the
|
4102 |
102 |
dgisselq |
+ * number
|
4103 |
|
|
+ *
|
4104 |
|
|
+ * The default version of this target hook returns always zero---good enough for
|
4105 |
|
|
+ * the ZipCPU.
|
4106 |
|
|
+ */
|
4107 |
|
|
+
|
4108 |
|
|
+/* TARGET_REGISTER_USAGE_LEVELING_P(VOID) ... A target hook which returns true
|
4109 |
|
|
+ * if we need register usage leveling. That means if a few hard registers are
|
4110 |
|
|
+ * equally good for the assignment, we choose the least used hard register. The
|
4111 |
|
|
+ * register usage leveling may be profitable for some targets. Don't use usage
|
4112 |
|
|
+ * leveling for targets with conditional execution or targets with big register
|
4113 |
|
|
+ * files as it hurts if-conversion and cross-jumping optimizations. The default
|
4114 |
|
|
+ * version of this target hook returns always false.
|
4115 |
|
|
+ *
|
4116 |
|
|
+ * ZipCPU --- Default is the right answer.
|
4117 |
|
|
+ */
|
4118 |
|
|
+
|
4119 |
|
|
+/* TARGET_DIFFERENT_ADDR_DISPLACEMENT_P ...
|
4120 |
|
|
+ * Default looks good.
|
4121 |
|
|
+ */
|
4122 |
|
|
+
|
4123 |
|
|
+/* TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P ...
|
4124 |
|
|
+ * Default looks good.
|
4125 |
|
|
+ */
|
4126 |
|
|
+
|
4127 |
|
|
+/* TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT ....
|
4128 |
|
|
+ */
|
4129 |
|
|
+
|
4130 |
|
|
+/* TARGET_SPILL_CLASS
|
4131 |
|
|
+ *
|
4132 |
|
|
+ * ZipCPU --- If we were running in supervisor mode only, this might be the
|
4133 |
|
|
+ * user set of registers. However, we're not building for that mode (now),
|
4134 |
|
|
+ * so we'll leave this at the default of NO_REGS.
|
4135 |
|
|
+ */
|
4136 |
|
|
+
|
4137 |
|
|
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
|
4138 |
|
|
+ * boolean result of conditional store patterns. The OCIDE argument is the
|
4139 |
|
|
+ * instruction code for the cstore being performed. Not defining this hook is
|
4140 |
|
|
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
|
4141 |
|
|
+ * patterns.
|
4142 |
|
|
+ *
|
4143 |
|
|
+ * ??? ZipCPU --- I don't follow this documentation. We'll leave this at the
|
4144 |
|
|
+ * default therefore.
|
4145 |
|
|
+ */
|
4146 |
|
|
+
|
4147 |
|
|
+/* 17.09 Stack Layout and Calling Conventions */
|
4148 |
|
|
+
|
4149 |
|
|
+
|
4150 |
|
|
+/* STACK_GROWS_DOWNWARD ... Define this macro if pushing a word onto the stack
|
4151 |
|
|
+ * moves the stack pointer to a smaller address, and false otherwise.
|
4152 |
|
|
+ *
|
4153 |
|
|
+ * ZipCPU ... well, our stack does grow downward, but it doesn't do so auto-
|
4154 |
|
|
+ * magically. We have to move the stack pointer ourselves. However, since this
|
4155 |
|
|
+ * is our convention, we'll define it as such.
|
4156 |
|
|
+ */
|
4157 |
|
|
+#undef STACK_GROWS_DOWNWARD
|
4158 |
|
|
+#define STACK_GROWS_DOWNWARD 1
|
4159 |
|
|
+
|
4160 |
|
|
+/* STACK_PUSH_CODE ... This macro defines the operation used when something is
|
4161 |
|
|
+ * pushed on the stack. In RTL, a push operation will be
|
4162 |
|
|
+ * (set (mem( STACK_PUSH_CODE(reg sp))) ...) The choiecs are PRE_DEC, POST_DEC,
|
4163 |
|
|
+ * PRE_INC, and POST_INC. Which of these is correct depends on the stack
|
4164 |
|
|
+ * direction and on whether the stack pointer points to the last item on the
|
4165 |
|
|
+ * stack or whether it points to the space for the next item on the stack.
|
4166 |
|
|
+ * The default is PRE_DECC when STACK_GROWS_DOWNWARD is true, which is almost
|
4167 |
|
|
+ * always right, and PRE_INC otherwise, which is often wrong.
|
4168 |
|
|
+ *
|
4169 |
|
|
+ * ZipCPU --- None of these is right, so let's leave this at the default and
|
4170 |
|
|
+ * see how badly we get mangled. In particular, ZipCPU doesn't have any of the
|
4171 |
|
|
+ * PRE_DEC, POST_DEC, PRE_INC, or POST_INC addressing modes used here.
|
4172 |
|
|
+ */
|
4173 |
|
|
+
|
4174 |
|
|
+/* FRAME_GROWS_DOWNWARD ... Define this macro to nonzero if the addresses of
|
4175 |
|
|
+ * local variable slots are at negative offsets from the frame pointer.
|
4176 |
|
|
+ *
|
4177 |
|
|
+ * ZipCPU --- If the frame pointer is defined as the stack pointer upon the
|
4178 |
103 |
dgisselq |
+ * start of function execution, and that stack pointer grows downward, then
|
4179 |
102 |
dgisselq |
+ * this should be the case as well.
|
4180 |
|
|
+ */
|
4181 |
|
|
+#undef FRAME_GROWS_DOWNWARD
|
4182 |
|
|
+#define FRAME_GROWS_DOWNWARD 1
|
4183 |
|
|
+// #define FRAME_GROWS_DOWNWARD 0 // This was ECO32's value
|
4184 |
|
|
+
|
4185 |
|
|
+
|
4186 |
|
|
+/* ARGS_GROW_DOWNWARD ... Define this macro if successive arguments to a
|
4187 |
|
|
+ * function occupy decreasing addresses on the stack.
|
4188 |
|
|
+ *
|
4189 |
|
|
+ * ZipCPU -- we can leave this up to the compiler's preferred implementation,
|
4190 |
|
|
+ * it is of no consequence to the hardware.
|
4191 |
|
|
+ */
|
4192 |
|
|
+
|
4193 |
|
|
+/* STARTING_FRAME_OFFSET ... Offset from the frame pointer to the first local
|
4194 |
|
|
+ * variable slot to be allocated. If FRAME_GROWS_DOWNWARD, find the next slot's
|
4195 |
171 |
dgisselq |
+ * offset by subtracting the first slot's length from STARTING_FRAME_OFFSET.
|
4196 |
102 |
dgisselq |
+ * Otherwise it is found by adding the length of the first slot to the value
|
4197 |
|
|
+ * START_FRAME_OFFSET.
|
4198 |
|
|
+ *
|
4199 |
|
|
+ * ZipCPU --- I'm not certain on this, let's come back after we look at how
|
4200 |
|
|
+ * the code is getting generated. However, the ECO32 code I am copying from
|
4201 |
|
|
+ * suggests that 0 is the right value, so we'll use that here.
|
4202 |
|
|
+ */
|
4203 |
171 |
dgisselq |
+// #warning "Re-evaluate me" --- I did. This still looks good.
|
4204 |
102 |
dgisselq |
+#define STARTING_FRAME_OFFSET 0
|
4205 |
|
|
+
|
4206 |
|
|
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
|
4207 |
|
|
+ * stack during reload. The nonzero default for this macro is suitable for most
|
4208 |
|
|
+ * ports.
|
4209 |
|
|
+ *
|
4210 |
|
|
+ * ZipCPU --- we'll leave this at the default, although if any alignment code
|
4211 |
|
|
+ * shows up on the stack we may need to adjust it.
|
4212 |
|
|
+ */
|
4213 |
|
|
+
|
4214 |
|
|
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
|
4215 |
|
|
+ * which outgoing arguments are placed. If not specified, the default value
|
4216 |
|
|
+ * of zero is used. This is the proper value for most machines.
|
4217 |
|
|
+ */
|
4218 |
|
|
+#define STACK_POINTER_OFFSET 0
|
4219 |
|
|
+
|
4220 |
|
|
+/* FIRST_PARM_OFFSET ... Offset from the argument pointer register to the first
|
4221 |
|
|
+ * argument's address. On some machines it may depend on the data type of the
|
4222 |
171 |
dgisselq |
+ * function.
|
4223 |
102 |
dgisselq |
+ */
|
4224 |
|
|
+#define FIRST_PARM_OFFSET(F) 0
|
4225 |
|
|
+
|
4226 |
|
|
+/* STACK_DYNAMIC_OFFSET(F) ... Offset from the stack pointer register to an item
|
4227 |
|
|
+ * dynamically allocated on the stack, e.g., by alloca. The default value for
|
4228 |
|
|
+ * this macro is STACK_POINTER_OFFSET plus the length of the outgoing arguments.
|
4229 |
|
|
+ * The default is correct for most machines, ...
|
4230 |
|
|
+ *
|
4231 |
|
|
+ * ZipCPU --- so we'll use it for the ZipCPU.
|
4232 |
|
|
+ */
|
4233 |
|
|
+
|
4234 |
|
|
+/* INITIAL_FRAME_ADDRESS_RTX ... A C expression whose value is RTL representing
|
4235 |
|
|
+ * the address of the initial stack frame. This address is passed to
|
4236 |
|
|
+ * RETURN_ADDR_RTX and DYNAMIC_CHAIN_ADDRESS. If you don't define this macro,
|
4237 |
|
|
+ * a reasonable default value will be used. Define this macro in order to make
|
4238 |
|
|
+ * frame pointer elimination work in the presence of __builtin_frame_address(C)
|
4239 |
|
|
+ * and __builtin_return_address(C) for (C) not equal to zero.
|
4240 |
|
|
+ *
|
4241 |
|
|
+ * ZipCPU --- Let's try the reasonable default and see what happens.
|
4242 |
|
|
+ */
|
4243 |
|
|
+
|
4244 |
|
|
+/* SETUP_FRAME_ADDRESSES ... A C expression that produces the machine-specific
|
4245 |
|
|
+ * code to setup the stack so that arbitrary frames can be accessed. For
|
4246 |
|
|
+ * example, on the SPARC, we must flush all of the register windows to the stack
|
4247 |
|
|
+ * before we can access arbitrary stack frames. You will seldom need to define
|
4248 |
|
|
+ * this macro. The default is to do nothing.
|
4249 |
|
|
+ *
|
4250 |
|
|
+ * ZipCPU --- which is what we shall do here.
|
4251 |
|
|
+ */
|
4252 |
|
|
+
|
4253 |
|
|
+/* TARGET_BUILTIN_SETJMP_FRAME_VALUE(VOID) ... This target hook should return
|
4254 |
|
|
+ * an RTX that is used to store the address of the current frame into the
|
4255 |
|
|
+ * builtin setjmp buffer. The default value, virtual_stack_vars_rtx, is correct
|
4256 |
|
|
+ * for most machines. One reason you may need to define this target hook is if
|
4257 |
|
|
+ * hard_frame_pointer_rtx is the appropriate value on your machine.
|
4258 |
|
|
+ *
|
4259 |
|
|
+ * ZipCPU --- leave this undefined, since the default value should be correct
|
4260 |
|
|
+ * for "most" machines.
|
4261 |
|
|
+ */
|
4262 |
|
|
+
|
4263 |
|
|
+/* FRAME_ADDR_RTX ... most machines do not need to define it.
|
4264 |
|
|
+ */
|
4265 |
|
|
+
|
4266 |
|
|
+/* RETURN_ADDR_RTX(COUNT,FRAMEADDR) ... A C expression whose value is RTL
|
4267 |
|
|
+ * representing the value of the return address for the frame COUNT steps up
|
4268 |
|
|
+ * from the current frame, after the prologue. FRAMEADDR is the frame pointer
|
4269 |
|
|
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
|
4270 |
|
|
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero. The value of the expression must
|
4271 |
|
|
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
|
4272 |
|
|
+ * there is no way to determine the return address of other frames.
|
4273 |
|
|
+ *
|
4274 |
|
|
+ * ZipCPU --- I have no idea how we'd do this, so let's just return NULL_RTX.
|
4275 |
|
|
+ */
|
4276 |
|
|
+#undef RETURN_ADDR_RTX
|
4277 |
|
|
+#define RETURN_ADDR_RTX(COUNT,FRAMEADDR) NULL_RTX
|
4278 |
|
|
+
|
4279 |
|
|
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
|
4280 |
|
|
+ * return address of a particular stack frame is accessed from the frame pointer
|
4281 |
|
|
+ * of the previous stack frame. The zero default for this macro is suitable
|
4282 |
|
|
+ * for most ports.
|
4283 |
|
|
+ *
|
4284 |
|
|
+ * ZipCPU---Default works here as well.
|
4285 |
|
|
+ */
|
4286 |
|
|
+
|
4287 |
|
|
+/* INCOMING_RETURN_ADDR_RTX ... A C expression whose value is RTL representing
|
4288 |
|
|
+ * the location of the incoming return address at the beginning of any function,
|
4289 |
|
|
+ * before the prologue. This RTL is either a REG, indicating that the return
|
4290 |
|
|
+ * value is saved in 'REG', or a MEM representing the location in the stack.
|
4291 |
|
|
+ * If this RTL is a REG, you should define DWARF_RETURN_COLUMN to
|
4292 |
|
|
+ * DWARF_FRAME_REGNUM(REGNO).
|
4293 |
|
|
+ *
|
4294 |
|
|
+ * ZipCPU --- While our incoming return address could theoretically be in any
|
4295 |
|
|
+ * register, our machine description file is going to place it into register
|
4296 |
|
|
+ * R0, so that's what we return here.
|
4297 |
|
|
+ */
|
4298 |
|
|
+#undef INCOMING_RETURN_ADDR_RTX
|
4299 |
|
|
+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(SImode, zip_R0)
|
4300 |
|
|
+
|
4301 |
|
|
+
|
4302 |
|
|
+/* DWARF_ALT_FRAME_RETURN_COLUMN
|
4303 |
|
|
+ */
|
4304 |
|
|
+
|
4305 |
|
|
+/* DWARF_ZERO_REG ... A C exrpession whose value is an integer giving a DWARF2
|
4306 |
|
|
+ * register number that is considered to always have the value zero. This
|
4307 |
|
|
+ * should only be defined if the target has an architected zero register (ZipCPU
|
4308 |
|
|
+ * does not), and someone decided it was a good idea to use that register number
|
4309 |
|
|
+ * to terminate the stack backtrace. New ports should avoid this (so the
|
4310 |
|
|
+ * ZipCPU port will avoid it as well).
|
4311 |
|
|
+ *
|
4312 |
|
|
+ */
|
4313 |
|
|
+
|
4314 |
|
|
+/* TARGET_DWARF_HANDLE_FRAME_UNSPEC
|
4315 |
|
|
+ */
|
4316 |
|
|
+
|
4317 |
171 |
dgisselq |
+/* INCOMING_FRAME_SP_OFFSET ... A C expression whose value is an integer giving
|
4318 |
|
|
+ * the offset, in bytes, from the value of the stack pointer register to the
|
4319 |
|
|
+ * top of the stack frame at the beginning of any function, before the prologue.
|
4320 |
|
|
+ * The top of the frame is defined to be the value of the stack pointer in the
|
4321 |
|
|
+ * previous frame, just before the call instruction.
|
4322 |
|
|
+ *
|
4323 |
|
|
+ * You only need to define this macro if you want to support call frame
|
4324 |
|
|
+ * debugging information like that provided by DWARF 2.
|
4325 |
|
|
+ *
|
4326 |
|
|
+ * ZipCPU---Our value is zero.
|
4327 |
102 |
dgisselq |
+ */
|
4328 |
|
|
+#define INCOMING_FRAME_SP_OFFSET 0
|
4329 |
|
|
+
|
4330 |
|
|
+/* ARG_POINTER_CFA_OFFSET
|
4331 |
|
|
+ */
|
4332 |
|
|
+
|
4333 |
|
|
+/* FRAME_POINTER_CFA_OFFSET
|
4334 |
|
|
+ */
|
4335 |
|
|
+
|
4336 |
|
|
+/* CFA_FRAME_BASE_OFFSET
|
4337 |
|
|
+ */
|
4338 |
|
|
+
|
4339 |
|
|
+/* 17.09.02 Exception handling support */
|
4340 |
|
|
+
|
4341 |
|
|
+/* EH_RETURN_DATA_REGNO(N) ... A C expression whose value is the Nth register
|
4342 |
|
|
+ * number used for data by exception handlers, or INVALID_REGNUM if fewer than
|
4343 |
|
|
+ * N registers are usable. The exception handling library routines communicate
|
4344 |
|
|
+ * with the exception handlers via a set of agreed upon registers. Ideally
|
4345 |
|
|
+ * these registers should be call clobbered; it is possible to use call-saved
|
4346 |
|
|
+ * registers, but may negatively impact code size. The target must support at
|
4347 |
|
|
+ * least 2 data registers, but should define 4 if their are enough free
|
4348 |
|
|
+ * registers.
|
4349 |
|
|
+ *
|
4350 |
|
|
+ * You must define this macro if you want to support call frame exception
|
4351 |
|
|
+ * handling like that provided by DWARF 2.
|
4352 |
|
|
+ */
|
4353 |
|
|
+#define EH_RETURN_DATA_REGNO(N) (((N<ZIP_FIRST_ARG_REGNO)||(N>ZIP_LAST_ARG_REGNO))?(N-1):INVALID_REGNUM)
|
4354 |
|
|
+
|
4355 |
|
|
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
|
4356 |
|
|
+ * a location in which to store a stack adjustment to be applied before function
|
4357 |
|
|
+ * return. This is used to unwind the stack to an exception handler's call
|
4358 |
|
|
+ * frame. It will be assigned zero on code paths that return normally.
|
4359 |
|
|
+ *
|
4360 |
|
|
+ * Do not define this macro if the stack pointer is saved and restored by the
|
4361 |
|
|
+ * regular prolog and epilog code in the call frame itself (which it is for the
|
4362 |
|
|
+ * ZipCPU); in this case, the exception handling library routines will update
|
4363 |
|
|
+ * the stack location to be restored in place. Otherwise, you must define this
|
4364 |
|
|
+ * macro if you want to support call frame exception handling like that provided
|
4365 |
|
|
+ * by DWARF 2.
|
4366 |
|
|
+ *
|
4367 |
|
|
+ */
|
4368 |
|
|
+
|
4369 |
|
|
+/* EH_RETURN_HANDLER_RTX ... A C expression whose value is RTL representing a
|
4370 |
|
|
+ * location in which to store the address of an exception handler to which we
|
4371 |
|
|
+ * should return. It will not be assigned on code paths that return normally.
|
4372 |
|
|
+ *
|
4373 |
|
|
+ * Typcally this is the location in the call frame at which the normal return
|
4374 |
|
|
+ * address is stored. For targets that return by popping an address of the
|
4375 |
|
|
+ * stack, this might be a memory address just below the target callf rame
|
4376 |
|
|
+ * rather than inside the current call frame. If defined,
|
4377 |
|
|
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
|
4378 |
|
|
+ * to calculate the location of the target call frame.
|
4379 |
|
|
+ *
|
4380 |
|
|
+ * If you want to support call frame exception handling, you must define either
|
4381 |
|
|
+ * this macro or the eh_return instruction pattern.
|
4382 |
|
|
+ */
|
4383 |
|
|
+// #warning "I don't know what to do here."
|
4384 |
|
|
+
|
4385 |
|
|
+/*
|
4386 |
|
|
+ *
|
4387 |
|
|
+ *
|
4388 |
|
|
+ *
|
4389 |
|
|
+ * REST OF SECTION SKIPPED ...
|
4390 |
|
|
+ *
|
4391 |
|
|
+ *
|
4392 |
|
|
+ *
|
4393 |
|
|
+ */
|
4394 |
|
|
+
|
4395 |
|
|
+/* 17.09.03 Specifying how stack checking is done */
|
4396 |
|
|
+
|
4397 |
|
|
+/* STACK_CHECK_BUILTIN ... a non-zero value if stack checking is done by the
|
4398 |
|
|
+ * configuration files in a machine-dependent manner. You should define this
|
4399 |
|
|
+ * macro if stack checking is required by the ABI of your machine or if you
|
4400 |
|
|
+ * would like to do stack checking in some more efficient way than the generic
|
4401 |
|
|
+ * appraoch. The default value of this macro is zero.
|
4402 |
|
|
+ *
|
4403 |
|
|
+ * ZipCPU --- The default makes sense for us.
|
4404 |
|
|
+ */
|
4405 |
|
|
+// #define STACK_CHECK_BUILTIN 0
|
4406 |
|
|
+
|
4407 |
|
|
+/* STACK_CHECK_STATIC_BUILTIN ... A nonzero value if static stack checking is
|
4408 |
|
|
+ * done by the configuration files in a machine-dependent manner. You should
|
4409 |
|
|
+ * define this macro if you would like to do static stack checking in some more
|
4410 |
|
|
+ * efficient way than the generic approach. The default value of this macro
|
4411 |
|
|
+ * is zero.
|
4412 |
|
|
+ *
|
4413 |
|
|
+ * ZipCPU --- The default makes sense for us.
|
4414 |
|
|
+ */
|
4415 |
|
|
+
|
4416 |
|
|
+/* STACK_CHECK_PROBE_INTERVAL_EXP ... An integer specifying the interval at
|
4417 |
|
|
+ * which GCC must generate stack probe instructions, defined as 2 raised to this
|
4418 |
|
|
+ * interval. You will normally define this macro so that the interval is no
|
4419 |
|
|
+ * larger than the size of the "guard pages" at the end of a stack area. The
|
4420 |
|
|
+ * default value of 12 (4096-byte interval) is suitable for most systems.
|
4421 |
|
|
+ *
|
4422 |
|
|
+ * ZipCPU --- Default.
|
4423 |
|
|
+ */
|
4424 |
|
|
+
|
4425 |
|
|
+/* STACK_CHECK_MOVING_SP ... An integer which is non-zero if GCC should move
|
4426 |
|
|
+ * the stack pointer page by page when doing probes. This can be necessary
|
4427 |
|
|
+ * on systems where the stack pointer contains the bottom address of the memory
|
4428 |
|
|
+ * area accessible to the executing thread at any point in time. In this
|
4429 |
|
|
+ * situation, an alternate signal stack is required in order to be able to
|
4430 |
|
|
+ * recover from a stack overflow. The default value of this macro is zero.
|
4431 |
|
|
+ *
|
4432 |
|
|
+ * ZipCPU -- Default.
|
4433 |
|
|
+ */
|
4434 |
|
|
+
|
4435 |
|
|
+/* STACK_CHECK_PROTECT
|
4436 |
|
|
+ */
|
4437 |
|
|
+/* STACK_CHECK_MAX_FRAME_SIZE
|
4438 |
|
|
+ * ... you should normally not change the default value of this macro.
|
4439 |
|
|
+ */
|
4440 |
|
|
+/* STACK_CHECK_FIXED_FRAME_SIZE
|
4441 |
|
|
+ * ... you ... will normally use the default of four words.
|
4442 |
|
|
+ */
|
4443 |
|
|
+
|
4444 |
|
|
+/* STACK_CHECK_MAX_VAR_SIZE
|
4445 |
|
|
+ * ... you will normally not need to override that default.
|
4446 |
|
|
+ */
|
4447 |
|
|
+
|
4448 |
|
|
+/* 17.09.04 Registers that Address the Stack Frame*/
|
4449 |
|
|
+
|
4450 |
|
|
+/* STACK_POINTER_REGNUM ... The register number of the stack pointer register,
|
4451 |
|
|
+ * which must also be a fixed register according to FIXED_REGISTERS. On most
|
4452 |
|
|
+ * machines, the hardware determines which register this is.
|
4453 |
|
|
+ */
|
4454 |
|
|
+#undef STACK_POINTER_REGNUM
|
4455 |
|
|
+#define STACK_POINTER_REGNUM zip_SP
|
4456 |
|
|
+
|
4457 |
|
|
+/* FRAME_POINTER_REGNUM ... The register number of the frame pointer register,
|
4458 |
|
|
+ * which is used to access certain automatic variables in the stack frame. On
|
4459 |
|
|
+ * some machines, the hardware determines which register this is. On other
|
4460 |
|
|
+ * machines you can choose any register you wish for this purpose.
|
4461 |
|
|
+ *
|
4462 |
|
|
+ * ZipCPU --- While I'd like to dump this pointer, since I don't really see
|
4463 |
|
|
+ * a need for it, alloca() requires it. Therefore let's assine a register to
|
4464 |
|
|
+ * this purpose and watch what the compiler does with it.
|
4465 |
|
|
+ */
|
4466 |
|
|
+#define FRAME_POINTER_REGNUM zip_FP
|
4467 |
|
|
+
|
4468 |
|
|
+/* HARD_FRAME_POINTER_REGNUM ... On some machines the offset between the frame
|
4469 |
|
|
+ * pointer and starting offset of the automatic variables is not known until
|
4470 |
|
|
+ * after register allocation has been done (for example, because the saved
|
4471 |
|
|
+ * registers are between these two locations). On those machines, define
|
4472 |
|
|
+ * FRAME_POINTER_REGNUM the number of a special, fixed register to be used
|
4473 |
|
|
+ * internally until the offset is known, and define HARD_FRAME_POINTER_REGNUM
|
4474 |
|
|
+ * to be the actual hard register number used for the frame pointer.
|
4475 |
|
|
+ *
|
4476 |
|
|
+ * Do not define this macro if it would be the same as FRAME_POINTER_REGNUM
|
4477 |
|
|
+ *
|
4478 |
|
|
+ * ZipCPU --- we do not define this macro.
|
4479 |
|
|
+ */
|
4480 |
103 |
dgisselq |
+#define HARD_FRAME_POINTER_REGNUM zip_FP
|
4481 |
102 |
dgisselq |
+
|
4482 |
|
|
+/* ARG_POINTER_REGNUM ... The register number of the arg pointer register, which
|
4483 |
|
|
+ * is used to access the function's argument list. On some machines, this is
|
4484 |
|
|
+ * the same as the frame pointer register. On some machines, the hardware
|
4485 |
|
|
+ * determines which register this is. On other machines, you can choose any
|
4486 |
|
|
+ * register you wish for this purpose. If this is not the same register as the
|
4487 |
|
|
+ * frame pointer register, then you must mark it as a fixed register according
|
4488 |
|
|
+ * to FIXED_REGISTERs, or arrange to be able to eliminate it.
|
4489 |
|
|
+ *
|
4490 |
|
|
+ * ZipCPU --- We really don't want to lose another register to something
|
4491 |
|
|
+ * pointless, so let's set this to be the frame pointer register. Especially
|
4492 |
|
|
+ * given the ZipCPU's ease of accessing things via offsets of registers, this
|
4493 |
|
|
+ * should work for a rather large stack frame.
|
4494 |
171 |
dgisselq |
+ *
|
4495 |
|
|
+ * However ... we had problems with passing 6+ variables on the stack, so let's
|
4496 |
|
|
+ * try creating a pseudo register for this, and appropriately adjusting the
|
4497 |
|
|
+ * offset between this pseudo register and the stack pointer ...
|
4498 |
102 |
dgisselq |
+ */
|
4499 |
171 |
dgisselq |
+#define ARG_POINTER_REGNUM zip_AP_PSEUDO
|
4500 |
102 |
dgisselq |
+
|
4501 |
|
|
+/* HARD_FRAME_POINTER_IS_FRAME_POINTER ... define this to be a preprocessor
|
4502 |
|
|
+ * constant that is nonzero if hard_frame_pointer_rtx and frame_pointer_rtx
|
4503 |
|
|
+ * should be the same. The default definition is sufficient for us.
|
4504 |
|
|
+ */
|
4505 |
|
|
+
|
4506 |
|
|
+/* HARD_FRAME_POINTER_IS_ARG_POINTER ...
|
4507 |
|
|
+ * ZipCPU doesn't need this macro
|
4508 |
|
|
+ */
|
4509 |
|
|
+
|
4510 |
|
|
+/* RETURN_ADDRESS_POINTER_REGNUM ... The register number of the return address
|
4511 |
|
|
+ * pointer register, which is used to access the current function's return
|
4512 |
|
|
+ * address from the stack. On some machines, the return address is not at a
|
4513 |
|
|
+ * fixed offset from the frame pointer or stack pointer or argument pointer.
|
4514 |
|
|
+ * This register can be defined to point to the return address on the stack, and
|
4515 |
|
|
+ * then to be converted by ELIMINABLE_REGS into either the frame pointer or the
|
4516 |
|
|
+ * stack pointer.
|
4517 |
|
|
+ *
|
4518 |
|
|
+ * Do not define this macro unless there is no other way to get the return
|
4519 |
|
|
+ * address from the stack.
|
4520 |
|
|
+ *
|
4521 |
|
|
+ * ZipCPU---we need this.
|
4522 |
|
|
+ */
|
4523 |
|
|
+#define RETURN_ADDRESS_REGNUM zip_R0
|
4524 |
|
|
+
|
4525 |
|
|
+
|
4526 |
|
|
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
|
4527 |
|
|
+ * static chain pointer. If register windows are used, the register number as
|
4528 |
|
|
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
|
4529 |
|
|
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM. If
|
4530 |
|
|
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
|
4531 |
|
|
+ * defined.
|
4532 |
|
|
+ *
|
4533 |
|
|
+ * ZipCPU doesn't have register windows, so we don't need to define this.
|
4534 |
|
|
+ */
|
4535 |
|
|
+// #warning "I have no reason to believe this will even work"
|
4536 |
|
|
+#define STATIC_CHAIN_REGNUM zip_GOT
|
4537 |
|
|
+
|
4538 |
|
|
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
|
4539 |
|
|
+ * al for targets that may use different static chain locations for different
|
4540 |
|
|
+ * nested functions. This may be required if the target has function attributes
|
4541 |
|
|
+ * that affect the calling conventions of the function and those calling
|
4542 |
|
|
+ * conventions use different static chain locations.
|
4543 |
|
|
+ *
|
4544 |
|
|
+ * ZipCPU --- don't need this.
|
4545 |
|
|
+ */
|
4546 |
|
|
+// #define STATIC_CHAIN_REGNUM zip_R11
|
4547 |
|
|
+
|
4548 |
|
|
+
|
4549 |
|
|
+/* DWARF_FRAME_REGISTERS ... This macro specifies the maximum number of hard
|
4550 |
|
|
+ * registers that can be saved in a call frame. This is used to size data
|
4551 |
|
|
+ * structures used in DWARF2 exception handling.
|
4552 |
|
|
+ *
|
4553 |
|
|
+ * Prior to GCC 3.0, this macro was needed in order to establish a stable
|
4554 |
|
|
+ * exception handling ABI in the face of adding new hard registers for ISA
|
4555 |
|
|
+ * extensions. In GCC 3.0 and later, the EH ABI is insulated from changes in
|
4556 |
|
|
+ * the number of hard registers. Nevertheless, this macro can still be used to
|
4557 |
|
|
+ * reduce the runtime memory requirements of the exception handling routines,
|
4558 |
|
|
+ * which can be substantial if the ISA contains a lot of registers that are not
|
4559 |
|
|
+ * call-saved.
|
4560 |
|
|
+ *
|
4561 |
|
|
+ * If this macro is not defined, it defaults to FIRST_PSEUDO_REGISTER.
|
4562 |
|
|
+ *
|
4563 |
|
|
+ * ZipCPU --- The default is not sufficient. The CC and PC registers need to
|
4564 |
|
|
+ * be saved and examined as well in any debug/exception context. Hence, we
|
4565 |
|
|
+ * define this to be all of our registers.
|
4566 |
|
|
+ */
|
4567 |
|
|
+#undef DWARF_FRAME_REGISTERS
|
4568 |
|
|
+#define DWARF_FRAME_REGISTERS 16
|
4569 |
|
|
+
|
4570 |
|
|
+/* PRE_GCC3_DWARF_FRAME_REGISTERS ... This macro is similar to DWARF_FRAME_REG..
|
4571 |
|
|
+ * but is provided for backward compatibility in pre GCC 3.0 compiled code.
|
4572 |
|
|
+ *
|
4573 |
|
|
+ * If not defined, it defaults to DWARF_FRAME_REGISTERS---which is perfect for
|
4574 |
|
|
+ * the ZipCPU.
|
4575 |
|
|
+ */
|
4576 |
|
|
+
|
4577 |
|
|
+/* DWARF_REG_TO_UNWIND_COLUMN(REGNO) ... Define this macro if the target's
|
4578 |
|
|
+ * representation for dwarf registers is different than the internal
|
4579 |
|
|
+ * representation for unwind column. Given a dwarf register, this macro should
|
4580 |
|
|
+ * return the unwind column number to use instead.
|
4581 |
|
|
+ *
|
4582 |
|
|
+ * ... ???
|
4583 |
|
|
+ */
|
4584 |
|
|
+
|
4585 |
|
|
+/* DWARF_FRAME_REGNUM(REGNO) ... Define this macro is the target's
|
4586 |
|
|
+ * representation for dwarf registers used in .eh_frame or .debug_frame is
|
4587 |
|
|
+ * different from that used in other debug info sections. Given a GCC hard
|
4588 |
|
|
+ * register number, this macro should return the .eh_frame register number.
|
4589 |
|
|
+ * The default is DBX_REGISTER_NUMBER(REGNO).
|
4590 |
|
|
+ *
|
4591 |
|
|
+ * ZipCPU --- provided we define DBX_REGISTER_NUMBER(REGNO) well, this default
|
4592 |
|
|
+ * should still work for us.
|
4593 |
|
|
+ */
|
4594 |
|
|
+
|
4595 |
|
|
+/* DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) ... Define this macro to map register
|
4596 |
|
|
+ * numbers held in the call frame info that GCC has collected using
|
4597 |
|
|
+ * DWARF_FRAME_REGNO to those that should be output in .debug_frame (for_eh is
|
4598 |
|
|
+ * zero) and .eh_frame (for_eh is non-zero). The default is to return REGNO.
|
4599 |
|
|
+ *
|
4600 |
|
|
+ * ZipCPU --- Default is good enough.
|
4601 |
|
|
+ */
|
4602 |
|
|
+
|
4603 |
|
|
+/* REG_VALUE_IN_UNWIND_CONTEXT ... Define this macro if the target stores
|
4604 |
|
|
+ * register values as _Unwind_Word type in unwind context. It should be defined
|
4605 |
|
|
+ * if target register size is larger than the size of void *. The default
|
4606 |
|
|
+ * is to store register values as void *type.
|
4607 |
|
|
+ *
|
4608 |
|
|
+ * ZipCPU --- Default is what we need.
|
4609 |
|
|
+ */
|
4610 |
|
|
+
|
4611 |
|
|
+/* ASSUME_EXTENDED_UNWIND_CONTEXT ... Define this macro to be 1 if the target
|
4612 |
|
|
+ * always uses extended unwind context with version, args_size, and by_value
|
4613 |
|
|
+ * fields. If it is undefined, it will always be defined to 1 when REG_VALUE_IN_UNWIND_CONTEXT is defined and 0 otherwise.
|
4614 |
|
|
+ *
|
4615 |
|
|
+ */
|
4616 |
|
|
+
|
4617 |
|
|
+
|
4618 |
|
|
+/* 17.09.05 Eliminating Frame Pointer and Arg Pointer */
|
4619 |
|
|
+
|
4620 |
|
|
+/* TARGET_FRAME_POINTER_REQUIRED(VOID) ... This target hook should return true
|
4621 |
|
|
+ * if a function must have and use a frame pointer. This target hook is
|
4622 |
|
|
+ * called in the reload pass. If its return value is true, the function will
|
4623 |
|
|
+ * have a frame pointer.
|
4624 |
|
|
+ *
|
4625 |
|
|
+ * This target hook can in principle examine the current function and decide
|
4626 |
|
|
+ * according to the facts, but on most machines the constant false or the
|
4627 |
|
|
+ * constant true suffices. Use false when the machine allows code to be
|
4628 |
|
|
+ * generated with no frame pointer, and doing so saves some time or space.
|
4629 |
|
|
+ * Use true when there is no possible advantage to avoiding a frame pointer.
|
4630 |
|
|
+ *
|
4631 |
|
|
+ * ZipCPU---if we add in a frame pointer, we become register starved. Hence,
|
4632 |
|
|
+ * we'll treat this as a constant false--which is also the default value.
|
4633 |
|
|
+ */
|
4634 |
|
|
+#define target_frame_pointer_required zip_frame_pointer_required
|
4635 |
|
|
+
|
4636 |
|
|
+/* INITIAL_FRAME_POINTER_OFFSET ... A C statement to store in the variable
|
4637 |
|
|
+ * depth-var the difference between the frame pointer and the stack pointer
|
4638 |
|
|
+ * values immediately after the function prologue. The value would be computed
|
4639 |
|
|
+ * from information such as the result of get_frame_size() and the tables of
|
4640 |
|
|
+ * registers regs_ever_live and call_used_regs.
|
4641 |
|
|
+ *
|
4642 |
|
|
+ * If ELIMINABLE_REGS is defined, this macro will not be used and need not be
|
4643 |
|
|
+ * defined. Otherwise, it must be defined even if TARGET_FRAME_POINTER_REQD
|
4644 |
|
|
+ * always returns true; in that case you may set depth-var to anything.
|
4645 |
|
|
+ *
|
4646 |
|
|
+ * ZipCPU --- we intend to set ELIMINABLE_REGS, so this is not necessary.
|
4647 |
|
|
+ */
|
4648 |
|
|
+// #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0
|
4649 |
|
|
+
|
4650 |
|
|
+
|
4651 |
|
|
+/* ELIMINABLE_REGS ... If defined, this macro specifies a table of register
|
4652 |
|
|
+ * pairs used to eliminate unneeded registers that point into the stack frame.
|
4653 |
|
|
+ * If it is not defined, the only elimination attempted by the compiler is to
|
4654 |
|
|
+ * replace references to the frame pointer with references to the stack pointer.
|
4655 |
|
|
+ *
|
4656 |
|
|
+ * On some machines, the position of the argument pointer is not known until
|
4657 |
|
|
+ * the compilation is completed. In such a case, a separate hard register
|
4658 |
|
|
+ * must be used for the argument pointer. This register can be eliminated by
|
4659 |
|
|
+ * replacing it with either the frame pointer or the argument pointer,
|
4660 |
|
|
+ * depending on whether or not the frame pointer has been eliminated.
|
4661 |
|
|
+ *
|
4662 |
|
|
+ * ZipCPU we'll take their suggestion and define this as:
|
4663 |
|
|
+ */
|
4664 |
|
|
+#undef ELIMINABLE_REGS
|
4665 |
|
|
+#define ELIMINABLE_REGS \
|
4666 |
|
|
+ {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
|
4667 |
|
|
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
|
4668 |
|
|
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
|
4669 |
|
|
+
|
4670 |
|
|
+/* bool TARGET_CAN_ELIMINATE(FROM,TO) ... This target function should return
|
4671 |
|
|
+ * true if the compiler is allowed to try to replace register number FROM with
|
4672 |
|
|
+ * register number TO. This target hook need only be defined if ELIMINABLE_REGS
|
4673 |
|
|
+ * is defined, and will usually return true since most of the cases preventing
|
4674 |
|
|
+ * register elimination are things that the compiler already knows about.
|
4675 |
|
|
+ *
|
4676 |
|
|
+ * ZipCPU ... does the compiler know about my decision as to whether or not
|
4677 |
117 |
dgisselq |
+ * the frame pointer was needed? Yes it does, but it's kept separately. We'll
|
4678 |
|
|
+ * just say everything can be eliminated.
|
4679 |
102 |
dgisselq |
+ */
|
4680 |
|
|
+#define TARGET_CAN_ELIMINATE zip_can_eliminate
|
4681 |
|
|
+
|
4682 |
|
|
+/* INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) ... This macro is similar to
|
4683 |
|
|
+ * INITIAL_FRAME_POINTER_OFFSET. It specifies the initial difference between
|
4684 |
|
|
+ * the specified pair of registers. This macro must be defined if
|
4685 |
|
|
+ * ELIMINABLE_REGS is defined.
|
4686 |
|
|
+ *
|
4687 |
117 |
dgisselq |
+ * ZipCPU---We had at one time set this to a default offset of 0. This didn't
|
4688 |
|
|
+ * work. It turns out that this is not only the *initial* elimination offset,
|
4689 |
|
|
+ * but also the offset along the way. Hence, when a variable needs to be
|
4690 |
|
|
+ * spilled to the stack, this offset must change. Reload goes and checks for
|
4691 |
|
|
+ * this, and adjusts registers if the offset has changed. Hence, without this,
|
4692 |
|
|
+ * we get negative (i.e. illegal) stack offsets.
|
4693 |
102 |
dgisselq |
+ */
|
4694 |
|
|
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
4695 |
|
|
+ do { (OFFSET) = zip_initial_elimination_offset((FROM), (TO)); } \
|
4696 |
|
|
+ while(0) \
|
4697 |
|
|
+
|
4698 |
|
|
+/* 17.09.06 Passing function arguments on the stack */
|
4699 |
|
|
+
|
4700 |
|
|
+/* TARGET_PROMOTE_PROTOTYPES ... Returns true if an argument declared in a
|
4701 |
|
|
+ * prototype as an integral type smaller than int should actually be
|
4702 |
|
|
+ * passed as an int. In addition to avoiding errors in certain cases of
|
4703 |
|
|
+ * mismatch, it also makes for better code on certain machines. The default is
|
4704 |
|
|
+ * to not promote prototypes.
|
4705 |
|
|
+ *
|
4706 |
|
|
+ * Since everything is an int on the ZipCPU, let's promote anything smaller
|
4707 |
|
|
+ * (which should still be an int) up to an int anyway.
|
4708 |
|
|
+ */
|
4709 |
|
|
+#undef TARGET_PROMOTE_PROTOTYPES
|
4710 |
|
|
+#define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
|
4711 |
|
|
+
|
4712 |
|
|
+/* PUSH_ARGS ... A C expression. If nonzero, push instructions will be used to
|
4713 |
|
|
+ * pass outgoing arguments. If the target machine does not have a push
|
4714 |
|
|
+ * instruction, set it to zero. That directs GCC to use an alternate strategy:
|
4715 |
|
|
+ * to allocate the entire argument block and then store the arguments into it.
|
4716 |
|
|
+ * When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too.
|
4717 |
|
|
+ *
|
4718 |
|
|
+ * ZipCPU does not have a push instruction, so we set this to zero.
|
4719 |
|
|
+ */
|
4720 |
|
|
+#undef PUSH_ARGS
|
4721 |
|
|
+#define PUSH_ARGS 0
|
4722 |
|
|
+
|
4723 |
|
|
+/* PUSH_ARGS_REVERSED ... A C expression. If nonzero, function arguments will
|
4724 |
|
|
+ * be evaluated last to first, rather than first to last. If this macro is
|
4725 |
|
|
+ * not defined, it defaults to PUSH_ARGS on targets where the stack and args
|
4726 |
|
|
+ * grow in opposite directions, and zero otherwise.
|
4727 |
|
|
+ *
|
4728 |
|
|
+ * ZipCPU---Let's evaluate our arguments first to last.
|
4729 |
|
|
+ */
|
4730 |
|
|
+#define PUSH_ARGS_REVERSED 1
|
4731 |
|
|
+
|
4732 |
|
|
+/* PUSH_ROUNDING(NPUSHED) ... A C expression that is the number of bytes
|
4733 |
|
|
+ * actually pushed onto the stack when an instruction attempts to push
|
4734 |
|
|
+ * (NPUSHED) bytes.
|
4735 |
|
|
+ *
|
4736 |
|
|
+ * ZipCPU---We cannot push bytes. Let's leave this undefined and see what
|
4737 |
|
|
+ * happens.
|
4738 |
|
|
+ */
|
4739 |
|
|
+// #warning "No appropriate definition seemed right."
|
4740 |
|
|
+
|
4741 |
|
|
+/* ACCUMULATE_OUTGOING_ARGS ... A C expression. If non-zero, the maximum amount
|
4742 |
|
|
+ * of space required for outgoing arguments will be computed and placed into
|
4743 |
171 |
dgisselq |
+ * crtl->outgoing_args_size. No space will be pushed onto the stack for each
|
4744 |
|
|
+ * call; instead the function prologue should increase the stack frame size by
|
4745 |
|
|
+ * this amount.
|
4746 |
102 |
dgisselq |
+ *
|
4747 |
|
|
+ * ZipCPU---This is *cool* and so necessary---it saves an extra two instructions
|
4748 |
|
|
+ * each time we try to call a function/routine. Yes, we want and *need* this
|
4749 |
|
|
+ * for good performance. I mean, think of it, free performance increase? Who
|
4750 |
|
|
+ * could argue with that?
|
4751 |
|
|
+ */
|
4752 |
|
|
+#undef ACCUMULATE_OUTGOING_ARGS
|
4753 |
|
|
+#define ACCUMULATE_OUTGOING_ARGS 1
|
4754 |
|
|
+
|
4755 |
|
|
+
|
4756 |
|
|
+/* REG_PARM_STACK_SPACCE(FN) ... Define this macro if functions should assume
|
4757 |
|
|
+ * that stack space has been allocated for arguments even when their values
|
4758 |
|
|
+ * are passed in registers. The value of this macro is the size, in bytes, of
|
4759 |
|
|
+ * the area reserved for arguments passed in registers for the function
|
4760 |
|
|
+ * represented by FN, which can be zero if GCC is calling a library function.
|
4761 |
|
|
+ * The argument FN can be the FUNCTION_DECL, or the type itself of the function.
|
4762 |
|
|
+ *
|
4763 |
|
|
+ * This space can be allocated by the caller, or be part of the machine
|
4764 |
|
|
+ * dependent stack frame: OUTGOING_REG_PARM_STACK_SPACE says which.
|
4765 |
|
|
+ *
|
4766 |
|
|
+ * ZipCPU --- Why allocate space you won't use? Let's leave this undefined
|
4767 |
|
|
+ * therefore.
|
4768 |
|
|
+ */
|
4769 |
|
|
+// #undef REG_PARM_STACK_SPACE
|
4770 |
|
|
+
|
4771 |
|
|
+
|
4772 |
|
|
+
|
4773 |
|
|
+/* INCOMING_REG_PARM_STACK_SPACE(FN) ... Like REG_PARM_STACK_SPACE, but for
|
4774 |
|
|
+ * incoming register arguments. Define this macro if space guaranteed when
|
4775 |
|
|
+ * compiling a function body is different to space required when making a call,
|
4776 |
|
|
+ * a situation that can arise with K&R style function definitions.
|
4777 |
|
|
+ *
|
4778 |
|
|
+ */
|
4779 |
|
|
+
|
4780 |
|
|
+/* OUTGOING_REG_PARM_STACK_SPACE(FN) ... Define this to a nonzero value if it
|
4781 |
|
|
+ * is the responsibility of the caller to allocate the area reserved for
|
4782 |
|
|
+ * arguments passed in registers when calling a function of FN. FN may be NULL
|
4783 |
|
|
+ * if the function called is a library function.
|
4784 |
|
|
+ *
|
4785 |
|
|
+ * ZipCPU---Why allocate space you don't need?
|
4786 |
|
|
+ */
|
4787 |
|
|
+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 0
|
4788 |
|
|
+
|
4789 |
|
|
+
|
4790 |
|
|
+/* STACK_PARMS_IN_REG_PARM_AREA ... Define this macro if REG_PARM_STACK_SPACE
|
4791 |
|
|
+ * is defined, buyt the stack parameters don't skip the area specified by it.
|
4792 |
|
|
+ *
|
4793 |
|
|
+ * ZipCPU---We didn't define REG_PARM_STACK_SPACE, so we won't define this.
|
4794 |
|
|
+ */
|
4795 |
|
|
+
|
4796 |
|
|
+/* TARGET_RETURN_POPS_ARGS(DECL,FNTYPE,SZ) ... This target hook returns the
|
4797 |
|
|
+ * number of bytes of its own arguments that a function pops on returning, or 0
|
4798 |
|
|
+ * if the function pops no arguments and the caller must therefore pop them all
|
4799 |
|
|
+ * after the function returns.
|
4800 |
|
|
+ *
|
4801 |
|
|
+ * ZipCPU --- If we define this, we'll lose our gain from
|
4802 |
|
|
+ * ACCUMULATE_OUTOING_ARGS. Thus, we leave this undefined.
|
4803 |
|
|
+ */
|
4804 |
|
|
+
|
4805 |
|
|
+/* CALL_POPS_ARGS(CUM) ... A C expression that should indicate the number of
|
4806 |
|
|
+ * bytes a call sequence pops off of the stack. It is added to the value of
|
4807 |
|
|
+ * RETURN_POPS_ARGS when compiling a function call. CUM is the variable in
|
4808 |
|
|
+ * which all arguments to the function have been accumulated.
|
4809 |
|
|
+ *
|
4810 |
|
|
+ * ZipCPU---The call sequence, by itself, doesn't touch the stack. Therefore
|
4811 |
|
|
+ * this is zero.
|
4812 |
|
|
+ */
|
4813 |
|
|
+#undef CALL_POPS_ARGS
|
4814 |
|
|
+#define CALL_POPS_ARGS(CUM) 0
|
4815 |
|
|
+
|
4816 |
|
|
+
|
4817 |
|
|
+/* 17.09.07 Passing arguments in registers */
|
4818 |
|
|
+
|
4819 |
|
|
+/* TARGET_FUNCTION_ARG ... Return an RTX indicating whether a function argument
|
4820 |
|
|
+ * is passed in a register, and if so, which register.
|
4821 |
|
|
+ */
|
4822 |
|
|
+/*
|
4823 |
|
|
+ * This has been poisoned ... so let's not define it anymore and look for
|
4824 |
|
|
+ * a better way to do this ...
|
4825 |
|
|
+ *
|
4826 |
|
|
+ * #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) (((NAMED) == 0) ? NULL_RTX
|
4827 |
|
|
+ * : targetm.calls.must_pass_in_stack(MODE, TYPE) ? NULL_RTX
|
4828 |
|
|
+ * : (CUM) > ZIP_LAST_ARG_REGNO ? NULL_RTX
|
4829 |
|
|
+ * : gen_rtx_REG(MODE, CUM))
|
4830 |
|
|
+ */
|
4831 |
|
|
+#define TARGET_FUNCTION_ARG zip_function_arg
|
4832 |
|
|
+
|
4833 |
|
|
+
|
4834 |
171 |
dgisselq |
+/* TARGET_MUST_PASS_IN_STACK(MODE, TYPE) ... This target hook should return
|
4835 |
|
|
+ * true if we should not pass TYPE solely in registers. The file 'expr.h'
|
4836 |
|
|
+ * defines a definition that is usually appropriate, refer to 'expr.h' for
|
4837 |
|
|
+ * additional documentation.
|
4838 |
|
|
+ *
|
4839 |
|
|
+ * ZipCPU ... Ok, so I looked into expr.h and didn't find anything that looked
|
4840 |
|
|
+ * like this. So ... I don't know.
|
4841 |
102 |
dgisselq |
+ */
|
4842 |
|
|
+// #undef TARGET_MUST_PASS_IN_STACK
|
4843 |
|
|
+// #define TARGET_MUST_PASS_IN_STACK zip_must_pass_in_stack
|
4844 |
|
|
+
|
4845 |
|
|
+/* TARGET_FUNCTION_INCOMING_ARG ... Define this hook if the target machine
|
4846 |
|
|
+ * has register windows, ... which ZipCPU does not have.
|
4847 |
|
|
+ */
|
4848 |
|
|
+
|
4849 |
|
|
+/* TARGET_USE_PSEUDO_PIC_REG(void) ... This hook should return 1 in case
|
4850 |
|
|
+ * pseudo register should be created for pic_offset_table_rtx during function
|
4851 |
|
|
+ * expand.
|
4852 |
|
|
+ *
|
4853 |
|
|
+ * This should be defined by global parameters, isn't it?
|
4854 |
|
|
+ */
|
4855 |
|
|
+
|
4856 |
|
|
+/* TARGET_INIT_PIC_REG(v) ... Perform a target dependent initialization of
|
4857 |
|
|
+ * pic_offset_table_rtx. This hook is called at the start of register
|
4858 |
|
|
+ * allocation.
|
4859 |
|
|
+ *
|
4860 |
|
|
+ * ZipCPU---Let's revisit this.
|
4861 |
|
|
+ */
|
4862 |
|
|
+// #warning "Come back and relook at relocations"
|
4863 |
|
|
+
|
4864 |
|
|
+/* TARGET_ARG_PARTIAL_BYTES ... This target hook returns the number of bytes
|
4865 |
|
|
+ * at the beginning of an argument that must be put in registers. The value
|
4866 |
|
|
+ * must be zero for arguments that are passed entirely in registers or that
|
4867 |
|
|
+ * are entirely pushed on the stack.
|
4868 |
|
|
+ */
|
4869 |
|
|
+// #undef TARGET_ARG_PARTIAL_BYTES
|
4870 |
|
|
+// #define TARGET_ARG_PARTIAL_BYTES zip_arg_partial_bytes
|
4871 |
|
|
+
|
4872 |
|
|
+/* TARGET_PASS_BY_REFERENCE(CUM,MOD,TREE,NAMED) ... This target hook should
|
4873 |
|
|
+ * return true if an argument at the position indicated by CUM should be passed
|
4874 |
|
|
+ * by reference. This predicate is queried after target independent reasons
|
4875 |
|
|
+ * for being pssed by reference, such as TREE_ADDRESSABLE(TREE).
|
4876 |
|
|
+ *
|
4877 |
|
|
+ */
|
4878 |
|
|
+// #undef TARGET_PASS_BY_REFERENCE
|
4879 |
|
|
+// #define TARGET_PASS_BY_REFERENCE zip_pass_by_reference
|
4880 |
|
|
+
|
4881 |
|
|
+/* CUMULATIVE ARGS ... A C type for declaring a variable that is used as the
|
4882 |
|
|
+ * first argument of 'FUNCTION_ARG' and other related values.
|
4883 |
|
|
+ *
|
4884 |
|
|
+ * ZipCPU---We're in trouble if an 'int' won't work, so let's just use that.
|
4885 |
|
|
+ */
|
4886 |
|
|
+#define CUMULATIVE_ARGS int
|
4887 |
|
|
+
|
4888 |
|
|
+/*
|
4889 |
|
|
+ * OVERRIDE_ABI_FORMAT
|
4890 |
|
|
+ */
|
4891 |
|
|
+
|
4892 |
|
|
+/* INIT_CUMULATIVE_ARGS ... A C statement (sans semicolon) for initializing the
|
4893 |
|
|
+ * variable CUM for the state at the beginning of the argument list.
|
4894 |
|
|
+ *
|
4895 |
|
|
+ *
|
4896 |
|
|
+ * ZipCPU---The first argument is passed in register ZIP_FIRST_ARG_REGNO, or
|
4897 |
|
|
+ * R1 (unless it has been redefined above ...)
|
4898 |
|
|
+ */
|
4899 |
|
|
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) (CUM = 0)
|
4900 |
|
|
+
|
4901 |
|
|
+/* INIT_CUMULATIVE_LIBCALL_ARGS
|
4902 |
|
|
+ * INIT_CUMULATIVE_INCOMING_ARGS
|
4903 |
|
|
+ *
|
4904 |
|
|
+ * These default to the last INIT_CUM_ARGS value above.
|
4905 |
|
|
+ */
|
4906 |
|
|
+
|
4907 |
|
|
+/* TARGET_FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) .. This hook updates
|
4908 |
|
|
+ * the summarizer variable pointed to by CUM to advance past an argument in
|
4909 |
|
|
+ * the argument list. The values MODE, TYPE, and NAMED describe that
|
4910 |
|
|
+ * argument. Once this is done, the variable CUM is suitable for analyzing the
|
4911 |
|
|
+ * following argument with TARGET_FUNCTION_ARG, etc. This hook need not do
|
4912 |
|
|
+ * anything if the argument in question was passed on the stack. The compiler
|
4913 |
|
|
+ * knows how to track the amount of stack space used for arguments without
|
4914 |
|
|
+ * any special help.
|
4915 |
|
|
+ *
|
4916 |
|
|
+ * ZipCPU---Here we simply copy from ECO32.
|
4917 |
|
|
+ */
|
4918 |
|
|
+#define TARGET_FUNCTION_ARG_ADVANCE zip_function_arg_advance
|
4919 |
|
|
+
|
4920 |
|
|
+/*
|
4921 |
171 |
dgisselq |
+ * TARGET_ARG_OFFSET(MODE, TYPE) ... If defined, a C expression that is the
|
4922 |
|
|
+ * number of bytes to add to the offset of the argument passed in memory.
|
4923 |
|
|
+ * This is needed for the SPU, which passes char and short arguments in the
|
4924 |
|
|
+ * preferred slot that is in the middle of the quad word instead of starting
|
4925 |
|
|
+ * at the top.
|
4926 |
|
|
+ *
|
4927 |
|
|
+ * ZipCPU -- sounds like the default would be (more) appropriate.
|
4928 |
|
|
+ */
|
4929 |
|
|
+/*
|
4930 |
102 |
dgisselq |
+ * FUNCTION_ARG_PADDING --- not necessary, since we shouldn't be padding
|
4931 |
|
|
+ * PAD_VARARGS_DOWN --- not necessary, since we shouldn't be padding
|
4932 |
|
|
+ * BLOCK_REG_PADDING
|
4933 |
|
|
+ * TARGET_FUNCTION_ARG_BOUNDARY
|
4934 |
|
|
+ * TARGET_FUNCTION_ARG_ROUND_BOUNDARY
|
4935 |
|
|
+ */
|
4936 |
|
|
+
|
4937 |
|
|
+/* FUNCTION_ARG_REGNO_P(REGNO) ... A C expression that is nonzero if REGNO is
|
4938 |
|
|
+ * the number of a hard register in which function arguments are sometimes
|
4939 |
|
|
+ * passed. This does not include implicit arguments such as the static chain
|
4940 |
|
|
+ * and the structure-value address. On many machines, no registers can be used
|
4941 |
|
|
+ * for this purpose since all function arguments are pushed on the stack.
|
4942 |
|
|
+ */
|
4943 |
|
|
+#define FUNCTION_ARG_REGNO_P(r) ((r >= ZIP_FIRST_ARG_REGNO)&&(r<=ZIP_LAST_ARG_REGNO))
|
4944 |
|
|
+
|
4945 |
|
|
+/* TARGET_SPLIT_COMPLEX_ARG(TYPE) ... This hook should return true if parameter
|
4946 |
|
|
+ * of type TYPE are passed as two scalar parameters. By default, GCC will
|
4947 |
|
|
+ * attempt to pack complex arguments into the target's word size. Some ABI's
|
4948 |
|
|
+ * require complex arguments to be split and treated as their individual
|
4949 |
|
|
+ * components.
|
4950 |
|
|
+ *
|
4951 |
|
|
+ * The default value of this hook is NULL, which is treated as always false,
|
4952 |
|
|
+ * and which should be good enough for ZipCPU--which can go either way.
|
4953 |
|
|
+ */
|
4954 |
|
|
+
|
4955 |
|
|
+/* TARGET_BUILD_BUILTIN_VA_LIST ... This hook returns a type node for va_list
|
4956 |
|
|
+ * for the target. The default version of the hook returns void*.
|
4957 |
|
|
+ *
|
4958 |
|
|
+ */
|
4959 |
|
|
+
|
4960 |
|
|
+/* TARGET_ENUM_VA_LIST_P
|
4961 |
|
|
+ */
|
4962 |
|
|
+
|
4963 |
|
|
+/* TARGET_FN_ABI_VA_LIST ... This hook returns the va_list type of the calling
|
4964 |
|
|
+ * convention specified by FN. The default version of this returns va_list_type_node.
|
4965 |
|
|
+ */
|
4966 |
|
|
+
|
4967 |
|
|
+/* TARGET_FN_ABI_VA_LIST
|
4968 |
|
|
+ */
|
4969 |
|
|
+
|
4970 |
|
|
+/* TARGET_CANONICAL_VA_LIST_TYPE
|
4971 |
|
|
+ */
|
4972 |
|
|
+
|
4973 |
|
|
+/* TARGET_GIMPLIFY_VA_ARG_EXPR
|
4974 |
|
|
+ */
|
4975 |
|
|
+
|
4976 |
|
|
+/* TARGET_VALID_POINTER_MODE(MODE) ... Define this to return nonzero if the
|
4977 |
|
|
+ * port can handle pointers with machine mode MODE. The default version of this
|
4978 |
|
|
+ * hook returns true for both ptr_mode and Pmode.
|
4979 |
|
|
+ *
|
4980 |
|
|
+ * ZipCPU---if Pmode is properly defined (above, and I think it is), then the
|
4981 |
|
|
+ * default behavior is quite appropriate.
|
4982 |
|
|
+ */
|
4983 |
|
|
+
|
4984 |
|
|
+/* TARGET_REF_MAY_ALIAS_ERRNO(REFP) ... Define this to return nonzero if the
|
4985 |
|
|
+ * memory reference REF may alias with the system C library errno location.
|
4986 |
|
|
+ * The default version of this hook assumes the system C library errno location
|
4987 |
|
|
+ * is either a declaration of type int or accessed by dereferencing a pointer
|
4988 |
|
|
+ * to int.
|
4989 |
|
|
+ *
|
4990 |
|
|
+ * ZipCPU --- Default sounds good to me.
|
4991 |
|
|
+ */
|
4992 |
|
|
+
|
4993 |
|
|
+
|
4994 |
|
|
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
|
4995 |
|
|
+ * the port is prepared to handl instructions involving scalar mode MODE. For
|
4996 |
|
|
+ * a scalar mode to be considered supported, all the basic arithmetic and
|
4997 |
|
|
+ * comparisons must work.
|
4998 |
|
|
+ *
|
4999 |
|
|
+ * The default version of this hook returns true for any mode required to
|
5000 |
|
|
+ * handle the basic C types (as defined by the port). Included here are the
|
5001 |
|
|
+ * double-word arithmetic supported by the code in optabs.c.
|
5002 |
|
|
+ */
|
5003 |
|
|
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
|
5004 |
|
|
+#define TARGET_SCALAR_MODE_SUPPORTED_P zip_scalar_mode_supported_p
|
5005 |
|
|
+
|
5006 |
|
|
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
|
5007 |
|
|
+ * port is prepared to handle instructions involving vector mode MODE. At the
|
5008 |
|
|
+ * very least, it must have move patterns for this mode.
|
5009 |
|
|
+ *
|
5010 |
|
|
+ * ZipCPU---does not support any vector modes.
|
5011 |
|
|
+ */
|
5012 |
|
|
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
|
5013 |
|
|
+#define TARGET_VECTOR_MODE_SUPPORTED_P hook_bool_mode_false
|
5014 |
|
|
+
|
5015 |
|
|
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
|
5016 |
|
|
+ * try to use a scalar mode to store an array of NELEMS elements, given that
|
5017 |
|
|
+ * each element has mode MODE. Returning true here overrides the usual MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
|
5018 |
|
|
+ *
|
5019 |
|
|
+ * ZipCPU---Sounds good.
|
5020 |
|
|
+ */
|
5021 |
|
|
+// #undef TARGET_ARRAY_MODE_SUPPORTED_P
|
5022 |
|
|
+// #define TARGET_ARRAY_MODE_SUPPORTED_P zip_array_mode_supported_p
|
5023 |
|
|
+
|
5024 |
|
|
+/* TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P(MODE) ... Define this to return
|
5025 |
|
|
+ * nonzero if libgcc provides support for the floating-point mode MODE, which is
|
5026 |
|
|
+ * known to pass TARGET_SCALAR_MODE_SUPPORTED_P. The default version of this
|
5027 |
|
|
+ * hook returns true for all of SFmode, DFmode, XFmode, and TFmode, if such
|
5028 |
|
|
+ * modes exist.
|
5029 |
|
|
+ *
|
5030 |
|
|
+ * ZipCPU---We only support SFmode and DFmode, but for now only in emulation
|
5031 |
|
|
+ * (if we can). Let's allow both of those and see how far we get.
|
5032 |
|
|
+ */
|
5033 |
|
|
+#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
|
5034 |
|
|
+#define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P zip_libgcc_floating_mode_supported_p
|
5035 |
|
|
+
|
5036 |
|
|
+/* TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P(MODE) ... Define this to return
|
5037 |
|
|
+ * nonzero for machine modes for which the port has small register classes. If
|
5038 |
|
|
+ * target hook returns nonzero for a given MODE, the compiler will try to
|
5039 |
|
|
+ * minimize the lifetime of registers in MODE. The hook may be called with
|
5040 |
|
|
+ * VOIDmode as an argument. In this case, the hook is expected to return
|
5041 |
|
|
+ * nonzero if it returns nonzero for any mode.
|
5042 |
|
|
+ *
|
5043 |
|
|
+ * The default version of this hook returns false for any mode.
|
5044 |
|
|
+ *
|
5045 |
|
|
+ * ZipCPU---Default sounds good.
|
5046 |
|
|
+ */
|
5047 |
|
|
+
|
5048 |
|
|
+/* 17.09.08 How scalar function values are returned */
|
5049 |
|
|
+
|
5050 |
|
|
+/* TARGET_FUNCTION_VALUE
|
5051 |
|
|
+ */
|
5052 |
|
|
+
|
5053 |
|
|
+/* LIBCALL_VALUE
|
5054 |
|
|
+ */
|
5055 |
|
|
+
|
5056 |
|
|
+
|
5057 |
|
|
+/* 17.09.09 How large values are returned */
|
5058 |
|
|
+
|
5059 |
|
|
+/* TARGET_RETURN_IN_MEMORY(TYP,FNTYP) ... This target hook should return a
|
5060 |
|
|
+ * nonzero value to say to return the function value in memory, just as large
|
5061 |
|
|
+ * structures are always returned. Here type will be the data type of the value
|
5062 |
|
|
+ * and FNTYP will be the type of the function doing the returning, or NULL
|
5063 |
|
|
+ * for libcalls.
|
5064 |
|
|
+ *
|
5065 |
|
|
+ */
|
5066 |
|
|
+#undef TARGET_RETURN_IN_MEMORY
|
5067 |
|
|
+#define TARGET_RETURN_IN_MEMORY zip_return_in_memory
|
5068 |
|
|
+
|
5069 |
|
|
+/* DEFAULT_PCC_STRUCT_RETURN
|
5070 |
|
|
+ * TARGET_STRUCT_VALUE_RTX
|
5071 |
|
|
+ * PCC_STATIC_STRUCT_RETURN
|
5072 |
|
|
+ * TARGET_GET_RAW_RESULT_MODE
|
5073 |
|
|
+ * TARGET_GET_RAW_ARG_MODE
|
5074 |
|
|
+ */
|
5075 |
|
|
+
|
5076 |
|
|
+
|
5077 |
|
|
+/* 17.09.10 Caller-Saves Register Allocation */
|
5078 |
|
|
+/* 17.09.11 Function Entry and Exit */
|
5079 |
111 |
dgisselq |
+// TARGET_ASM_FUNCTION_PROLOGUE
|
5080 |
|
|
+// TARGET_ASM_FUNCTION_END_PROLOGUE
|
5081 |
|
|
+// TARGET_ASM_FUNCCTION_BEGIN_EPILOGUE
|
5082 |
|
|
+// TARGET_ASM_FUNCTION_EPILOGUE
|
5083 |
|
|
+/* EXIT_IGNORE_STACK ... Define this macro as a C expression that is nonzero
|
5084 |
|
|
+ * if the return instruction or the function epilogue ignores the value of the
|
5085 |
|
|
+ * stack pointer; in other words, if it is safe to delete an instruction to
|
5086 |
|
|
+ * adjust the stack pointer before a return from the function.
|
5087 |
|
|
+ *
|
5088 |
|
|
+ * The default is 0.
|
5089 |
|
|
+ *
|
5090 |
|
|
+ * Note that this macro's value is relevant only for functions for which frame
|
5091 |
|
|
+ * pointers are maintained. It is never safe to delete a final stack adjustment
|
5092 |
|
|
+ * in a function that has no frame pointer, and the compiler knows this
|
5093 |
|
|
+ * regardless of EXIT_IGNORE_STACK.
|
5094 |
|
|
+ *
|
5095 |
|
|
+ * ZipCPU -- Thanks to the example of the m68k, and a careful selection of what
|
5096 |
|
|
+ * our options otherwise could have been, our epilogue code does not use the
|
5097 |
|
|
+ * stack register at all, but rather starts by moving the frame register into
|
5098 |
|
|
+ * the stack register.
|
5099 |
|
|
+ */
|
5100 |
|
|
+#define EXIT_IGNORE_STACK 1
|
5101 |
|
|
+// EPILOGUE_USES(regno)
|
5102 |
|
|
+// EH_USES(regno)
|
5103 |
|
|
+// TARGET_ASM_OUTPUT_MI_THUNK
|
5104 |
|
|
+// TARGET_ASM_CAN_OUTPUT_MI_THUNK
|
5105 |
|
|
+
|
5106 |
102 |
dgisselq |
+/* 17.09.12 Generating code for profiling */
|
5107 |
111 |
dgisselq |
+// FUNCTION_PROFILER
|
5108 |
|
|
+// PROFILE_HOOK
|
5109 |
|
|
+// NO_PROFILE_COUNTERS
|
5110 |
|
|
+// PROFILE_BEFORE_PROLOGUE
|
5111 |
|
|
+// TARGET_KEEP_LEAF_WHEN_PROFILED
|
5112 |
|
|
+
|
5113 |
102 |
dgisselq |
+/* 17.09.13 Permitting tail calls*/
|
5114 |
111 |
dgisselq |
+
|
5115 |
|
|
+/* TARGET_FUNCTION_OK_FOR_SIBCALL(DECL,EXP) ... True if it is OK to do sibling
|
5116 |
|
|
+ * call optimizations for the specified call expression EXP. DECL will be the
|
5117 |
|
|
+ * called function, or NULL if this is an indirect call.
|
5118 |
|
|
+ *
|
5119 |
|
|
+ * It is not uncommon for limitations of calling conventions to prevent tail
|
5120 |
|
|
+ * calls to functions outside the current unit of translation, or during PIC
|
5121 |
|
|
+ * compilation. The hook is used to enforce these restrictions, as the sibcall
|
5122 |
|
|
+ * md pattern can not fail, or fall over to a 'normal' call. The criteria for
|
5123 |
|
|
+ * successful sibling call optimization may vary greatly between different
|
5124 |
|
|
+ * architectures.
|
5125 |
|
|
+ *
|
5126 |
|
|
+ * ?? What's a sibling call?
|
5127 |
|
|
+ */
|
5128 |
|
|
+
|
5129 |
|
|
+// TARGET_EXTRA_LIVE_ON_ENTRY
|
5130 |
|
|
+// TARGET_SET_UP_BY_PROLOGUE
|
5131 |
|
|
+// TARGET_WARN_FUNC_RETURN
|
5132 |
|
|
+
|
5133 |
102 |
dgisselq |
+/* 17.09.14 Stack smashing protection */
|
5134 |
111 |
dgisselq |
+// TARGET_STACK_PROTECT_GUARD
|
5135 |
|
|
+// TARGET_STACK_PROTECT_FAIL
|
5136 |
|
|
+// TARGET_SUPPORTS_SPLIT_STACK
|
5137 |
|
|
+
|
5138 |
102 |
dgisselq |
+/* 17.09.15 Miscellaneous register hooks */
|
5139 |
|
|
+
|
5140 |
111 |
dgisselq |
+// TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
|
5141 |
|
|
+
|
5142 |
102 |
dgisselq |
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
|
5143 |
|
|
+ * ZipCPU --- default is good enough for us.
|
5144 |
|
|
+ */
|
5145 |
|
|
+
|
5146 |
|
|
+/* 17.10 Implementing VARARGS MACROS */
|
5147 |
|
|
+
|
5148 |
|
|
+/* ...
|
5149 |
|
|
+ */
|
5150 |
|
|
+
|
5151 |
|
|
+/* void TARGET_SETUP_INCOMING_VARARGS(A,M,T,I,S) ... This target hook offers an
|
5152 |
|
|
+ * alternative to using __builtin_saveregs and defining the hook TARGET_EXPAND..
|
5153 |
|
|
+ * _BUILTIN_SAVEREGS. Use it to store the anonymous register arguments into the
|
5154 |
|
|
+ * stack so that all the arguments appear to have been passed consecutively
|
5155 |
|
|
+ * on the stack. Once this is done, you can use the standard implementation
|
5156 |
|
|
+ * of varargs that works for machines that pass all their arguments on the
|
5157 |
|
|
+ * stack.
|
5158 |
|
|
+ */
|
5159 |
|
|
+// #undef TARGET_SETUP_INCOMING_VARARGS
|
5160 |
|
|
+// #define TARGET_SETUP_INCOMING_VARARGS zip_setup_incoming_varargs
|
5161 |
|
|
+
|
5162 |
|
|
+/* ...
|
5163 |
|
|
+ */
|
5164 |
|
|
+
|
5165 |
|
|
+/* 17.11 Trampolines for Nested Functions */
|
5166 |
|
|
+
|
5167 |
|
|
+/* TARGET_ASM_TRAMPOLINE_TEMPLATE ... This hook is called by
|
5168 |
|
|
+ * assemble_trampoline_template to output, on the stream f, assembler code for
|
5169 |
|
|
+ * a block of data that contains the constant parts of a trampoline. This code
|
5170 |
|
|
+ * should not include a label--the label is taken care of automatically.
|
5171 |
|
|
+ *
|
5172 |
|
|
+ * ZipCPU -- looks like we need to do this.
|
5173 |
|
|
+ */
|
5174 |
|
|
+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
|
5175 |
|
|
+#define TARGET_ASM_TRAMPOLINE_TEMPLATE zip_asm_trampoline_template
|
5176 |
|
|
+
|
5177 |
|
|
+/* TRAMPOLINE_SECTION ... Return the section into which the trampoline template
|
5178 |
|
|
+ * is to be placed. The default value is readonly_data_section.
|
5179 |
|
|
+ *
|
5180 |
|
|
+ * ZipCPU--default should be good enough.
|
5181 |
|
|
+ */
|
5182 |
|
|
+
|
5183 |
|
|
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
|
5184 |
|
|
+ * as an integer.
|
5185 |
|
|
+ *
|
5186 |
|
|
+ * ZipCPU--it's three instructions, or 96 bits. However, 32-bits is our minimal
|
5187 |
|
|
+ * addressible unit, so what size do we offer here? We'll stick with the number
|
5188 |
|
|
+ * of bytes, but we may need to change this later.
|
5189 |
|
|
+ *
|
5190 |
|
|
+ */
|
5191 |
|
|
+// #warning "May need to redefine trampoline_size in words, not bytes"
|
5192 |
|
|
+#undef TRAMPOLINE_SIZE
|
5193 |
|
|
+#define TRAMPOLINE_SIZE 3
|
5194 |
|
|
+
|
5195 |
|
|
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
|
5196 |
|
|
+ *
|
5197 |
|
|
+ * Well that's well known in ZipCPU --- 32-bits.
|
5198 |
|
|
+ */
|
5199 |
|
|
+#undef TRAMPOLINE_ALIGNMENT
|
5200 |
|
|
+#define TRAMPOLINE_ALIGNMENT 32
|
5201 |
|
|
+
|
5202 |
|
|
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
|
5203 |
|
|
+ * initialize a trampoline. m_tramp is an RTX for the memory block for the
|
5204 |
|
|
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion; CH is an
|
5205 |
|
|
+ * rtx for the static chain value that should be passed to the function when
|
5206 |
|
|
+ * it is called.
|
5207 |
|
|
+ *
|
5208 |
|
|
+ * ZipCPU ... Can we get by without this?
|
5209 |
|
|
+ */
|
5210 |
|
|
+#undef TARGET_TRAMPOLINE_INIT
|
5211 |
|
|
+#define TARGET_TRAMPOLINE_INIT zip_trampoline_init
|
5212 |
|
|
+
|
5213 |
|
|
+/* TARGET_TRAMPOLINE_ADJUST_ADDRESS(RTX) ... This hook should perform any
|
5214 |
|
|
+ * machine-specific adjustment in the address of the trampoline. Its argument
|
5215 |
|
|
+ * contains the address of the memory block that was passed to
|
5216 |
|
|
+ * TARGET_TRAMPOLINE_INIT. In case the address to be used for a function call
|
5217 |
|
|
+ * should be different from the address at which the template was stored, the
|
5218 |
|
|
+ * different address should be returned; otherwise addr should be returned
|
5219 |
|
|
+ * unchanged. If the hook is not defined, RTX (addr) will be used for function
|
5220 |
|
|
+ * calls.
|
5221 |
|
|
+ *
|
5222 |
|
|
+ * ZipCPU--works for us!
|
5223 |
|
|
+ */
|
5224 |
|
|
+
|
5225 |
|
|
+/* CLEAR_INSN_CACHE(BEG,END) ... If defined, expands to a C expression clearing
|
5226 |
|
|
+ * the instruction cache in the specified interval. The definition of this
|
5227 |
|
|
+ * macro would typically be a series of asm statements. Both BEG and END are
|
5228 |
|
|
+ * pointer expressions.
|
5229 |
|
|
+ *
|
5230 |
|
|
+ * ZipCPU --- Ouch! We have no way to do this (yet)!
|
5231 |
|
|
+ */
|
5232 |
|
|
+
|
5233 |
|
|
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
|
5234 |
111 |
dgisselq |
+ * subroutine to do their work. The macro should expand to a series of asm
|
5235 |
102 |
dgisselq |
+ * statements which will be compiled with GCC. They go in a library function
|
5236 |
|
|
+ * named __transfer_from_trampoline.
|
5237 |
|
|
+ *
|
5238 |
|
|
+ * We may need to rethink trampolines on ZipCPU.
|
5239 |
|
|
+ */
|
5240 |
|
|
+
|
5241 |
|
|
+
|
5242 |
|
|
+/* 17.12 Implicit Calls to Library Routines */
|
5243 |
|
|
+
|
5244 |
|
|
+/* DECLARE_LIBRARY_RENAMES
|
5245 |
|
|
+ *
|
5246 |
|
|
+ * ZipCPU: Don't need it.
|
5247 |
|
|
+ */
|
5248 |
|
|
+
|
5249 |
|
|
+/* TARGET_INIT_LIBFUNCS(VOID) ... This hook should declare additional library
|
5250 |
|
|
+ * routines or rename existing ones, using the functions set_optab_libfunc and
|
5251 |
|
|
+ * init_one_libfunc defined in optabs.c. init_optabs calls this macro after
|
5252 |
|
|
+ * initializing all the normal library routines.
|
5253 |
|
|
+ *
|
5254 |
|
|
+ * Most ports don't need to define this hook, so we won't either.
|
5255 |
|
|
+ */
|
5256 |
|
|
+
|
5257 |
|
|
+/* TARGET_LIBFUNC_GNU_PREFIX ... If false (the default), internal library
|
5258 |
|
|
+ * routines start with two underscores. If set to true, these routines start
|
5259 |
|
|
+ * with __gnu_ instead.
|
5260 |
|
|
+ *
|
5261 |
|
|
+ * ZipCPU: No change necessary.
|
5262 |
|
|
+ */
|
5263 |
|
|
+
|
5264 |
|
|
+/* FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE,COMPARISON) ... This macro should return
|
5265 |
|
|
+ * true if the library routine that implements the floating point comparison
|
5266 |
|
|
+ * operator comparison in mode mode will return a boolean and false if it will
|
5267 |
|
|
+ * return a tristate.
|
5268 |
|
|
+ *
|
5269 |
|
|
+ * Most ports don't need to define this macro, so Zip CPU won't either.
|
5270 |
|
|
+ */
|
5271 |
|
|
+
|
5272 |
|
|
+/* TARGET_HAS_NO_HW_DIVIDE ... This macro should be defined if the target has no
|
5273 |
|
|
+ * hardware divide instructions. If this macro is defined, GCC will use an
|
5274 |
|
|
+ * algorithm which makes use of simple logical and arithmetic operations for
|
5275 |
|
|
+ * 64-bit division. If the macro is not defined, GCC will use an algorithm
|
5276 |
|
|
+ * which makes use of a 64-bit by 32-bit divide primitive.
|
5277 |
|
|
+ *
|
5278 |
|
|
+ * Zip CPU, though, doesn't have the 64-bit by 32-bit divide primitive, thus
|
5279 |
|
|
+ * we have no HW DIVIDE (for now).
|
5280 |
|
|
+ */
|
5281 |
|
|
+#define TARGET_HAS_NO_HW_DIVIDE
|
5282 |
|
|
+
|
5283 |
|
|
+/* TARGET_EDOM ... The value of EDOM on the target machine, as a C integer
|
5284 |
|
|
+ * expression. If you don't define this macro, GCC does not attempt to deposit
|
5285 |
|
|
+ * the value of EDOM into errno directly. Look in /usr/include/errno.h to find
|
5286 |
|
|
+ * the value of EDOM on your system.
|
5287 |
|
|
+ *
|
5288 |
|
|
+ * EDOM is the error created when a math argument is out of the domain of the
|
5289 |
|
|
+ * function.
|
5290 |
|
|
+ *
|
5291 |
|
|
+ * ZipCPU: Don't need it---I don't think.
|
5292 |
|
|
+ */
|
5293 |
|
|
+
|
5294 |
|
|
+/* GEN_ERRNO_RTX ... Define this macro as a C exrpession to create an rtl
|
5295 |
|
|
+ * expression that refers to the global "variable" errno. (On certain
|
5296 |
|
|
+ * systems, errno may not actually be a variable.) If you don't define this
|
5297 |
|
|
+ * macro, a reasonable default is used.
|
5298 |
|
|
+ *
|
5299 |
|
|
+ * ZipCPU --- if a reasonable default is used, we'll use that--especially since
|
5300 |
|
|
+ * I doubt we'll be using errno for a while.
|
5301 |
|
|
+ */
|
5302 |
|
|
+
|
5303 |
|
|
+/* NEXT_OBJC_RUNTIME ... Set this macro to 1 to use the "NeXT" Objective-C
|
5304 |
|
|
+ * message sending conventions by default. This calling convention involves
|
5305 |
|
|
+ * passing the object, the selector and the method arguments all at once to the
|
5306 |
|
|
+ * method-lookup library function. This is the usual setting when targetting
|
5307 |
|
|
+ * Darwin/Mac OS X systems, which have the NeXT runtime installed.
|
5308 |
|
|
+ *
|
5309 |
|
|
+ * If the macro is set to 0, ...
|
5310 |
|
|
+ *
|
5311 |
|
|
+ * Doesn't look relevant (yet) for the Zip CPU--especially since we don't have
|
5312 |
|
|
+ * an O/S yet.
|
5313 |
|
|
+ */
|
5314 |
|
|
+
|
5315 |
|
|
+
|
5316 |
|
|
+
|
5317 |
|
|
+/* 17.13 Addressing Modes */
|
5318 |
|
|
+
|
5319 |
|
|
+/* C expressions that are nonzero if the machine supports pre-increment,
|
5320 |
|
|
+ * pre-decrement, post-increment, or post-decrement addressing respectively.
|
5321 |
|
|
+ */
|
5322 |
|
|
+#define HAVE_PRE_INCREMENT (0)
|
5323 |
|
|
+#define HAVE_PRE_DECREMENT (0)
|
5324 |
|
|
+#define HAVE_POST_INCREMENT (0)
|
5325 |
|
|
+#define HAVE_POST_DECREMENT (0)
|
5326 |
|
|
+
|
5327 |
|
|
+/* C expression that is nonzero if the machine supports pre- or post- address
|
5328 |
|
|
+ * side-effect generation involving constants other than the size of the memory
|
5329 |
|
|
+ * operand.
|
5330 |
|
|
+ */
|
5331 |
|
|
+#define HAVE_PRE_MODIFY_DISP (0)
|
5332 |
|
|
+#define HAVE_POST_MODIFY_DISP (0)
|
5333 |
|
|
+
|
5334 |
|
|
+/* C expression that is non-zero if the machine supports pre- or post-address
|
5335 |
|
|
+ * side-effect generation involving a register displacement.
|
5336 |
|
|
+ */
|
5337 |
|
|
+#define HAVE_PRE_MODIFY_REG (0)
|
5338 |
|
|
+#define HAVE_POST_MODIFY_REG (0)
|
5339 |
|
|
+
|
5340 |
|
|
+/* CONSTANT_ADDRESS_P(X) ... A C expression that is 1 if the RTX X is a constant
|
5341 |
|
|
+ * which is a valid address. On most machines the default definition ... is
|
5342 |
|
|
+ * acceptable, but a few machines are more restrictive as to which constant
|
5343 |
|
|
+ * addresses are supported.
|
5344 |
|
|
+ *
|
5345 |
|
|
+ * Zip CPU is designed for offset addresses, not constant addresses. Although
|
5346 |
|
|
+ * the CPU will support 18-bit signed constant addresses, the assembler and
|
5347 |
|
|
+ * general programming model do not. Further, without knowing where the final
|
5348 |
|
|
+ * address will be located, this is an unusable model. Therefore we will
|
5349 |
|
|
+ * define this as not supported.
|
5350 |
|
|
+ *
|
5351 |
|
|
+ * In hindsight, this isn't true--labels and symbols are valid addresses, and
|
5352 |
|
|
+ * they are also constant addresses. Hence, we leave this at its default.
|
5353 |
|
|
+ */
|
5354 |
|
|
+// #undef CONSTANT_ADDRESS_P
|
5355 |
|
|
+// #define CONSTANT_ADDRESS_P(X) (0)
|
5356 |
|
|
+
|
5357 |
111 |
dgisselq |
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code,
|
5358 |
|
|
+ * accepts integer values expressions whose values are not explicitly known,
|
5359 |
|
|
+ * such as symbol_ref, label_ref, and high expressions and const arithmetic
|
5360 |
|
|
+ * expressions, in addition to const_int and const_double expressions.
|
5361 |
102 |
dgisselq |
+ *
|
5362 |
|
|
+ * Huh???
|
5363 |
|
|
+ */
|
5364 |
|
|
+// #define CONSTANT_P(X) ???
|
5365 |
|
|
+
|
5366 |
111 |
dgisselq |
+/* MAX_REGS_PER_ADDRESS ... A number, the maximum number of registers that can
|
5367 |
|
|
+ * appear in a valid memory address. Note that it is up to you to specify a
|
5368 |
|
|
+ * value equal to the maximum number that TARGET_LEGITIMATE_ADDRESS_P would
|
5369 |
|
|
+ * ever accept.
|
5370 |
102 |
dgisselq |
+ */
|
5371 |
|
|
+#define MAX_REGS_PER_ADDRESS 1
|
5372 |
|
|
+
|
5373 |
|
|
+/* TARGET_LEGITIMATE_ADDRESS_P(MODE,RTX,STRICT) ... A function that returns
|
5374 |
|
|
+ * whether RTX is a legitimate memory address on the target machine for a
|
5375 |
|
|
+ * memory operation of mode MODE.
|
5376 |
|
|
+ */
|
5377 |
|
|
+#undef TARGET_LEGITIMATE_ADDRESS_P
|
5378 |
|
|
+#define TARGET_LEGITIMATE_ADDRESS_P zip_legitimate_address_p
|
5379 |
|
|
+
|
5380 |
|
|
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
|
5381 |
|
|
+ * default 'm' character for general memory addresses. This defines the
|
5382 |
|
|
+ * constraint letter which matches the memory addresses accepted by
|
5383 |
|
|
+ * TARGET_LEGITIMATE_ADDRESS_P. Define this macro if you want to support new
|
5384 |
|
|
+ * address format in your back end without changing the semantics of the 'm'
|
5385 |
|
|
+ * constraint. This is necessary in order to preserve functionality of inline
|
5386 |
|
|
+ * assembly constructs using the 'm' constraint.
|
5387 |
|
|
+ *
|
5388 |
|
|
+ * ZipCPU--doesn't look like we need to define this at all.
|
5389 |
|
|
+ */
|
5390 |
|
|
+
|
5391 |
|
|
+/* FIND_BASE_TERM(X) ... A C expression to determine the base term of address
|
5392 |
|
|
+ * X or to provide a simplified version of X from which alias.c can easily find
|
5393 |
|
|
+ * the base term. This macro is used in only two places: find_base_value and
|
5394 |
|
|
+ * find_base_term in alias.c.
|
5395 |
|
|
+ *
|
5396 |
|
|
+ * It is always safe for this macro to not be defined. It exists so that
|
5397 |
|
|
+ * alias analysis can understand machine-dependent addresses.
|
5398 |
|
|
+ *
|
5399 |
|
|
+ * ZipCPU: We'll skip this then.
|
5400 |
|
|
+ */
|
5401 |
|
|
+
|
5402 |
|
|
+/* TARGET_LEGITIMIZE_ADDRESS(RTX,OLD,MODE) ... This hook is given an invalid
|
5403 |
|
|
+ * memory address RTX for an operand of mode MODE and should try to return a
|
5404 |
|
|
+ * valid memory address. RTX will always be the result of a call to
|
5405 |
|
|
+ * break_out_memory_refs, and OLD will be the operand that was given to that
|
5406 |
|
|
+ * function to produce RTX.
|
5407 |
|
|
+ *
|
5408 |
111 |
dgisselq |
+ * ZipCPU --
|
5409 |
102 |
dgisselq |
+ */
|
5410 |
111 |
dgisselq |
+#undef TARGET_LEGITIMIZE_ADDRESS
|
5411 |
|
|
+#define TARGET_LEGITIMIZE_ADDRESS zip_legitimize_address
|
5412 |
102 |
dgisselq |
+
|
5413 |
|
|
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
|
5414 |
|
|
+ * that attempts to replace X, which is an address that needs reloading, with
|
5415 |
|
|
+ * a valid memory address for an operand of mode MODE. WIN will be a C
|
5416 |
|
|
+ * statement label elsewhere in the code. It is not necessary to define this
|
5417 |
|
|
+ * macro, but it might be useful for performance reasons.
|
5418 |
|
|
+ *
|
5419 |
|
|
+ * ZipCPU: This is worth coming back to, according to the notes page, but it
|
5420 |
|
|
+ * may also be a difficult macro to use. Look at other implementations before
|
5421 |
|
|
+ * we dive into this.
|
5422 |
|
|
+ */
|
5423 |
|
|
+// #undef LEGITIMIZE_RELOAD_ADDRESS
|
5424 |
|
|
+// #define LEGITIMIZE_RELOAD_ADDRESS
|
5425 |
|
|
+
|
5426 |
|
|
+/* TARGET_MODE_DEPENDENT_ADDRESS_P(ADDR,SPACE) ... This hook returns true
|
5427 |
|
|
+ * if memory address addr in address space addrspace can have different meanings
|
5428 |
|
|
+ * depending on the machine mode of the memory reference it is used for or if
|
5429 |
|
|
+ * the address is valid for some modes but not others.
|
5430 |
|
|
+ */
|
5431 |
|
|
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
|
5432 |
|
|
+#define TARGET_MODE_DEPENDENT_ADDRESS_P zip_mode_dependent_address_p
|
5433 |
|
|
+
|
5434 |
111 |
dgisselq |
+/* TARGET_LEGITIMATE_CONSTANT_P(MODE,RTX) ... This hook returns true if x is a
|
5435 |
|
|
+ * legitimate constant for a MODE-mode immediate operand on the target machine.
|
5436 |
|
|
+ * You can assume the RTX satisfies CONSTANT_P, so you need not check this.
|
5437 |
|
|
+ *
|
5438 |
|
|
+ * The default definition returns true.
|
5439 |
102 |
dgisselq |
+ */
|
5440 |
|
|
+
|
5441 |
|
|
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
|
5442 |
|
|
+ */
|
5443 |
|
|
+
|
5444 |
|
|
+/* TARGET_CONST_NOT_OK_FOR_DEBUG_P(RTX) ... This hook should return true if RTX
|
5445 |
|
|
+ * should not be emitted into debug sections.
|
5446 |
|
|
+ */
|
5447 |
|
|
+
|
5448 |
|
|
+/* TARGET_CANNOT_FORCE_CONST_MEM(MODE,RTX) ... This hook should return true if
|
5449 |
|
|
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
|
5450 |
|
|
+ * MODE is the mode of X. The default version returns false.
|
5451 |
|
|
+ */
|
5452 |
111 |
dgisselq |
+// #define TARGET_CANNOT_FORCE_CONST_MEM hook_bool_mode_rtx_false
|
5453 |
102 |
dgisselq |
+
|
5454 |
|
|
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
|
5455 |
|
|
+ * if pool entries for constant RTX can be placed in an object_block structure.
|
5456 |
|
|
+ * MODE is the mode of X. The default version returns false for all constants.
|
5457 |
|
|
+ *
|
5458 |
|
|
+ *????
|
5459 |
|
|
+ */
|
5460 |
|
|
+// #warning "Huh?"
|
5461 |
|
|
+
|
5462 |
|
|
+/* TARGET_USE_BLOCKS_FOR_DECL_P(DECL) ... This hook should return true if pool
|
5463 |
|
|
+ * entries for DECL should be placed in an object_block structure. The default
|
5464 |
|
|
+ * version returns true for all DECL's.
|
5465 |
|
|
+ *
|
5466 |
|
|
+ * Sounds good.
|
5467 |
|
|
+ */
|
5468 |
|
|
+
|
5469 |
|
|
+/* TARGET_BUILTIN_RECIPROCAL(TREE) ... This hook should return the DECL of a
|
5470 |
|
|
+ * function that implements the reciprocal of the machine specific builtin
|
5471 |
|
|
+ * function fndecl, or NULL_TREE if such a function is not available.
|
5472 |
|
|
+ */
|
5473 |
|
|
+
|
5474 |
|
|
+/* TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD(VOID) ... This hook should return the
|
5475 |
|
|
+ * DECL of a function f that given an address addr as an argument returns a mask
|
5476 |
|
|
+ * m that can be used to extrract from two vectors the relevant data that
|
5477 |
|
|
+ * resides in addr in case addr is not properly aligned.
|
5478 |
|
|
+ *
|
5479 |
|
|
+ * Zip CPU does not support vectorization.
|
5480 |
|
|
+ */
|
5481 |
|
|
+
|
5482 |
|
|
+/* Other vector, SIMD, and GOACC macros skipped as Zip CPU doesn't support
|
5483 |
|
|
+ * such data accesses and manipulation.
|
5484 |
|
|
+ */
|
5485 |
|
|
+
|
5486 |
|
|
+/* 17.14 Anchored Addresses */
|
5487 |
|
|
+
|
5488 |
|
|
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
|
5489 |
|
|
+ * a section anchor. On most targets, it should be the smallest offset that
|
5490 |
|
|
+ * can be applied to a base register while still giving a legitimate address for
|
5491 |
|
|
+ * every mode. The default value is 0.
|
5492 |
|
|
+ *
|
5493 |
|
|
+ * On the Zip CPU, this is the minimum operand B offset to a LOD or STO
|
5494 |
|
|
+ * operation, which would be a signed 14 bit number.
|
5495 |
|
|
+ */
|
5496 |
|
|
+#undef TARGET_MIN_ANCHOR_OFFSET
|
5497 |
|
|
+#define TARGET_MIN_ANCHOR_OFFSET zip_min_anchor_offset
|
5498 |
|
|
+
|
5499 |
|
|
+/* TARGET_MAX_ANCHOR_OFFSET ... Like TARGET_MIN_ANCHOR_OFFSET, but the maximum
|
5500 |
|
|
+ * (inclusive) offset that should be applied to section anchors. The default
|
5501 |
|
|
+ * value is 0.
|
5502 |
|
|
+ */
|
5503 |
|
|
+#undef TARGET_MAX_ANCHOR_OFFSET
|
5504 |
|
|
+#define TARGET_MAX_ANCHOR_OFFSET zip_max_anchor_offset
|
5505 |
|
|
+
|
5506 |
|
|
+/* TARGET_ASM_OUTPUT_ANCHOR(RTX) ... Write the assembly code to define section
|
5507 |
|
|
+ * anchor RTX, which is a SYMBOL_REF for which 'SYMBOL_REF_ANCHOR_P(RTL) is
|
5508 |
|
|
+ * true. The hook is called with the assembly output position set to the
|
5509 |
|
|
+ * beginning of SYMBOL_REF_BLOCK(X).
|
5510 |
|
|
+ *
|
5511 |
|
|
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
|
5512 |
|
|
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'. If ASM_OUTPUT_DEF
|
5513 |
|
|
+ * is not available, the hook's default definition is NULL, which disables the
|
5514 |
|
|
+ * use of section anchors altogether.
|
5515 |
|
|
+ *
|
5516 |
|
|
+ * Section anchors will be very valuable in Zip CPU assembly, therefore we
|
5517 |
|
|
+ * must define this hook.
|
5518 |
|
|
+ */
|
5519 |
|
|
+// #undef TARGET_ASM_OUTPUT_ANCHOR
|
5520 |
|
|
+// #define TARGET_ASM_OUTPUT_ANCHOR zip_asm_output_anchor
|
5521 |
|
|
+
|
5522 |
|
|
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
|
5523 |
|
|
+ * to use anchors to access SYMBOL_REF X. You can assume SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
|
5524 |
|
|
+ *
|
5525 |
|
|
+ * The default version is correct for most targets, but you might need to intercept this hook to handle things like target specific attributes or target-specific sections.
|
5526 |
|
|
+ *
|
5527 |
|
|
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
|
5528 |
|
|
+ */
|
5529 |
|
|
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
|
5530 |
|
|
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P zip_use_anchors_for_symbol_p
|
5531 |
|
|
+
|
5532 |
|
|
+/* 17.15 Condition Code Status */
|
5533 |
|
|
+
|
5534 |
|
|
+/* 17.15.1 Representation of condition codes using (cc0) --- that's us */
|
5535 |
|
|
+
|
5536 |
|
|
+/* CC_STATUS_MDEP ... C code for a data type which is used for declaring
|
5537 |
|
|
+ * the mdep component of cc_status. It defaults to int.
|
5538 |
|
|
+ *
|
5539 |
|
|
+ * ZipCPU---Int is good for us.
|
5540 |
|
|
+ */
|
5541 |
|
|
+
|
5542 |
|
|
+/* CC_STATUS_MDEP_INIT ... A C expression to initialize the mdep field to
|
5543 |
|
|
+ * "empty". The default definition does nothing, since most machines don't
|
5544 |
|
|
+ * use the field anyway. If you want to use the field, you should probably
|
5545 |
|
|
+ * define this macro to initialize it.
|
5546 |
|
|
+ */
|
5547 |
|
|
+
|
5548 |
|
|
+/* NOTICE_UPDATE_CC(EXP, INSN) ... A C compound statement to set the components
|
5549 |
|
|
+ * of cc_status appropriately for an insn insn whose body is exp. It is this
|
5550 |
|
|
+ * macro's responsibility to recognize insns that set the condition code as
|
5551 |
|
|
+ * a byproduct of other activity as well as those that explicitly set (cc0).
|
5552 |
|
|
+ *
|
5553 |
|
|
+ * ZipCPU --- We need this, as not all expressions set (cc0).
|
5554 |
|
|
+ *
|
5555 |
|
|
+ */
|
5556 |
122 |
dgisselq |
+#ifdef HAVE_cc0
|
5557 |
102 |
dgisselq |
+#define NOTICE_UPDATE_CC(EXP, INSN) zip_update_cc_notice(EXP, INSN)
|
5558 |
122 |
dgisselq |
+#endif
|
5559 |
102 |
dgisselq |
+
|
5560 |
|
|
+
|
5561 |
|
|
+/* 17.15.2 Representation of condition codes using registers */
|
5562 |
|
|
+/* ... which the ZipCPU doesn't have. The ZipCPU has a CC0 register, and hence
|
5563 |
|
|
+ * this section isn't supposed to apply.
|
5564 |
|
|
+ */
|
5565 |
|
|
+
|
5566 |
122 |
dgisselq |
+/* SELECT_CC_MODE(op, x, y) ... On many machines, the condition code may be
|
5567 |
|
|
+ * produced by other instructions than compares, for example the branch can use
|
5568 |
|
|
+ * directyl the condition code set by a subtract instruction. However, on some
|
5569 |
|
|
+ * machines when the condition code is set this way some bits (such as the
|
5570 |
|
|
+ * overflow bit) are not set in the same way as a test instruction, so that a
|
5571 |
|
|
+ * different branch instruction must be used for some conditional branches.
|
5572 |
|
|
+ * When this happens, use the machinemode of the condition code register to
|
5573 |
|
|
+ * record different formats of the condition code register. Modes can also be
|
5574 |
|
|
+ * used to reccord which compare instruction (e.g. a signed or an unsigned
|
5575 |
|
|
+ * comparison) produced the condition codes.
|
5576 |
|
|
+ *
|
5577 |
|
|
+ * If other modes than CCmode are required, add them to 'machine-modes.def' and
|
5578 |
|
|
+ * define SELECT_CC_MODE to choose a mode given an operand of a compare. This
|
5579 |
|
|
+ * is needed because the modes have to be chosen not only during RTL generation
|
5580 |
|
|
+ * but also, for example, by instruction combination. The result of
|
5581 |
|
|
+ * SELECT_CC_MODE should be consistent with the mode used in the patterns; ...
|
5582 |
|
|
+ *
|
5583 |
|
|
+ * ZipCPU ... We have only one CC Mode, so we'll use the CCmode defined in
|
5584 |
|
|
+ * machine-modes.def and should be fine with it. Hence, this doesn't need
|
5585 |
|
|
+ * to be defined.
|
5586 |
102 |
dgisselq |
+ */
|
5587 |
|
|
+
|
5588 |
|
|
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines
|
5589 |
|
|
+ * (such as the ZipCPU) not all possible comparisons are defined, but you can
|
5590 |
|
|
+ * convert an invalid comparison into a valid one. For example, the Alpha
|
5591 |
|
|
+ * does not have a GT comparison, but you can use an LT comparison instead and
|
5592 |
|
|
+ * swap the order of the operands.
|
5593 |
|
|
+ *
|
5594 |
|
|
+ * On such machines, implement this hook to do any required conversions: code
|
5595 |
|
|
+ * is the initial comparison code and op0 and op1 are the left and right
|
5596 |
|
|
+ * operands of the comparison, respectively. If op0_preserve_value is true the
|
5597 |
|
|
+ * implementation is not allowed to change the value of op0 since the value
|
5598 |
|
|
+ * might be used in RTXs which aren't comparisons. E.g. the implementation is
|
5599 |
|
|
+ * not allowed to swap operands in that case.
|
5600 |
|
|
+ *
|
5601 |
|
|
+ * GCC will not assume that the comparison resulting from this macro is valid
|
5602 |
|
|
+ * but will see if the resulting insn matches a pattern in the 'md' file.
|
5603 |
|
|
+ *
|
5604 |
|
|
+ * You need not implement this hook if it would never change the comparison
|
5605 |
|
|
+ * code or operands.
|
5606 |
|
|
+ *
|
5607 |
|
|
+ * In the case of the ZipCPU, the ZipCPU only keeps track of 8 possible
|
5608 |
|
|
+ * comparisons, and bastardizing other comparisons into those 8 is extremely
|
5609 |
|
|
+ * painful. Therefore, we *need* this capability to make certain we can use
|
5610 |
|
|
+ * our comparisons successfully.
|
5611 |
|
|
+ *
|
5612 |
|
|
+ * The only problem is ... this hook appears to only be called on non-CC0
|
5613 |
|
|
+ * machines. Hence, defining it hasn't done anything for us.
|
5614 |
|
|
+ */
|
5615 |
122 |
dgisselq |
+#define TARGET_CANONICALIZE_COMPARISON zip_canonicalize_comparison
|
5616 |
102 |
dgisselq |
+
|
5617 |
122 |
dgisselq |
+/* REVERSIBLE_CC_MODE(MODE) ... A C expression whose value is one if it is
|
5618 |
|
|
+ * always safe to reverse a comparison whose mode is MODE. If SELECT_CC_MODE
|
5619 |
|
|
+ * can ever return MODE for a floating-point inequality comparison, than
|
5620 |
|
|
+ * REVERSIBLE_CC_MODE(MODE) must be zero.
|
5621 |
|
|
+ *
|
5622 |
|
|
+ * You need not define this macro if it would always return zero or if the
|
5623 |
|
|
+ * floating-point format is anything other than IEEE_FLOAT_FORMAT. For example,
|
5624 |
|
|
+ * here ...
|
5625 |
|
|
+ *
|
5626 |
|
|
+ * ZipCPU -- We'll always return zero, so this need not be defined.
|
5627 |
|
|
+ */
|
5628 |
|
|
+
|
5629 |
|
|
+/* REVERSE_CONDITION(CODE,MODE) ... A C expression whose value is reversed
|
5630 |
|
|
+ * condition code of thecode for comparison done in CC_MODE MODE. This macro
|
5631 |
|
|
+ * is used only in case REVERSIBLE_CC_MODE(MODE) is nonzero. ...
|
5632 |
|
|
+ *
|
5633 |
|
|
+ * ZipCPU ... Since REVERSIBLE_CC_MODE(MODE) will always be zero, we'll leave
|
5634 |
|
|
+ * this undefined.
|
5635 |
|
|
+ */
|
5636 |
|
|
+
|
5637 |
|
|
+/* bool TARGET_FIXED_CONDITION_CODE_REGS(int *, int *) ... On targets which do
|
5638 |
|
|
+ * not use (cc0), and which use a hard register rather than a pseudo-register
|
5639 |
|
|
+ * to hold condition codes, the regular CSE passes are often not able to
|
5640 |
|
|
+ * identify cases in which the hard register is set to a common value. Use this
|
5641 |
|
|
+ * hook to enable a small pass which optimizes such cases. This hook should
|
5642 |
|
|
+ * return true to enable this pass, and it should set the integers to which its
|
5643 |
|
|
+ * arguments point to the hard register numbers used for condition codes. When
|
5644 |
|
|
+ * there is only one such register, as is true on most systems, the integer
|
5645 |
|
|
+ * pointed to by p2 should be set to INVALID_REGNUM.
|
5646 |
|
|
+ *
|
5647 |
|
|
+ * The default version of this hook returns false.
|
5648 |
|
|
+ *
|
5649 |
|
|
+ * ZipCPU --- I like the idea of enabling optimizations. Let's return
|
5650 |
|
|
+ * something other than false.
|
5651 |
|
|
+ */
|
5652 |
|
|
+#define TARGET_FIXED_CONDITION_CODE_REGS zip_fixed_condition_code_regs
|
5653 |
|
|
+
|
5654 |
|
|
+/* machine_mode TARGET_CC_MODES_COMPATIBLE(M1,M2) .. On targets which use
|
5655 |
|
|
+ * multiple condition code modes in class MODE_CC, it is sometimes the case
|
5656 |
|
|
+ * that a comparison can be validly done in more than one mode. On such a
|
5657 |
|
|
+ * system, define this target hook to take two mode arguments and to return a
|
5658 |
|
|
+ * mode in which both comparisons may be validly done. If there is no such
|
5659 |
|
|
+ * mode, return VOIDmode.
|
5660 |
|
|
+ *
|
5661 |
|
|
+ * The default version of this hook checks whether the modes are the same. If
|
5662 |
|
|
+ * they are, it returns that mode. If they are different, it returns VOIDmode.
|
5663 |
|
|
+ *
|
5664 |
|
|
+ * ZipCPU--Given that we only have the one CCmode, the default definition works
|
5665 |
|
|
+ * well enough for us.
|
5666 |
|
|
+ */
|
5667 |
|
|
+
|
5668 |
|
|
+/* unsigned int TARGET_FLAGS_REGNUM ... If the target has a dedicated flags
|
5669 |
|
|
+ * register, and it needs to use the post-reload comparison elimination pass,
|
5670 |
|
|
+ * then this value should be set appropriately.
|
5671 |
|
|
+ *
|
5672 |
|
|
+ * ZipCPU---Looks like we can set this easily enough without any problems.
|
5673 |
|
|
+ */
|
5674 |
|
|
+#undef TARGET_FLAGS_REGNUM
|
5675 |
|
|
+#define TARGET_FLAGS_REGNUM zip_CC
|
5676 |
|
|
+
|
5677 |
102 |
dgisselq |
+/* 17.16 Relative costs of operations */
|
5678 |
|
|
+
|
5679 |
|
|
+
|
5680 |
|
|
+// #define REGISTER_MOVE_COST(MODE,FROM,TO) ((MODE==DImode)||(MODE==DFmode))?4:2
|
5681 |
|
|
+// #define TARGET_REGISTER_MOVE_COST
|
5682 |
|
|
+// #define MEMORY_MOVE_COST(MODE, CLASS, IN) ((MODE==DImode)||(MODE==DFmode))?8:7
|
5683 |
|
|
+/* TARGET_REGISTER_MOVE_COST(M,FRM,TO) ... This target hook should return the
|
5684 |
|
|
+ * cost of moving data of mode M from a register in class FRM to one in class
|
5685 |
|
|
+ * TO. The classes are expressed using the enumeration values such as
|
5686 |
|
|
+ * GENERAL_REGS. A value of 2 is the default; other values are interpreted
|
5687 |
|
|
+ * relative to that.
|
5688 |
|
|
+ *
|
5689 |
|
|
+ * It is not required that the cost always equal 2 when FROM is the same as TO;
|
5690 |
|
|
+ * on some machines it is expensive to move between registers if they are not
|
5691 |
|
|
+ * general registers.
|
5692 |
|
|
+ *
|
5693 |
|
|
+ * If reload sees ...
|
5694 |
|
|
+ *
|
5695 |
|
|
+ * ZipCPU ... We can leave this at its default value of 2.
|
5696 |
|
|
+ */
|
5697 |
|
|
+
|
5698 |
|
|
+/* TARGET_MEMORY_MOVE_COST(MOD,CL,IN) ... This target hook should return the
|
5699 |
|
|
+ * cost of moving data of mode MOD between a register of class CL and memory.
|
5700 |
|
|
+ * IN is false if the value is to be written to memory, true if it is to be
|
5701 |
|
|
+ * read in. This cost is relative to those in TARGET_REGISTER_MOVE_COST.
|
5702 |
|
|
+ * If moving between registers and memory is more expensive that between two
|
5703 |
|
|
+ * registers, you should add this target hook to express the relative cost.
|
5704 |
|
|
+ *
|
5705 |
|
|
+ * If you do not add this target hook, GCC uses a default cost of 4 plus the
|
5706 |
|
|
+ * cost of copying via a secondary reload register, if one is needed. If your
|
5707 |
|
|
+ * machine requires a secondary reload register to copy between memory and a
|
5708 |
|
|
+ * register of CL but the reload mechanism is more complex than copying via
|
5709 |
|
|
+ * an intermediate, use this target hook to reflect the actual cost of the
|
5710 |
|
|
+ * move.
|
5711 |
|
|
+ *
|
5712 |
|
|
+ * ZipCPU --- Memory moves are more expensive than twice the cost of register
|
5713 |
|
|
+ * moves, so let's make certain this is defined.
|
5714 |
|
|
+ */
|
5715 |
|
|
+#define TARGET_MEMORY_MOVE_COST zip_memory_move_cost
|
5716 |
|
|
+
|
5717 |
|
|
+// #warning "This needs to be double checked, and annotated"
|
5718 |
111 |
dgisselq |
+#define BRANCH_COST(SPEED,PREDICTABLE) ((PREDICTABLE)?2:5)
|
5719 |
102 |
dgisselq |
+
|
5720 |
|
|
+/* Define this macro as a C expression which is nonzero if accessing less than
|
5721 |
|
|
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
|
5722 |
|
|
+ * a word of memory.
|
5723 |
|
|
+ */
|
5724 |
|
|
+#define SLOW_BYTE_ACCESS 1
|
5725 |
|
|
+
|
5726 |
|
|
+/* MOVE_RATIO(SPD) ... The threshold of number of scalar memory-to-memory move
|
5727 |
|
|
+ * instructions, below which a sequence of instructions should be generated
|
5728 |
|
|
+ * instead of a string move instruction or a library call. Increasing the
|
5729 |
|
|
+ * value will always make code faster, but eventually incurs high cost in
|
5730 |
|
|
+ * increased code size.
|
5731 |
|
|
+ */
|
5732 |
|
|
+#define MOVE_RATIO(SPD) 5
|
5733 |
|
|
+
|
5734 |
|
|
+/* TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(SZ,ALGN,OP,SPD) ...
|
5735 |
|
|
+ */
|
5736 |
|
|
+// #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)
|
5737 |
|
|
+// #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)// needs hook
|
5738 |
|
|
+
|
5739 |
|
|
+/* CLEAR_RATIO(SPD) ... The threshold number of scalar move instructions, below
|
5740 |
|
|
+ * which a sequence of instructions should be generated to clear memory instead
|
5741 |
|
|
+ * of a string clear instruction or a library call. Increasing the value will
|
5742 |
|
|
+ * always make the code faster, but eventually incurs high cost in increased
|
5743 |
|
|
+ * code size.
|
5744 |
|
|
+ */
|
5745 |
|
|
+#define CLEAR_RATIO(SPD) MOVE_RATIO(SPD)
|
5746 |
|
|
+
|
5747 |
|
|
+/* NO_FUNCTION_CSE ... Define this macro to be true if it is as good or better
|
5748 |
|
|
+ * to call a constant function address than to call an address kept in a
|
5749 |
|
|
+ * register.
|
5750 |
|
|
+ *
|
5751 |
|
|
+ * On the Zip CPU, constant function addresses--especially relative ones,
|
5752 |
|
|
+ * can be optimized into a single cycle delay. Register jumps will always
|
5753 |
|
|
+ * stall the whole (5-stage) pipeline.
|
5754 |
|
|
+ */
|
5755 |
|
|
+#define NO_FUNCTION_CSE
|
5756 |
|
|
+
|
5757 |
111 |
dgisselq |
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
|
5758 |
|
|
+ * the relative costs of RTL expressions.
|
5759 |
|
|
+ *
|
5760 |
|
|
+ * The cost may depend on the precise form of the expression, which is avaialble
|
5761 |
|
|
+ * for examination in X, and the fact that X appears as operand OPNO of an
|
5762 |
|
|
+ * expression with rtx code OUTER. That is, the hook can assume that there is
|
5763 |
|
|
+ * some RTX Y such that GET_CODE(Y)==OUTER and such that either (a) XEXP(Y,OPNO)
|
5764 |
|
|
+ * == X or (b) XVEC(Y,OPNO) contains X.
|
5765 |
|
|
+ *
|
5766 |
|
|
+ * ...
|
5767 |
|
|
+ * The hook returns true when all subexpressions of x have been processed and
|
5768 |
|
|
+ * false when rtx_cost should recurse.
|
5769 |
102 |
dgisselq |
+ */
|
5770 |
111 |
dgisselq |
+
|
5771 |
102 |
dgisselq |
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
|
5772 |
|
|
+ * addressing mode that contains ADDR. If not defined, the cost is computed
|
5773 |
|
|
+ * from the ADDR expression and the TARGET_RTX_COST hook. In cases where more
|
5774 |
|
|
+ * than one form of an address is known, the form with the lowest cost will be
|
5775 |
|
|
+ * used. If multiple forms have the same, lowest, cost, the one that is the
|
5776 |
|
|
+ * most complex will be used.
|
5777 |
|
|
+ *
|
5778 |
|
|
+ * ZipCPU really has only one address cost, the only type of address it
|
5779 |
|
|
+ * supports. Sure, index addressing would cost us more, but we don't support
|
5780 |
|
|
+ * that so ... I think we're okay defining this as a constant. Indeed, the
|
5781 |
|
|
+ * docs state that, "On RISC amchines, all instructions normally have the same
|
5782 |
|
|
+ * length and execution time. Hence all addresses will have equal costs."
|
5783 |
|
|
+ */
|
5784 |
|
|
+#undef TARGET_ADDRESS_COST
|
5785 |
|
|
+#define TARGET_ADDRESS_COST zip_address_cost
|
5786 |
|
|
+
|
5787 |
|
|
+
|
5788 |
|
|
+/* TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P ... This predicate controls the use
|
5789 |
|
|
+ * of the eager delay slot filler to disallow speculatively executed
|
5790 |
|
|
+ * instructions being placed in delay slots. Targets such as certain MIPS
|
5791 |
|
|
+ * architectures posess both branches with and without delay slots. As the
|
5792 |
|
|
+ * eager delay slot filler can decrease performance, disabling it is beneficial
|
5793 |
|
|
+ * when ordinary branches are available. Use of delay slot branches filled
|
5794 |
|
|
+ * using basic filler is often still desirable as the delay slot can hide a
|
5795 |
|
|
+ * pipeline bubble.
|
5796 |
|
|
+ */
|
5797 |
|
|
+// How should Zip CPU define this--we have no delay slots.
|
5798 |
|
|
+
|
5799 |
|
|
+
|
5800 |
|
|
+/* 17.17 Instruction Scheduler */
|
5801 |
|
|
+
|
5802 |
|
|
+#define TARGET_SCHED_ISSUE_RATE zip_sched_issue_rate
|
5803 |
|
|
+
|
5804 |
|
|
+/* 17.18 Dividing the Output into Sections */
|
5805 |
|
|
+
|
5806 |
|
|
+/* Switch to the text or data segment. */
|
5807 |
|
|
+#define TEXT_SECTION_ASM_OP "\t.text"
|
5808 |
|
|
+#define DATA_SECTION_ASM_OP "\t.data"
|
5809 |
|
|
+
|
5810 |
|
|
+// #undef TARGET_LIBGCC_SDATA_SECTION
|
5811 |
|
|
+// #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
|
5812 |
|
|
+
|
5813 |
|
|
+
|
5814 |
|
|
+/* 17.19 Position Independent Code */
|
5815 |
|
|
+
|
5816 |
|
|
+#define PIC_OFFSET_TABLE_REGNUM zip_GOT
|
5817 |
|
|
+#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 0
|
5818 |
|
|
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
|
5819 |
|
|
+
|
5820 |
|
|
+/* 17.20 Defining the Output Assembler Language */
|
5821 |
|
|
+
|
5822 |
146 |
dgisselq |
+/* 17.20.4 Output of Data */
|
5823 |
|
|
+
|
5824 |
|
|
+#undef TARGET_ASM_ALIGNED_HI_OP
|
5825 |
|
|
+#undef TARGET_ASM_ALIGNED_SI_OP
|
5826 |
|
|
+#define TARGET_ASM_UNALIGNED_HI_OP "\t.byte\t"
|
5827 |
|
|
+#define TARGET_ASM_UNALIGNED_SI_OP "\t.byte\t"
|
5828 |
|
|
+/* These hooks (above) specify assembly directives for creating certain kinds
|
5829 |
|
|
+ * of integer objects. The TARGET_ASM_BYTE_OP directive creates a byte-sized
|
5830 |
|
|
+ * object. The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
|
5831 |
|
|
+ * and so on. Any of the hookd may be NULL, indicating that no suitable
|
5832 |
|
|
+ * directive is available.
|
5833 |
|
|
+ *
|
5834 |
|
|
+ * The compiler will print these strings at the start of a new line, followed
|
5835 |
|
|
+ * immediately by the object's initial value. In most cases, the string should
|
5836 |
|
|
+ * contain a tab, a pseudo op, and then another tab.
|
5837 |
|
|
+ */
|
5838 |
|
|
+
|
5839 |
102 |
dgisselq |
+/* 17.20.4 Output and Generation of Labels */
|
5840 |
|
|
+
|
5841 |
|
|
+/* ASM_OUTPUT_LABEL
|
5842 |
|
|
+ * ... A default definition of this macro is provided which is correct for
|
5843 |
|
|
+ * most systems.
|
5844 |
|
|
+ */
|
5845 |
|
|
+
|
5846 |
|
|
+/* ASM_OUTPUT_FUNCTION_LABEL
|
5847 |
|
|
+ * ... if not defined, then the function name is defined in the usual manner
|
5848 |
|
|
+ * as a label.
|
5849 |
|
|
+ */
|
5850 |
|
|
+
|
5851 |
|
|
+/* ASM_OUTPUT_INTERNAL_LABEL ... Identical to ASM_OUTPUT_LABEL, except that name
|
5852 |
|
|
+ * is known to refer to a compiler-generated label. The default definition
|
5853 |
|
|
+ * uses assemble_name_raw, which is like assemble_name except that it is more
|
5854 |
|
|
+ * efficient.
|
5855 |
|
|
+ */
|
5856 |
|
|
+
|
5857 |
|
|
+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive
|
5858 |
|
|
+ * to specify the size of a symbol, without any arguments. ON systems that
|
5859 |
|
|
+ * use ELF, the dfault is "\t.size\t"; on other systems, the default is not to
|
5860 |
|
|
+ * define this macro.
|
5861 |
|
|
+ *
|
5862 |
|
|
+ * Define this amcro only if it is correct to use the default definitions of
|
5863 |
|
|
+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.
|
5864 |
|
|
+ * If you need your own custom definitions of those macros, or if you do not
|
5865 |
|
|
+ * need explicit symbol sizes at all, do not define this macro.
|
5866 |
|
|
+ */
|
5867 |
|
|
+
|
5868 |
|
|
+/* ASM_OUTPUT_SIZE_DIRECTIVE
|
5869 |
|
|
+ * ASM_OUTPUT_MEASURED_SIZE
|
5870 |
|
|
+ */
|
5871 |
|
|
+
|
5872 |
|
|
+/* NO_DOLLAR_IN_LABEL ... Define this macro if the assembler does not accept
|
5873 |
|
|
+ * the character '$' in label names. By default constructors and destructors
|
5874 |
|
|
+ * in G++ have "$" in the identifiers. If this label is defined, '.' is
|
5875 |
|
|
+ * used instead.
|
5876 |
|
|
+ */
|
5877 |
|
|
+
|
5878 |
|
|
+/* NO_DOT_IN_LABEL ... Define this macro if the assembler does not accept the
|
5879 |
|
|
+ * character '.' in label names. By default constructors and destructors in
|
5880 |
|
|
+ * G++ have names that use '.'. If this macro is defined, these names are
|
5881 |
|
|
+ * rewritten to avoid '.'.
|
5882 |
|
|
+ */
|
5883 |
|
|
+
|
5884 |
|
|
+/* TYPE_ASM_OP ... A C string containing the appropriate assembler directive to
|
5885 |
|
|
+ * specify the type of a symbol, without any arguments. On systems that use
|
5886 |
|
|
+ * ELF the default in config/elfos.h is "\t.type\t"; on other systems, the default is not to define this macro.
|
5887 |
|
|
+ *
|
5888 |
|
|
+ * Define this macro only if it is correct to use the default definition of
|
5889 |
|
|
+ * ASM_OUTPUT_TYPE_DIRECTIVE forr your system. If you need your own custom
|
5890 |
|
|
+ * definition of this macr, or if you do not need explicit symbol types at all,
|
5891 |
|
|
+ * do not define this macro.
|
5892 |
|
|
+ */
|
5893 |
|
|
+
|
5894 |
|
|
+/* TYPE OPERAND_FMD ... A
|
5895 |
|
|
+ */
|
5896 |
|
|
+
|
5897 |
|
|
+/* ASM_OUTPUT_TYPE_DIRECTIVE
|
5898 |
|
|
+ */
|
5899 |
|
|
+
|
5900 |
|
|
+/* ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) ...
|
5901 |
|
|
+ * if this macro is not defined, then the function name is defined in the usual
|
5902 |
|
|
+ * manner as a label (by means of ASM_OUTPUT_FUNCTION_LABEL).
|
5903 |
|
|
+ */
|
5904 |
|
|
+
|
5905 |
|
|
+/* ASM_DECLARE_FUNCTION_SIZE
|
5906 |
|
|
+ * ASM_DECLARE_COLD_FUNCTION_NAME
|
5907 |
|
|
+ * ASM_DECLARE_COLD_FUNCTION_SIZE
|
5908 |
|
|
+ * ASM_DECLARE_OBJECT_NAME
|
5909 |
|
|
+ * TARGET_ASM_DECLARE_CONSTANT_NAME
|
5910 |
|
|
+ */
|
5911 |
|
|
+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement
|
5912 |
|
|
+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for
|
5913 |
|
|
+ * claiming a register REGNO for a global variable DECL with name NAME.
|
5914 |
|
|
+ *
|
5915 |
|
|
+ * If you don't defin this macro, that is equivalent to dfining it to do
|
5916 |
|
|
+ * nothing.
|
5917 |
|
|
+ */
|
5918 |
|
|
+
|
5919 |
|
|
+/* ASM_FINISH_DECLARE_OBJECT
|
5920 |
|
|
+ * TARGET_ASM_GLOBALIZE_LABEL
|
5921 |
|
|
+ * TARGET_ASM_GLOBALIZE_DECL_NAME
|
5922 |
|
|
+ * TARGET_ASM_ASSEMBLE_UNDEFINED_DECL
|
5923 |
|
|
+ * ASM_WEAKEN_LABEL
|
5924 |
|
|
+ * ASM_WEAKEN_DECL
|
5925 |
|
|
+ * ASM_OUTPUT_WEAKREF
|
5926 |
|
|
+ * SUPPORTS_WEAK
|
5927 |
|
|
+ * TARGET_SUPPORTS_WEAK
|
5928 |
|
|
+ * MAKE_DECL_ONE_ONLY
|
5929 |
|
|
+ * SUPPORTS_ONE_ONLY
|
5930 |
|
|
+ * TARGTE_ASM_ASSEMBLE_VISIBILITY
|
5931 |
|
|
+ * TARGET_WEAK_NOT_IN_ARCHIVE_TOC
|
5932 |
|
|
+ * ASM_OUTPUT_EXTERNAL
|
5933 |
|
|
+ * TARGET_ASM_EXTERNAL_LIBCALL
|
5934 |
|
|
+ * TARGET_ASM_MARK_DECLPRESERVED
|
5935 |
|
|
+ * ASM_OUTPUT_LABELREF
|
5936 |
|
|
+ * TARGET_MANGLE_ASSEMBLER_NAME
|
5937 |
|
|
+ * ASM_OUTPUT_SYMBOL_REF
|
5938 |
|
|
+ * ASM_OUTPUT_LABEL_REF
|
5939 |
|
|
+ * TARGET_ASM_INTERNAL_LABEL
|
5940 |
|
|
+ * ASM_OUTPUT_DEBUG_LABEL
|
5941 |
|
|
+ * ASM_GENERATE_INTERNAL_LABEL
|
5942 |
|
|
+ * ASM_FORMAT_PRIVATE_NAME
|
5943 |
|
|
+ */
|
5944 |
|
|
+
|
5945 |
|
|
+/* ASM_OUTPUT_DEF ... A C statement to output to the stdio stream STREAM
|
5946 |
|
|
+ * assembler code which defines (equates) the symbol NAME to have the value
|
5947 |
|
|
+ * VALUE.
|
5948 |
|
|
+ *
|
5949 |
|
|
+ * ZipCPU---So many other things that we need depend upon this, that we need
|
5950 |
|
|
+ * to implement a non-default version.
|
5951 |
|
|
+ */
|
5952 |
|
|
+#define ASM_OUTPUT_DEF zip_asm_output_def
|
5953 |
|
|
+
|
5954 |
|
|
+/* ASM_OUTPUT_DEF_FROM_DECLS
|
5955 |
|
|
+ * TARGET_DEFERRED_OUTPUT_DEFS
|
5956 |
|
|
+ * ASM_OUTPUT_WEAK_ALIAS
|
5957 |
|
|
+ * OBJ_GEN_METHOD_LABEL
|
5958 |
|
|
+ */
|
5959 |
|
|
+
|
5960 |
|
|
+
|
5961 |
|
|
+/* 17.20.7 Output of Assembler Instructions */
|
5962 |
|
|
+
|
5963 |
171 |
dgisselq |
+#define REGISTER_NAMES { \
|
5964 |
|
|
+ "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
|
5965 |
|
|
+ "R8", "R9", "R10", "R11", "R12", "SP", "CC", "PC", \
|
5966 |
|
|
+ "uR0","uR1","uR2", "uR3", "uR4", "uR5","uR6","uR7", \
|
5967 |
|
|
+ "uR8","uR9","uR10","uR11","uR12","uSP","uCC","uPC", \
|
5968 |
|
|
+ "PSEUDO-AP" }
|
5969 |
102 |
dgisselq |
+
|
5970 |
|
|
+/* REGISTER_PREFIX (Undefined by default)
|
5971 |
|
|
+ * LOCAL_LABEL_PREFIX (Undefined by default)
|
5972 |
|
|
+ * USER_LABEL_PREFIX defaults to "*"
|
5973 |
|
|
+ * IMMEDIATE_PREFIX (Undefined by default)
|
5974 |
|
|
+ *
|
5975 |
|
|
+ * If defined, C string expressions to be used for the '%R', '%L', '%U', and
|
5976 |
|
|
+ * '%I' options of asm_fprintf (see 'final.c'). These are useful when a single
|
5977 |
|
|
+ * 'md' file must support multiple assembler formats. In that case, the various
|
5978 |
|
|
+ * 'tm.h' files can define these macros differently.
|
5979 |
|
|
+ */
|
5980 |
|
|
+// #define USER_LABEL_PREFIX "*"
|
5981 |
|
|
+
|
5982 |
|
|
+/* Defining memory operand address formats is in this section. */
|
5983 |
|
|
+
|
5984 |
|
|
+/* 17.20.10 Assembler Commands for Alignment */
|
5985 |
|
|
+
|
5986 |
|
|
+/* JUMP_ALIGN(label) ... The alignment (log base 2) to put in front of label,
|
5987 |
|
|
+ * which is a common destination of jumps and has no fallthru incoming
|
5988 |
|
|
+ * edge. This macro need not be defined if you don't want any special alignment
|
5989 |
|
|
+ * to be done at such a time. Most machine descriptions do not currently define
|
5990 |
|
|
+ * this macro.
|
5991 |
|
|
+ *
|
5992 |
|
|
+ * ZipCPU---The assembler should automatically deal with label alignment, so
|
5993 |
|
|
+ * let's not do anything about it here.
|
5994 |
|
|
+ */
|
5995 |
|
|
+
|
5996 |
|
|
+/* TARGET_ASM_JUMP_ALIGN_MAX_SKIP
|
5997 |
|
|
+ */
|
5998 |
|
|
+
|
5999 |
|
|
+/* LABEL_ALIGN_AFTER_BARRIER
|
6000 |
|
|
+ * TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
|
6001 |
|
|
+ */
|
6002 |
|
|
+
|
6003 |
|
|
+/* LOOP_ALIGN(label)
|
6004 |
|
|
+ * TARGET_ASM_LOOP_ALIGN_MAX_SKIP
|
6005 |
|
|
+ * LABEL_ALIGN
|
6006 |
|
|
+ * TARGET_ASM_LABEL_ALIGN_MAX_SKIP
|
6007 |
|
|
+ */
|
6008 |
|
|
+
|
6009 |
|
|
+/* ASM_OUTPUT_SKIP(STREAM, NBYTES) A C statement to output to the stdio
|
6010 |
|
|
+ * stream an assembler instruction to advance the location counter by nbytes
|
6011 |
|
|
+ * bytes.
|
6012 |
|
|
+ */
|
6013 |
|
|
+
|
6014 |
|
|
+/* TARGET_ASM_LABEL_ALIGN */
|
6015 |
|
|
+/* Assembler Commands for Alignment */
|
6016 |
|
|
+#define ASM_OUTPUT_ALIGN(STREAM,POWER) \
|
6017 |
127 |
dgisselq |
+ { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
|
6018 |
102 |
dgisselq |
+
|
6019 |
|
|
+
|
6020 |
|
|
+
|
6021 |
|
|
+/* 17.21 Controlling Debugging Information Format */
|
6022 |
|
|
+/* 17.22 Cross Compilation and Floating Point */
|
6023 |
111 |
dgisselq |
+
|
6024 |
|
|
+// REAL_VALUE_TYPE
|
6025 |
|
|
+// REAL_VALUES_EQUAL
|
6026 |
|
|
+// REAL_VALUES_LESS ... Tess whether x is less than y
|
6027 |
|
|
+/* REAL_VALUE_FIX ... Truncates x to an unsigned integer, rouding toward zero.
|
6028 |
|
|
+ * If x is negative, returns zero.
|
6029 |
|
|
+ */
|
6030 |
|
|
+// REAL_VALUE_ATOF
|
6031 |
|
|
+// REAL_VALUE_NEGATIVE
|
6032 |
|
|
+// REAL_VALUE_ISINF
|
6033 |
|
|
+// REAL_VALUE_ISNAN
|
6034 |
|
|
+/* REAL_ARITHMETIC(OUT,CODE,X,Y) ... (Macro) Calculates an arithmetic operation
|
6035 |
|
|
+ * on two floating point values X and Y, storing the result in OUT (which must
|
6036 |
|
|
+ * be a variable).
|
6037 |
|
|
+ *
|
6038 |
|
|
+ * The operation to be performed is specified by CODE. Only the following
|
6039 |
|
|
+ * codes are supported: PLUS_EXPR, MINUS_EXPR, MULT_EXPR, RDIV_EXPR, MAX_EXPR,
|
6040 |
|
|
+ * MIN_EXPR.
|
6041 |
|
|
+ *
|
6042 |
|
|
+ * If REAL_ARITHMETIC is asked to evaluate division by zero and the target's
|
6043 |
|
|
+ * floating point format cannot represent infinity, it will call abort().
|
6044 |
|
|
+ * Callers shoudl check for this situation first, using MODE_HAS_INFINITIES.
|
6045 |
|
|
+ */
|
6046 |
|
|
+/* REAL_VALUE_NEGATE(X) ... [Macro] Returns the negative of the floating point
|
6047 |
|
|
+ * value X.
|
6048 |
|
|
+ */
|
6049 |
|
|
+/* REAL_VALUE_ABS(X) ... [Macro] Returns the absolute value of X.
|
6050 |
|
|
+ */
|
6051 |
102 |
dgisselq |
+/* 17.23 Mode switching instructions */
|
6052 |
|
|
+/* 17.24 Defining target-specific uses of __attribute__ */
|
6053 |
|
|
+#undef TARGET_OPTION_OVERRIDE
|
6054 |
|
|
+#define TARGET_OPTION_OVERRIDE zip_override_options
|
6055 |
|
|
+
|
6056 |
|
|
+/* 17.25 Emulating TLS */
|
6057 |
|
|
+/* 17.26 Defining coprocessor specifics for MIPS targets*/
|
6058 |
|
|
+
|
6059 |
|
|
+ // ZipCPU isn't MIPS.
|
6060 |
|
|
+
|
6061 |
|
|
+/* 17.27 Parameters for Precompiled Header Validity Checking */
|
6062 |
|
|
+/* 17.28 C++ ABI parameters */
|
6063 |
|
|
+/* 17.29 Adding support for named address spaces */
|
6064 |
|
|
+/* 17.30 Miscellaneous Parameters */
|
6065 |
|
|
+
|
6066 |
|
|
+/* HAS_LONG_COND_BRANCH ... Define this boolean macro to indicate whether or
|
6067 |
|
|
+ * not your architecture has conditional branches that can span all of memory.
|
6068 |
|
|
+ * It is used in conjunction with an optimization that partitions hot and
|
6069 |
|
|
+ * cold basic blocks into separate sections of the executable. If this macro
|
6070 |
|
|
+ * is set to false, gcc will convert any conditional branches that attempt to
|
6071 |
|
|
+ * cross between sections into unconditional branches or indirect jumps.
|
6072 |
|
|
+ *
|
6073 |
|
|
+ * ZipCPU --- The assembler renders long unconditional branch code without
|
6074 |
|
|
+ * problems, so we can pretend that such long branches exist.
|
6075 |
|
|
+ */
|
6076 |
|
|
+#define HAS_LONG_COND_BRANCH true
|
6077 |
|
|
+
|
6078 |
|
|
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
|
6079 |
|
|
+ * or not your architecture has unconditional branches that can span all of
|
6080 |
|
|
+ * memory. (ZipCPU does ... via the LOD (PC),PC instruction.) It is used in
|
6081 |
|
|
+ * conjunction with an optimization that partitions hot and cold basic blocks
|
6082 |
|
|
+ * into separate sections of the executable. If this macro is set to false,
|
6083 |
|
|
+ * gcc will convert any unconditional branches that attempt to cross between
|
6084 |
|
|
+ * sections into indirect jumps.
|
6085 |
|
|
+ *
|
6086 |
|
|
+ * ZipCPU has the LOD (PC),PC instruction which can be used to implement a long
|
6087 |
|
|
+ * jump.
|
6088 |
|
|
+ */
|
6089 |
|
|
+#define HAS_LONG_UNCOND_BRANCH true
|
6090 |
|
|
+
|
6091 |
|
|
+/* CASE_VECTOR_MODE ... An alias for a machine mode name. This is the machine
|
6092 |
|
|
+ * mode that eleemnts of a jump-table should have.
|
6093 |
|
|
+ *
|
6094 |
|
|
+ */
|
6095 |
|
|
+#define CASE_VECTOR_MODE SImode
|
6096 |
|
|
+
|
6097 |
|
|
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
|
6098 |
|
|
+ * mode for an addr_diff_vec when the minimum and maximum offset are known.
|
6099 |
|
|
+ * If you define this, it enables extra code in branch shortening to deal with
|
6100 |
|
|
+ * addr_diff_vec. To make this work, you also have to define INSN_ALIGN and
|
6101 |
|
|
+ * make the alignment for addr_diff_vec explicit. The body argument is provided so that the offset_unsigned and scale flags can be updated.
|
6102 |
|
|
+ *
|
6103 |
|
|
+ * ZipCPU---No advantage here.
|
6104 |
|
|
+ */
|
6105 |
|
|
+
|
6106 |
|
|
+/* CASE_VECTOR_PC_RELATIVE ... Define this exrpession to indicate when
|
6107 |
|
|
+ * jump-tables should contain relative addresses. You need not define this
|
6108 |
|
|
+ * macro if jump-tables never contain relative addresses, or jump-tables
|
6109 |
|
|
+ * should contain relative addresses only when -fPIC or -FPIC is in effect.
|
6110 |
|
|
+ *
|
6111 |
|
|
+ * ZipCPU---No advantage in PC-Relative jump tables--except in PIC relative
|
6112 |
|
|
+ * code.
|
6113 |
|
|
+ */
|
6114 |
|
|
+
|
6115 |
|
|
+/* TARGET_CASE_VALUES_THRESHOLD(VOID) ... This function returns the smallest
|
6116 |
|
|
+ * number of different values for which it is best to use a jump-table instead
|
6117 |
|
|
+ * of a tree of conditional branches. The default is four for machines with a
|
6118 |
|
|
+ * casesi instruction and five otherwise. This is best for most machines.
|
6119 |
|
|
+ *
|
6120 |
|
|
+ * ZipCPU---Leave at the default.
|
6121 |
|
|
+ */
|
6122 |
|
|
+
|
6123 |
|
|
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between
|
6124 |
|
|
+ * registers with integral mode smaller than a word are always performed on the
|
6125 |
|
|
+ * entire register. Most RISC machines have this property and most CISC
|
6126 |
|
|
+ * machines do not.
|
6127 |
|
|
+ *
|
6128 |
|
|
+ * ZipCPU---We have the property, 'cause we're fairly risk.
|
6129 |
|
|
+ */
|
6130 |
|
|
+#undef WORD_REGISTER_OPERATIONS
|
6131 |
|
|
+#define WORD_REGISTER_OPERATIONS 1
|
6132 |
|
|
+
|
6133 |
|
|
+/* LOAD_EXTEND_OP(MEMODE) ... Define this macro to be a C expression indicating
|
6134 |
|
|
+ * when insns that read memory in MEMMODE, an integral mode narrower than a
|
6135 |
|
|
+ * word, set the bits outside of MEMMODE to be either the sign extension or
|
6136 |
|
|
+ * zero-extension of the data read. Return SIGN_EXTEND for values of MEMMODE
|
6137 |
|
|
+ * for which the insn sign-extends, ZERO_EXTEND for which it zero-extends, and
|
6138 |
|
|
+ * UNKNOWN for other modes.
|
6139 |
|
|
+ *
|
6140 |
|
|
+ * Do not define this macro if it would always return UNKNOWN.
|
6141 |
|
|
+ *
|
6142 |
|
|
+ * ZipCPU---This should be irrelevant, so we leave it undefined.
|
6143 |
|
|
+ */
|
6144 |
|
|
+#undef LOAD_EXTEND_OP
|
6145 |
|
|
+#define LOAD_EXTEND_OP(MEM) SIGN_EXTEND
|
6146 |
|
|
+
|
6147 |
|
|
+/* SHORT_IMMEDIATES_SIGN_EXTEND ... Define this macro to 1 if loading short immediate values into registers sign extends.
|
6148 |
|
|
+ *
|
6149 |
|
|
+ * ZipCPU---All immediates are sign extended, so yes.
|
6150 |
|
|
+ */
|
6151 |
|
|
+#undef SHORT_IMMEDIATES_SIGN_EXTEND
|
6152 |
|
|
+#define SHORT_IMMEDIATES_SIGN_EXTEND 1
|
6153 |
|
|
+
|
6154 |
|
|
+/* TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
|
6155 |
|
|
+ */
|
6156 |
|
|
+
|
6157 |
|
|
+/* MOVE_MAX ... The maximum number of bytes that a single instruction can move
|
6158 |
|
|
+ * quickly between memory and registers or between two memory locations.
|
6159 |
|
|
+ *
|
6160 |
|
|
+ * ZipCPU --- Although we can move 32-bits at a time, and most people would call
|
6161 |
|
|
+ * this 4-bytes, the compiler defines a byte as the minimum addressable unit.
|
6162 |
|
|
+ * Therefore, this is defined to be one.
|
6163 |
|
|
+ */
|
6164 |
|
|
+#define MOVE_MAX 1
|
6165 |
|
|
+
|
6166 |
|
|
+/* MAX_MOVE_MAX ... The maximum number of bytes that a single instruction can
|
6167 |
|
|
+ * move quickly between memory and registers or between two memory ...
|
6168 |
|
|
+ *
|
6169 |
|
|
+ * ZipCPU --- this sounds just the same as MOVE_MAX, which is the default
|
6170 |
|
|
+ * definition of this.
|
6171 |
|
|
+ */
|
6172 |
|
|
+
|
6173 |
|
|
+/* SHIFT_COUNT_TRUNCATED ... A C expression that is nonzero if on this machine
|
6174 |
|
|
+ * the number of bits actually used for the count of a shift operation is equal
|
6175 |
|
|
+ * to the number of bits needed to represent the size of the object being
|
6176 |
|
|
+ * shifted.
|
6177 |
|
|
+ *
|
6178 |
|
|
+ * You need not define this macro if it would have the value of zero.
|
6179 |
|
|
+ *
|
6180 |
|
|
+ * ZipCPU---A shift of 33 (or more) in either direction will wipe out the
|
6181 |
|
|
+ * value in the register, therefore this value should be zero, the default.
|
6182 |
|
|
+ */
|
6183 |
|
|
+
|
6184 |
|
|
+/* TARGET_SHIFT_TRUNCATION_MASK(MODE) ... This function describes how the
|
6185 |
|
|
+ * standard shift patterns for MODE deal with shifts by negative amounts or by
|
6186 |
|
|
+ * more than the width of the mode.
|
6187 |
|
|
+ *
|
6188 |
|
|
+ * ZipCPU---The default is zero, since we didn't define SHIFT_COUNT_TRUNCATED.
|
6189 |
|
|
+ * This is the case for the ZipCPU as well.
|
6190 |
|
|
+ */
|
6191 |
|
|
+
|
6192 |
|
|
+/* TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) ... A C expression which is nonzero
|
6193 |
|
|
+ * if on this machine it is safe to "convert" an integer of INPREC bits to one
|
6194 |
|
|
+ * of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on
|
6195 |
|
|
+ * it as if it had OUTPREC bist. On many machines, this expression can be 1.
|
6196 |
|
|
+ *
|
6197 |
|
|
+ * ZiPCPU ... If both values are 32-bit, what conversion takes place? If one is
|
6198 |
|
|
+ * 64-bit and the other 32-bit ... I suppose it would then be safe.
|
6199 |
|
|
+ */
|
6200 |
|
|
+#undef TRULY_NOOP_TRUNCATION
|
6201 |
|
|
+#define TRULY_NOOP_TRUNCATION(O,I) 1
|
6202 |
|
|
+
|
6203 |
|
|
+/* TARGET_MODE_REP_EXTENDED(MODE,REPMODE) ... The representation of an integral
|
6204 |
|
|
+ * mode can be such that the values are always extended to a wider integral
|
6205 |
|
|
+ * mode. Return SIGN_EXTEND if values of MODE are represented in sign-extended
|
6206 |
|
|
+ * form to REPMODE. Return UNKNOWN otherwise. (Currently none of the targets
|
6207 |
|
|
+ * use zero-extended.
|
6208 |
|
|
+ *
|
6209 |
|
|
+ */
|
6210 |
|
|
+// #undef TARGET_MODE_REP_EXTENDED
|
6211 |
|
|
+// #define TARGET_MODE_REP_EXTENDED(R,M) SIGN_EXTEND
|
6212 |
|
|
+
|
6213 |
|
|
+/* STORE_FLAG_VALUE ... A C expression describing the value returned by a
|
6214 |
|
|
+ * comparison operator with an integral mode and stored by a store-flag
|
6215 |
|
|
+ * instruction (cstoremode4) when the condition is true. This description
|
6216 |
|
|
+ * must apply to all the cstoremode4 patterns and all the comparison operators
|
6217 |
|
|
+ * whose results have MODE_INT mode.
|
6218 |
|
|
+ *
|
6219 |
|
|
+ * ZipCPU---Doesn't really have a STORE_FLAG_VALUE instruction ...
|
6220 |
|
|
+ */
|
6221 |
|
|
+
|
6222 |
|
|
+/* FLOAT_STORE_FLAG_VALUE
|
6223 |
|
|
+ *
|
6224 |
|
|
+ * ZipCPU
|
6225 |
|
|
+ */
|
6226 |
|
|
+
|
6227 |
|
|
+/* VECTOR_STORE_FLAG_VALUE ... define this macro on machines that have vector
|
6228 |
|
|
+ * comparison operations that return a vector result ...
|
6229 |
|
|
+ *
|
6230 |
|
|
+ * ZipCPU---Doesn't support vector operations.
|
6231 |
|
|
+ */
|
6232 |
|
|
+
|
6233 |
|
|
+/* CLZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
|
6234 |
|
|
+ * CTZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
|
6235 |
|
|
+ *
|
6236 |
|
|
+ * A C expression that indicates whetther the architecture defines a value for
|
6237 |
|
|
+ * clz or ctz with a zero operand. A result of 0 indicates the value is
|
6238 |
|
|
+ * undefined. If the value is defined for only the RTL expression, the macro should evaluate to 1. If the value also applies to the corresponding optab
|
6239 |
|
|
+ * entry, then the macro should evaluate to 2. In cases where the value is
|
6240 |
|
|
+ * defined, value should be set to this value.
|
6241 |
|
|
+ * If this macro is not defined, the value of clz or ctz at zero is assumed to
|
6242 |
|
|
+ * be undefined.
|
6243 |
|
|
+ *
|
6244 |
|
|
+ * ZipCPU---Has neither clz nor ctz instructions, so we don't need this.
|
6245 |
|
|
+ */
|
6246 |
|
|
+
|
6247 |
|
|
+/* Pmode ... An alias for the machine mode for pointers. On most machines,
|
6248 |
|
|
+ * define this to be the integer mode corresponding to the width of a
|
6249 |
|
|
+ * hardware pointer. SImode on 32-bits machines, or DImode on 64-bit machines.
|
6250 |
|
|
+ * On some machines you must define this to be one of the partial
|
6251 |
|
|
+ * integer modes, such as PSImode.
|
6252 |
|
|
+ */
|
6253 |
|
|
+#undef Pmode
|
6254 |
|
|
+#define Pmode SImode
|
6255 |
|
|
+
|
6256 |
|
|
+/* FUNCTION_MODE ... An alais for the machine mode used for memory references to
|
6257 |
|
|
+ * function being called, in call RTL expressions. On most CISC machines, where
|
6258 |
|
|
+ * an instruction can begin at any byte address, this should be QImode. On most
|
6259 |
|
|
+ * RISC machines, where all instructions have fixed size and alignment, this
|
6260 |
|
|
+ * should be a mode with the same size and alignment as the machine instruction
|
6261 |
|
|
+ * words--typically SImode or HImode.
|
6262 |
|
|
+ *
|
6263 |
|
|
+ * ZipCPU---Definitely SImode, as with Pmode. (All words are 32-bits, including
|
6264 |
|
|
+ * addresses on the ZipCPU.
|
6265 |
|
|
+ */
|
6266 |
|
|
+#undef FUNCTION_MODE
|
6267 |
|
|
+#define FUNCTION_MODE SImode
|
6268 |
|
|
+
|
6269 |
|
|
+/* STDC_0_IN_SYSTEM_HEADERS
|
6270 |
|
|
+ */
|
6271 |
|
|
+
|
6272 |
|
|
+/* TARGET_C_PREINCLUDE(V) ... Define this hook to return the name of a header
|
6273 |
|
|
+ * file to be included at the start of all compilations, as if it had been
|
6274 |
|
|
+ * included with #include <file>. If this hook returns NULL, or is not defined,
|
6275 |
|
|
+ * or if the header is not found, or if the user specifies -ffreestanding or
|
6276 |
|
|
+ * -nostdinc, no header is included.
|
6277 |
|
|
+ *
|
6278 |
|
|
+ * ZipCPU --- We don't have a standard library defined yet, so we'll leave this
|
6279 |
|
|
+ * as NULL.
|
6280 |
|
|
+ */
|
6281 |
|
|
+#undef TARGET_C_PREINCLUDE
|
6282 |
|
|
+#define TARGET_C_PREINCLUDE NULL
|
6283 |
|
|
+
|
6284 |
|
|
+/* TARGET_CXX_IMPLICIT_EXTERN_C(CONST CHAR *) ... Define this hook to add target
|
6285 |
|
|
+ * specific C++ implicit extern C functions. If this function returns true
|
6286 |
|
|
+ * for the name of a file-scope function, that function implicitly gets extern
|
6287 |
|
|
+ * "C" linkage rather than whatever linkage the declaration would normally have.
|
6288 |
|
|
+ * An example of such function is WinMain on Win32 targets.
|
6289 |
|
|
+ *
|
6290 |
|
|
+ * ZipCPU---Not ready to deal with this yet.
|
6291 |
|
|
+ */
|
6292 |
|
|
+
|
6293 |
|
|
+/* NO_IMPLICIT_EXTERN_C ... Define this macro if the system header files
|
6294 |
|
|
+ * support C++ as well as C. This macro inhibits the usual method of using
|
6295 |
|
|
+ * system header files in C++, which is to pretend that the file's contents
|
6296 |
|
|
+ * are enclosed in 'extern "C" {...}'.
|
6297 |
|
|
+ *
|
6298 |
|
|
+ *
|
6299 |
|
|
+ * ZipCPU --- Don't have either C or C++ headers, so let's skip this for now.
|
6300 |
|
|
+ * Eventually, though, I think ZipCPU and C++ would go very well together.
|
6301 |
|
|
+ */
|
6302 |
|
|
+
|
6303 |
|
|
+/* REGISTER_TARGET_PRAGMAS ... Define this macro if you want to implement any
|
6304 |
|
|
+ * target specific pragmas.
|
6305 |
|
|
+ *
|
6306 |
|
|
+ * ZipCPU --- let's not.
|
6307 |
|
|
+ */
|
6308 |
|
|
+
|
6309 |
|
|
+/* HANDLE_PRAGMA_PACK_WITH_EXPANSION ... Define this macro if macros should be
|
6310 |
|
|
+ * expanded in the arguments of #pragma pack().
|
6311 |
|
|
+ *
|
6312 |
|
|
+ * ZipCPU ... why?
|
6313 |
|
|
+ */
|
6314 |
|
|
+
|
6315 |
|
|
+/* TARGET_DEFAULT_PACK_STRUCT ... If your target requires a struct packing
|
6316 |
|
|
+ * default other than 0 (meaning the machine default), define this macro to
|
6317 |
|
|
+ * the necessary value (in bytes). This must be a value that would also be
|
6318 |
|
|
+ * valid to use with #pragma pack() (that is a small power of two.
|
6319 |
|
|
+ */
|
6320 |
|
|
+
|
6321 |
|
|
+/* DOLLARS_IN_IDENTIFIERS
|
6322 |
|
|
+ * ZipCPU --- Default (not changing C)
|
6323 |
|
|
+ */
|
6324 |
|
|
+
|
6325 |
|
|
+/* INSN_SETS_ARE_DELAYED(INSN) ... Define this macro as a C expression that
|
6326 |
|
|
+ * is nonzero if it is safe for the delay slot schedule to place instructions
|
6327 |
|
|
+ * in the delay slot of INSN, even if they appear to use a resource set or
|
6328 |
|
|
+ * clobbered in INSN. INSN is always a ...
|
6329 |
|
|
+ *
|
6330 |
|
|
+ * ZipCPU --- You need not define this macro if it would always return zero.
|
6331 |
|
|
+ */
|
6332 |
|
|
+
|
6333 |
|
|
+/* INSN_REFERENCES_ARE_DELAYED(INSN) ... Define this macro as a C expression
|
6334 |
|
|
+ * that is nonzero if it is safe for the delay slot schedule to place
|
6335 |
|
|
+ * instructions in the delay slot of INSN, even if they appear to set or clobber
|
6336 |
|
|
+ * a resource referenced in INSN. INSN is always a jump_insn or an insn. On
|
6337 |
|
|
+ * machines where some insn or jump_insn is really a function call and ...
|
6338 |
|
|
+ *
|
6339 |
|
|
+ * ZipCPU --- You need not define this macro if it would always return zero.
|
6340 |
|
|
+ */
|
6341 |
|
|
+
|
6342 |
|
|
+/* MULTIPLE_SYMBOL_SPACES ... Define this macro as a C expression that is
|
6343 |
|
|
+ * nonzero if, in some cases, global symbols from one translation unit may not
|
6344 |
|
|
+ * be bound to undefined symbols in another translation unit without user
|
6345 |
|
|
+ * intervention. For instance, under Microsoft Windows symbols must be
|
6346 |
|
|
+ * explicitly imported from shared libraries (DLLs).
|
6347 |
|
|
+ *
|
6348 |
|
|
+ * ZipCPU---You need not define this macro if it would always evaluate to zero,
|
6349 |
|
|
+ * so we won't.
|
6350 |
|
|
+ */
|
6351 |
|
|
+
|
6352 |
|
|
+/* TARGET_MD_ASM_ADJUST
|
6353 |
|
|
+ */
|
6354 |
|
|
+/* MATH_LIBRARY ... Define this macro as a C constant ... you only need to
|
6355 |
|
|
+ * define this macro if the default of "m" is wrong.
|
6356 |
|
|
+ *
|
6357 |
|
|
+ * ZipCPU --- as we don't have a math library yet, building one such that "m"
|
6358 |
|
|
+ * works doesn't sound like a problem. Let's not define this.
|
6359 |
|
|
+ */
|
6360 |
|
|
+
|
6361 |
|
|
+/* LIBRARY_PATH_ENV ... Define this as a C string constant for the environment
|
6362 |
|
|
+ * variable that specifies where the linker should look for libraries.
|
6363 |
|
|
+ *
|
6364 |
|
|
+ * Just in case we want to add libraries for ZipCPU, let's place them in
|
6365 |
|
|
+ * /usr/local/zip/lib, so as not to confuse them with our local systems
|
6366 |
|
|
+ * libraries.
|
6367 |
|
|
+ */
|
6368 |
|
|
+#define LIBRARY_PATH_ENV "/usr/local/zip/lib"
|
6369 |
|
|
+
|
6370 |
|
|
+/* TARGET_POSIX_IO ... Define this macro if the target supports the following
|
6371 |
|
|
+ * POSIX file fucntions: access, mkdir, and file locking with fcntl/F_SETLKW.
|
6372 |
|
|
+ *
|
6373 |
|
|
+ * ZipCPU does not.
|
6374 |
|
|
+ */
|
6375 |
|
|
+
|
6376 |
|
|
+/* MAX_CONDITIONAL_EXECUTE ... A C expression for the maximum number of
|
6377 |
|
|
+ * instructions to execute via conditional execution instructions instead of a
|
6378 |
|
|
+ * branch. A value of BRANCH_COST+1 is the default if the machine does not use
|
6379 |
|
|
+ * cc0 and 1 if it does use cc0.
|
6380 |
|
|
+ *
|
6381 |
|
|
+ * ZipCPU---This sounds good enough for the ZipCPU as well--as long as we have
|
6382 |
|
|
+ * BRANCH_COST defined. However, BRANCH_COST is defined as conditionally to
|
6383 |
|
|
+ * something else, so let's keep looking into this.
|
6384 |
|
|
+ */
|
6385 |
|
|
+
|
6386 |
|
|
+/* IFCVT_MODIFY_TESTS(CEINFO,TRUE,FALSE) ... Used if the target needs to
|
6387 |
103 |
dgisselq |
+ * perform machine-dependent modifications on the conditionals used for turning
|
6388 |
102 |
dgisselq |
+ * basic blocks into conditionally executed code. CEINFO points to a data
|
6389 |
|
|
+ * structure, struct ce_if_block, which contains information about the currently
|
6390 |
|
|
+ * processed blocks. TRUE and FALSE are the tests that are used for
|
6391 |
|
|
+ * converting the then-block and the else-block, respectively. Set either TRUE
|
6392 |
|
|
+ * or FALSE to a null pointer if the tests cannot be converted.
|
6393 |
|
|
+ *
|
6394 |
|
|
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
|
6395 |
|
|
+ * execution and conditional testing capabilities.
|
6396 |
|
|
+ */
|
6397 |
122 |
dgisselq |
+#define IFCVT_MODIFY_TESTS(CI,TR,FL) zip_ifcvt_modify_tests(CI,&TR,&FL)
|
6398 |
102 |
dgisselq |
+
|
6399 |
|
|
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like
|
6400 |
|
|
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements
|
6401 |
|
|
+ * into conditions combined by and and or operations. BB contains the basic
|
6402 |
|
|
+ * block that contains the test that is currently being processed and about to
|
6403 |
|
|
+ * be turned into a condition.
|
6404 |
|
|
+ *
|
6405 |
|
|
+ *
|
6406 |
|
|
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
|
6407 |
|
|
+ * execution and conditional testing capabilities.
|
6408 |
|
|
+ */
|
6409 |
|
|
+// #warning "Need to come back to this."
|
6410 |
122 |
dgisselq |
+#define IFCVT_MODIFY_MULTIPLE_TESTS(CI,BB,TR,FL) TR=NULL_RTX
|
6411 |
102 |
dgisselq |
+
|
6412 |
|
|
+
|
6413 |
|
|
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the
|
6414 |
|
|
+ * PATTERN of an INSN that is to be converted to conditional execution format.
|
6415 |
|
|
+ * CEINFO points to a data structure, struct ce_if_block, which contains
|
6416 |
|
|
+ * information about the currently processed blocks.
|
6417 |
|
|
+ *
|
6418 |
|
|
+ *
|
6419 |
|
|
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
|
6420 |
|
|
+ * execution and conditional testing capabilities.
|
6421 |
|
|
+ */
|
6422 |
142 |
dgisselq |
+#define IFCVT_MODIFY_INSN(CE,PATRN,INSN) zip_ifcvt_modify_insn(CE,PATRN,INSN)
|
6423 |
102 |
dgisselq |
+
|
6424 |
|
|
+
|
6425 |
|
|
+/* IFCVT_MODIFY_FINAL(CEINFO) ... A C expression to perform any final
|
6426 |
|
|
+ * machine dependent modifications in converting code to conditional
|
6427 |
|
|
+ * execution. The involved basic blocks can be found in struct ce_if_block
|
6428 |
|
|
+ * structure pointed to be CEINFO.
|
6429 |
|
|
+ *
|
6430 |
|
|
+ *
|
6431 |
|
|
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
|
6432 |
|
|
+ * execution and conditional testing capabilities.
|
6433 |
|
|
+ */
|
6434 |
|
|
+// #warning "Need to come back to this."
|
6435 |
122 |
dgisselq |
+#define IFCVT_MODIFY_FINAL(CEINFO) zip_ifcvt_modify_final(CEINFO)
|
6436 |
102 |
dgisselq |
+
|
6437 |
|
|
+
|
6438 |
|
|
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine
|
6439 |
|
|
+ * dependent modifications in converting code to conditional execution. The
|
6440 |
|
|
+ * involved basic blocks can be found in the struct ce_if_block structure that
|
6441 |
|
|
+ * is pointed to by CEINFO.
|
6442 |
|
|
+ *
|
6443 |
|
|
+ *
|
6444 |
|
|
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
|
6445 |
|
|
+ * execution and conditional testing capabilities.
|
6446 |
|
|
+ */
|
6447 |
|
|
+// #warning "Need to come back to this."
|
6448 |
122 |
dgisselq |
+#define IFCVT_MODIFY_CANCEL(CEINFO) zip_ifcvt_modify_cancel(CEINFO)
|
6449 |
102 |
dgisselq |
+
|
6450 |
|
|
+
|
6451 |
|
|
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine
|
6452 |
|
|
+ * specific data for if-conversion of the if-block in the CEINFO block structure
|
6453 |
|
|
+ * that is pointed by CEINFO.
|
6454 |
|
|
+ *
|
6455 |
|
|
+ *
|
6456 |
|
|
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
|
6457 |
|
|
+ * execution and conditional testing capabilities.
|
6458 |
|
|
+ */
|
6459 |
|
|
+// #warning "Need to come back to this."
|
6460 |
122 |
dgisselq |
+#define IFCVT_MACHDEP_INIT(CEINFO) zip_ifcvt_machdep_init(CEINFO)
|
6461 |
102 |
dgisselq |
+
|
6462 |
|
|
+
|
6463 |
|
|
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a
|
6464 |
|
|
+ * target specific pass over the instruction stream. The compiler will run it
|
6465 |
|
|
+ * at all optimization levels, just before the point at which it normally does
|
6466 |
|
|
+ * delayed branch scheduling.
|
6467 |
|
|
+ *
|
6468 |
|
|
+ * You need not implement the hook if it has nothing to do.
|
6469 |
|
|
+ *
|
6470 |
|
|
+ * ZipCPU---This may be part of a later upgrade, but shouldn't be needed to
|
6471 |
|
|
+ * just get us started.
|
6472 |
|
|
+ */
|
6473 |
|
|
+
|
6474 |
|
|
+
|
6475 |
|
|
+/* TARGET_INIT_BUILTINS(VOID) ... Define this hook if you ahve any machine
|
6476 |
|
|
+ * specific builtin functions that need to be defined. It should be a function
|
6477 |
|
|
+ * that performs the necessary setup. Machine specific builtin functions can be
|
6478 |
|
|
+ * useful to expand special machine instructions that would otherwise not
|
6479 |
|
|
+ * normally be generated because they have no equivalent in the source language.
|
6480 |
|
|
+ *
|
6481 |
|
|
+ * To create a built in function, call the function lang_hooks.builtin_function
|
6482 |
|
|
+ * which is defined by the language front end. You can use any type nodes
|
6483 |
|
|
+ * set up by build_common_tree_nodes; only language front ends that use those
|
6484 |
|
|
+ * two functions will call "TARGET_INIT_BUILTINS".
|
6485 |
|
|
+ *
|
6486 |
|
|
+ * ZipCPU---We need to come back to this. We should have several built-ins
|
6487 |
|
|
+ * defined: rtu(), wait(), halt(), save_context(cstackregno), and
|
6488 |
|
|
+ * restore_context(cstackregno).
|
6489 |
|
|
+ *
|
6490 |
|
|
+ */
|
6491 |
|
|
+#undef TARGET_INIT_BUILTINS
|
6492 |
|
|
+#define TARGET_INIT_BUILTINS zip_init_builtins
|
6493 |
|
|
+
|
6494 |
|
|
+/* TARGET_BUILTIN_DECL(CODE,INITP) ... Define this hook if you have any
|
6495 |
|
|
+ * machine specific builtin functions that need to be defined. It should be a
|
6496 |
|
|
+ * function that returns the builtin function declaration for the builtin
|
6497 |
|
|
+ * function code code. If there is no such builtin and it cannot be initialized
|
6498 |
|
|
+ * at this time if INITP is true the function should return NULL_TREE. If
|
6499 |
|
|
+ * CODE is out of range the fucntion should return error-mark_node.
|
6500 |
|
|
+ *
|
6501 |
|
|
+ * ZipCPU ... needs to be done, don't know how to do it yet.
|
6502 |
|
|
+ */
|
6503 |
|
|
+#undef TARGET_BUILTIN_DECL
|
6504 |
|
|
+#define TARGET_BUILTIN_DECL zip_builtin_decl
|
6505 |
|
|
+
|
6506 |
|
|
+
|
6507 |
|
|
+/* TARGET_EXPAND_BUILTIN(TREE,TGT,SUB,MODE,IGNORE) ... Expand a call to a
|
6508 |
|
|
+ * machine specific built-in function that was set up by TARGET_INIT_BUILTINS.
|
6509 |
|
|
+ * TREE is the expression for the function call; the result should go to
|
6510 |
|
|
+ * TGT if that is convenient, and have mode MODE if that is convenient. SUB
|
6511 |
|
|
+ * may be used as the target for computing one of EXP's operands. IGNORE is
|
6512 |
|
|
+ * non-zero if the value is to be ignored. This function should return the
|
6513 |
|
|
+ * result of the call to the built-in function.
|
6514 |
|
|
+ *
|
6515 |
|
|
+ * ZipCPU ... needs to do it, just to get our special intrinsic functions
|
6516 |
|
|
+ */
|
6517 |
|
|
+#define TARGET_EXPAND_BUILTIN zip_expand_builtin
|
6518 |
|
|
+
|
6519 |
|
|
+
|
6520 |
|
|
+/* TARGET_BUILTIN_CHKP_FUNCTION(FCODE) ... Allows the target to redefine
|
6521 |
|
|
+ * builtin functions used by Pointer Bounds Checker for code instrumentation.
|
6522 |
|
|
+ *
|
6523 |
|
|
+ * ZipCPU --- not interested.
|
6524 |
|
|
+ */
|
6525 |
|
|
+/* TARGET_CHKP_BOUND_TYPE
|
6526 |
|
|
+ * TARGET_CHKP_MAKE_BOUNDS_CONSTANT
|
6527 |
|
|
+ * TARGET_CHKP_INITIALIZE_BOUNDS
|
6528 |
|
|
+ *
|
6529 |
|
|
+ * ZipCPU --- Same as last one.
|
6530 |
|
|
+ */
|
6531 |
|
|
+
|
6532 |
|
|
+
|
6533 |
|
|
+/* TARGET_RESOLVE_OVERLOADED_BUILTIN(LOC, FN, ARGS) ... Select a replacement
|
6534 |
|
|
+ * for a machine specific built-in function that was set up by
|
6535 |
|
|
+ * TARGET_INIT_BUILTINS.
|
6536 |
|
|
+ *
|
6537 |
|
|
+ * ZipCPU --- If I go to the trouble to create a builtin, why would I want
|
6538 |
|
|
+ * to then overload it?
|
6539 |
|
|
+ */
|
6540 |
|
|
+
|
6541 |
|
|
+/* TARGET_FOLD_BUILTIN(FN,NARGS,ARGP,IGNORE) ... Fold a call to a machine
|
6542 |
|
|
+ * specific built-in function that was set up by 'TARGET_INIT_BUILTINS' FN
|
6543 |
|
|
+ * is the declaration of the built-in function. NARGS is the number of
|
6544 |
|
|
+ * arguments passed to the function; the arguments themselves are pointed to by
|
6545 |
|
|
+ * ARGP. The result is another tree, valid for both GIMPLE and GENERIC,
|
6546 |
|
|
+ * containing as simplified expression for the call's result. If IGNORE is
|
6547 |
|
|
+ * true the value will be ignored.
|
6548 |
|
|
+ *
|
6549 |
|
|
+ * ZipCPU --- You know, this and the previous couple sound like something
|
6550 |
|
|
+ * whereby I might be able replace bit-reversal code with my bit reverse
|
6551 |
|
|
+ * instruction. That would be very useful, but not necessary to get me
|
6552 |
|
|
+ * started.
|
6553 |
|
|
+ */
|
6554 |
|
|
+
|
6555 |
|
|
+/* TARGET_GIMPLE_FOLD_BUILTIN
|
6556 |
|
|
+ * TARGET_COMPARE_VERSION_PRIORITY
|
6557 |
|
|
+ * TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
|
6558 |
|
|
+ * TARGET_GENERATE_VERSION_DISPATCHER_BODY
|
6559 |
|
|
+ * TARGET_CAN_USE_DOLOOP_P
|
6560 |
|
|
+ * TARGET_INVALID_WITHIN_DOOLOOP
|
6561 |
|
|
+ * TARGET_LEGITIMATE_COMBINED_INSN
|
6562 |
|
|
+ * TARGET_CAN_FOLLOW_JUMP
|
6563 |
|
|
+ * TARGET_COMMUTATIVE_P
|
6564 |
|
|
+ */
|
6565 |
|
|
+
|
6566 |
|
|
+/* TARGET_ALLOCATE_INITIAL_VALUE(REGNO) ... When the initial value of a hard
|
6567 |
|
|
+ * register has been copied in a pseudo register, it is often not necessary
|
6568 |
|
|
+ * ...
|
6569 |
|
|
+ */
|
6570 |
|
|
+/* TARGET_UNSPEC_MAY_TRAP_P(RTX,FLAGS) ... This target hook returns nonzero in
|
6571 |
|
|
+ * RTX, un unspec or unspec_volatile operation, might cause a trap. Targets
|
6572 |
|
|
+ * can use this hook to enhance precision of analysis for unspec and
|
6573 |
|
|
+ * unspec_volatile operations. You may call may_trap_p_1 to analyze inner
|
6574 |
|
|
+ * elements of RTX in which case flags should be passed along.
|
6575 |
|
|
+ */
|
6576 |
|
|
+
|
6577 |
|
|
+/* TARGET_SET_CURRENT_FUNCTION(TREE) The compiler invokes this hook whenever
|
6578 |
|
|
+ * it changes its current function context (CFUN). You can define this
|
6579 |
|
|
+ * function if the back end needs to perform any initialization or reset
|
6580 |
|
|
+ * actions on a per-function basis. For example, it may be used to implement
|
6581 |
|
|
+ * function attributes that affect register usage or code generation patterns.
|
6582 |
|
|
+ */
|
6583 |
|
|
+
|
6584 |
|
|
+/* TARGET_OBJECT_SUFFIX ... Define this macro to be a C string representing the
|
6585 |
|
|
+ * suffix for object files on your target machine. If you do not define this
|
6586 |
|
|
+ * macro, GCC will use ".o" as the suffix for object files.
|
6587 |
|
|
+ */
|
6588 |
|
|
+#define TARGET_OBJECT_SUFFIX ".o"
|
6589 |
|
|
+
|
6590 |
|
|
+/* TARGET_EXECUTABLE_SUFFIX
|
6591 |
|
|
+ */
|
6592 |
|
|
+#define TARGET_EXECUTABLE_SUFFIX ""
|
6593 |
|
|
+
|
6594 |
|
|
+/* COLLECT_EXPORT_LIST ... If defined, collect2 will scan the individual object
|
6595 |
|
|
+ * files specified on its command line and create an export list for the linker.
|
6596 |
|
|
+ * Define this macro for systems like AIX, where the linker discards object
|
6597 |
|
|
+ * files that are not referenced from main and uses export lists.
|
6598 |
|
|
+ *
|
6599 |
|
|
+ * ZipCPU --- shoudln't need this.
|
6600 |
|
|
+ */
|
6601 |
|
|
+
|
6602 |
|
|
+/* MODIFY_JNI_METHOD_CALL(MDECL) ... Define this macro to a C expression
|
6603 |
|
|
+ * representing a variant of the method call mdecl, if Java Native Interface
|
6604 |
|
|
+ * (JNI) methods must be invoked differently from other methods on your
|
6605 |
|
|
+ * target. For example, on 32-bit MSWindows, JNI methods must be invoked
|
6606 |
|
|
+ * using the stdcall calling convention and this macro is then ...
|
6607 |
|
|
+ *
|
6608 |
|
|
+ * ZipCPU----Don't need this. (yet)
|
6609 |
|
|
+ */
|
6610 |
|
|
+
|
6611 |
|
|
+
|
6612 |
|
|
+/* TARGET_CANNOT_MODIFY_JUMPS_P ... This target hook returns true past the
|
6613 |
|
|
+ * point in which a new jump instructions could be created. On machines that
|
6614 |
|
|
+ * require a register for every jump such as the SHmedia ISA of SH5, this point
|
6615 |
|
|
+ * would typically be reload, so thiss target hook should be defined to a
|
6616 |
|
|
+ * function such as:
|
6617 |
|
|
+ *
|
6618 |
117 |
dgisselq |
+ * ZipCPU --- I don't get what this is for.
|
6619 |
|
|
+ * Actually, in hind sight, ZipCPU needs this. Without this, the
|
6620 |
|
|
+ * compiler will try to reorder basic blocks, shuffling logic around and so
|
6621 |
|
|
+ * fortch, preventing our comparison optimizations from being used. By setting
|
6622 |
|
|
+ * this function appropriately, we can prevent it from reversing conditions into
|
6623 |
|
|
+ * conditions we don't support.
|
6624 |
102 |
dgisselq |
+ */
|
6625 |
117 |
dgisselq |
+#define TARGET_CANNOT_MODIFY_JUMPS_P zip_cannot_modify_jumps_p
|
6626 |
102 |
dgisselq |
+
|
6627 |
|
|
+/* TARGET_BRANCH_TARGET_REGISTER_CLASS ... This target hook returns a register
|
6628 |
|
|
+ * class for which branch target register optimizations should be applied. All
|
6629 |
|
|
+ * registers in this class should be usable interchangably. After reload,
|
6630 |
|
|
+ * registers in this class will be re-allocated and loads will be hoisted out of
|
6631 |
|
|
+ * loops and be subjected to inter-block scheduling.
|
6632 |
|
|
+ *
|
6633 |
|
|
+ * ZipCPU---GENERAL_REGS, but this should be a default already ...
|
6634 |
|
|
+ */
|
6635 |
|
|
+
|
6636 |
|
|
+
|
6637 |
|
|
+/* TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED ... Branch target register
|
6638 |
|
|
+ * optimization will by default exclude callee-saved registers that are not
|
6639 |
|
|
+ * already live during the current function. If this target hook returns true,
|
6640 |
|
|
+ * they will be included. The target code must then make sure that all target
|
6641 |
|
|
+ * registers in the class returned by TARGET_BRANCH_REGISTER_CLASS that might
|
6642 |
|
|
+ * be saved are saaved.
|
6643 |
|
|
+ *
|
6644 |
|
|
+ * ZipCPU---
|
6645 |
|
|
+ */
|
6646 |
|
|
+
|
6647 |
|
|
+
|
6648 |
|
|
+/* TARGET_HAVE_CONDITIONAL_EXECUTION(VOID) ... This target hook returns true
|
6649 |
|
|
+ * if the target supports conditional execution. This target hook is required
|
6650 |
|
|
+ * only when the target has several different modes and they have different
|
6651 |
|
|
+ * conditional execution capability, such as ARM.
|
6652 |
|
|
+ *
|
6653 |
|
|
+ * ZipCPU---Yes! All instructions may be conditionally executed (except the
|
6654 |
|
|
+ * long version load immediate ...)
|
6655 |
|
|
+ */
|
6656 |
|
|
+#define TARGET_HAVE_CONDITIONAL_EXECUTION hook_bool_void_true
|
6657 |
|
|
+
|
6658 |
|
|
+/* TARGET_GEN_CCMP_FIRST(PREP,GEN,CODE,OP0,OP1) .. This function prepares to
|
6659 |
|
|
+ * emit a comparison instruction for the first compare in a sequence of
|
6660 |
|
|
+ * conditional comparisons. It returns an appropriate comparison with CC for
|
6661 |
|
|
+ * passing to gen_ccmp_next or cbranch_optab. The instructions to prepare the
|
6662 |
|
|
+ * compare are saved in prep_seq and the compare instructions are saved in
|
6663 |
|
|
+ * gen_seq. They will be emitted when all the compares in the conditional
|
6664 |
|
|
+ * comparison are generated without error. CODE is the rtx_code of the compare
|
6665 |
|
|
+ * for op0 and op1.
|
6666 |
|
|
+ *
|
6667 |
|
|
+ *
|
6668 |
|
|
+ * ZipCPU---???
|
6669 |
|
|
+ */
|
6670 |
|
|
+
|
6671 |
|
|
+/* TARGET_GEN_CCMP_NEXT(PREP,GEN,PREV,CMP,OP0,OP1,BITCODE) ... This function
|
6672 |
|
|
+ * prepares to emit a conditional comparison within a sequence of conditional
|
6673 |
|
|
+ * comparisons. It returns an appropriate comparison with CC for passing to
|
6674 |
|
|
+ * gen_ccmp_next or cbranch_optab. The insn to prepare the compare are saved
|
6675 |
|
|
+ * in prep_seq and the compare instructions are saved in gen_seq. They will be
|
6676 |
|
|
+ * emitted when all the compares in the conditional comparison are generated
|
6677 |
|
|
+ * without error. The pPREV expression is the result of a prior call to either
|
6678 |
|
|
+ * gen_ccmp_first or gen_ccmp_next. It may return NULL if the combination of
|
6679 |
|
|
+ * PREV and this comparison is not supported, otherwise the result must be the
|
6680 |
|
|
+ * appropriate for passing to gen_ccmp_next or cbranch_optab. CODE is the RTX
|
6681 |
|
|
+ * code of the compare for op0 and op1. BITCODE is AND or IOR, which is the op
|
6682 |
|
|
+ * on the compares.
|
6683 |
|
|
+ *
|
6684 |
|
|
+ *
|
6685 |
|
|
+ * ZipCPU --- ???
|
6686 |
|
|
+ */
|
6687 |
|
|
+
|
6688 |
|
|
+/* TARGET_LOOP_UNROLL_ADJUST(NUNROLL, LOOP) ... This target hook returns a new
|
6689 |
|
|
+ * value for the number of times loop should be unrolled. The parameter NUNROLL
|
6690 |
|
|
+ * is the number of times the loop is to be unrolled. The parameter loop is a
|
6691 |
|
|
+ * pointer to the loop, which is going to be checked for unrolling. The target
|
6692 |
|
|
+ * hook is required only when the target has special constraints like maximum number of memory accesses.
|
6693 |
|
|
+ *
|
6694 |
|
|
+ *
|
6695 |
|
|
+ * ZipCPU -- ???
|
6696 |
|
|
+ */
|
6697 |
|
|
+
|
6698 |
|
|
+
|
6699 |
|
|
+/* POWI_MAX_MULTS ... If defined, this macro is interpreted as a signed integer
|
6700 |
|
|
+ * C expression that specifies the maximum number of floating point
|
6701 |
|
|
+ * multiplications that should be emitted when expanding exponentiation by an
|
6702 |
|
|
+ * integer constant inline. When this value is defined, exponentiation
|
6703 |
|
|
+ * requiring more than this number of multiplications is implemented by calling
|
6704 |
|
|
+ * the system library's pow, powf, or powl routines. The default value
|
6705 |
|
|
+ places no upper bound on the multiplication count.
|
6706 |
|
|
+ *
|
6707 |
|
|
+ * ZipCPU---As we have no system library pow() routine (yet) ... we're not
|
6708 |
|
|
+ * ready for this macro.
|
6709 |
|
|
+ */
|
6710 |
|
|
+
|
6711 |
|
|
+
|
6712 |
|
|
+/* TARGET_EXTRA_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
|
6713 |
|
|
+ * register any extra include files for the target. The parameter stdinc
|
6714 |
|
|
+ * indicates if normal include files are present. The parameter SYSROOT is the
|
6715 |
|
|
+ * system root directory. The parameter PFX is the prefix for the GCC
|
6716 |
|
|
+ * directoiry.
|
6717 |
|
|
+ *
|
6718 |
|
|
+ *
|
6719 |
|
|
+ * ZipCPU---None yet.
|
6720 |
|
|
+ */
|
6721 |
|
|
+
|
6722 |
|
|
+/* TARGET_EXTRA_PRE_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
|
6723 |
|
|
+ * register any extrra include files for the target before any standard headers.
|
6724 |
|
|
+ * The parameter stdinc indicates if normal include files are present.
|
6725 |
|
|
+ *
|
6726 |
|
|
+ * ZipCPU --- None.
|
6727 |
|
|
+ */
|
6728 |
|
|
+
|
6729 |
|
|
+/* TARGET_OPTF(PATH) ... This target hook should register special include paths
|
6730 |
|
|
+ * for the target. The parameter path is the integer to register. On Darwin
|
6731 |
|
|
+ * systems, this is used for Framework includes, which have semantics that are
|
6732 |
|
|
+ * different from -I.
|
6733 |
|
|
+ *
|
6734 |
|
|
+ *
|
6735 |
|
|
+ * ZipCPU --- None.
|
6736 |
|
|
+ */
|
6737 |
|
|
+
|
6738 |
|
|
+/* TARGET_USE_LOCAL_THUNK_ALIAS_P(FN) ... This target macro returns if it is
|
6739 |
|
|
+ * safe to use a local alias for a virtual function FN when constructing
|
6740 |
|
|
+ * thunks, false otherwise. By default, the macro returns true for all
|
6741 |
|
|
+ * functions, if a target supports aliases (i.e. defines ASM_OUTPUT_DEF),
|
6742 |
|
|
+ * false otherwise.
|
6743 |
|
|
+ *
|
6744 |
|
|
+ *
|
6745 |
|
|
+ * ZipCPU --- ???
|
6746 |
|
|
+ */
|
6747 |
|
|
+// #warning "ASM_OUTPUT_DEF's definition has not been considered"
|
6748 |
|
|
+
|
6749 |
|
|
+
|
6750 |
|
|
+/* TARGET_FORMAT_TYPES ... If defined, this macro is the name of a global
|
6751 |
|
|
+ * variable containing target-specific format checking information for the
|
6752 |
|
|
+ * -Wformat option. The default is to have no target-specific format checks.
|
6753 |
|
|
+ *
|
6754 |
|
|
+ * ZipCPU --- Default
|
6755 |
|
|
+ */
|
6756 |
|
|
+
|
6757 |
|
|
+/* TARGET_N_FORMAT_TYPES
|
6758 |
|
|
+ *
|
6759 |
|
|
+ * ZipCPU --- Default
|
6760 |
|
|
+ */
|
6761 |
|
|
+
|
6762 |
|
|
+/* TARGET_OVERRIDES_FORMAT_ATTRIBUTES ... If defined, this macro is the name of
|
6763 |
|
|
+ * a global variable containing target-specific format overrides for the
|
6764 |
|
|
+ * -Wformat option. The default is to have no target specific format overrides.
|
6765 |
|
|
+ *
|
6766 |
|
|
+ * ZipCPU --- Default
|
6767 |
|
|
+ */
|
6768 |
|
|
+
|
6769 |
|
|
+/* TARGET_OVERRIDEES_FORMAT_ATTRIBUTES
|
6770 |
|
|
+ * TARGET_OVERRIDEES_FORMAT_ATTRIBUTES_COUNT
|
6771 |
|
|
+ *
|
6772 |
|
|
+ * If defined, the (first) macro is the name of a global variable containing
|
6773 |
|
|
+ * target-specific format overrides for the -Wformat option.
|
6774 |
|
|
+ */
|
6775 |
|
|
+/* TARGET_OVERRIDES_FORMAT_INIT ... If defined, this macro specifies the
|
6776 |
|
|
+ * optional initialization routine for target specific customizations of the
|
6777 |
|
|
+* system printf and scanf formatter settings.
|
6778 |
|
|
+ */
|
6779 |
|
|
+
|
6780 |
|
|
+/* TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN(TLIST,FN,VAL) ... If defined, this
|
6781 |
|
|
+ * macro returns the diagnostic message when it is illegal to pass an argument
|
6782 |
|
|
+ * VAL to function FN with prototype TLIST.
|
6783 |
|
|
+ *
|
6784 |
|
|
+ * ZipCPU---Default.
|
6785 |
|
|
+ */
|
6786 |
|
|
+
|
6787 |
|
|
+/* TARGET_INVALID_CONVERSION
|
6788 |
|
|
+ * TARGET_INVALID_UNARY_OP
|
6789 |
|
|
+ * TARGET_INVALID_BINARY_OP
|
6790 |
|
|
+ * TARGET_INVALID_PARAMETER_TYPE
|
6791 |
|
|
+ * TARGET_INVALID_RETURN_TYPE
|
6792 |
|
|
+ * TARGET_PROMOTED_TYPE
|
6793 |
|
|
+ * TARGET_CONVERT_TO_TYPE
|
6794 |
|
|
+ * TARGET_USE_JCR_SECTION_TYPE
|
6795 |
|
|
+ * OBJC_JBLEN
|
6796 |
|
|
+ * LIBGCC2_UNWIND_ATTRIBUTE
|
6797 |
|
|
+ * TARGET_UPDATE_STACK_BOUNDARY
|
6798 |
|
|
+ * TARGET_GET_DRAP_RTX
|
6799 |
|
|
+ * TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
|
6800 |
|
|
+ */
|
6801 |
|
|
+/* TARGET_CONST_ANCHOR ... On some architectures it can take multiple
|
6802 |
|
|
+ * instructions to synthesize a constant. If there is another constant already
|
6803 |
|
|
+ * in a register that is close enough in value then it is preferable that the
|
6804 |
|
|
+ * new constant is computed from the register using immediate addition or
|
6805 |
|
|
+ * subtraction. We accomplish this through CSE. Besides the value of the
|
6806 |
|
|
+ * constant we also add a lower and an upper constant anchor to the available
|
6807 |
|
|
+ * expressions. These are then queried when encountering new constants. The
|
6808 |
|
|
+ * anchors are computed by rounding the constant up and down to a multiple of
|
6809 |
|
|
+ * the value of TARGET_CONST_ANCHOR. TARGET_CONST_ANCHOR should be the maximum
|
6810 |
|
|
+ * positive value accepted by immediate-add plus one. We currently assume that
|
6811 |
|
|
+ * the value of TARGET_CONST_ANCHOR is a poewr of 2. For example, on MIPS,
|
6812 |
|
|
+ * where add-immediate takes a 16-bit signed value, TARGET_CONST_ANCHOR is set
|
6813 |
|
|
+ * to 0x8000. The default value is zero, which disables this optimization.
|
6814 |
|
|
+ *
|
6815 |
|
|
+ * ZipCPU---One of the great strengths of the ZipCPU ISA is its ability to
|
6816 |
|
|
+ * access registers plus immediates. To use this, we *need* this capability.
|
6817 |
|
|
+ * So, we define it here. (to 0x20000, or 2^17 because we can handle 18-bits of
|
6818 |
|
|
+ * signed immediate offsets)
|
6819 |
|
|
+ *
|
6820 |
|
|
+ * On ZipCPU---2^17
|
6821 |
|
|
+ */
|
6822 |
|
|
+#define TARGET_CONST_ANCHOR zip_const_anchor
|
6823 |
|
|
+
|
6824 |
|
|
+/* TARGET_ASAN_SHADOW_OFFSET ... Return the offset bitwise ored into shifted
|
6825 |
|
|
+ * address to get corresponding Address Sanitizer shadow memory address. NULL
|
6826 |
|
|
+ * if address Sanitizer is not supported by the target.
|
6827 |
|
|
+ */
|
6828 |
|
|
+#define TARGET_ASAN_SHADOW_OFFSET NULL
|
6829 |
|
|
+
|
6830 |
|
|
+/* TARGET_MEMMODEL_CHECK
|
6831 |
|
|
+ */
|
6832 |
|
|
+/* TARGET_ATOMIC_TEST_AND_SET_TRUEVAL ... This value should be set if the result
|
6833 |
|
|
+ * written by atomic test and set is not exactly 1, i.e. the bool true.
|
6834 |
|
|
+ */
|
6835 |
|
|
+/* TARGET_HAS_IFUNC_P ... It returns true if the target supports GNU indirect
|
6836 |
|
|
+ * functions. The support includes the assembler, linker, and dynamic linker.
|
6837 |
|
|
+ * The default value of this hook is based on target's libc.
|
6838 |
|
|
+ */
|
6839 |
|
|
+#define TARGET_HAS_IFUNC_P hook_bool_void_true
|
6840 |
|
|
+
|
6841 |
|
|
+/* TARGET_ATOMIC_ALIGN_FOR_MODE(MODE) ... If defined, this function returns
|
6842 |
|
|
+ * an appropriate alignment in bits for an atomic object of machine mode
|
6843 |
|
|
+ * MODE. If 0 is returned then the default alignment for the specified mode
|
6844 |
|
|
+ * is used.
|
6845 |
|
|
+ *
|
6846 |
|
|
+ * ZipCPU---Both default and 2 would be valid. We'll stick to the default.
|
6847 |
|
|
+ */
|
6848 |
|
|
+
|
6849 |
|
|
+/* TARGET_ATOMIC_ASSIGN_EXPAND_FENV --- ISO C11 requires atomic compound
|
6850 |
|
|
+ * assignments that may raise floating-point exceptions to raise exceptions
|
6851 |
|
|
+ * corresponding to the arithmetic operation whose result was successfully
|
6852 |
|
|
+ * stored in a compare-and-exchange sequence. This requires code equivalent to
|
6853 |
|
|
+ * calls to feholdexcept, feclearexcept and feupdateenv to be generated at
|
6854 |
|
|
+ * appropriate points in the compare-and-exchange sequence. This hook should
|
6855 |
|
|
+ * set *hold to an expression equivalent
|
6856 |
|
|
+ *
|
6857 |
|
|
+ * ZipCPU --- ???
|
6858 |
|
|
+ */
|
6859 |
|
|
+
|
6860 |
|
|
+/* TARGET_RECORD_OFFLOAD_SYMBOL ... Used when offloaded functions are seen in
|
6861 |
|
|
+ * the compilation unit and no named sections are available. It is called once
|
6862 |
|
|
+ * for each symbol that must be recorded in the offload function and variable
|
6863 |
|
|
+ * table.
|
6864 |
|
|
+ *
|
6865 |
|
|
+ * ZipCPU --- Offloaded functions?
|
6866 |
|
|
+ */
|
6867 |
|
|
+
|
6868 |
|
|
+/* TARGET_OFFLOAD_OPTIONS
|
6869 |
|
|
+ *
|
6870 |
|
|
+ * ZipCPU---none defined
|
6871 |
|
|
+ */
|
6872 |
|
|
+
|
6873 |
|
|
+/* TARGET_SUPPORTS_WIDE_INT ... On older ports, large integers are stored
|
6874 |
|
|
+ * in CONST_DOUBLE rtl objects. Newer ports define TARGET_SUPPORTS_WIDE_INT
|
6875 |
|
|
+ * to be nonzero to indicate that large integers are stored in CONST_WIDE_INT
|
6876 |
|
|
+ * rtl objects. The CONST_WIDE_INT allows very large integer constants to be
|
6877 |
|
|
+ * represented. CONST_DOUBLE is limited to twice the size of the hosts
|
6878 |
|
|
+ * HOST_WIDE_INT representation.
|
6879 |
|
|
+ *
|
6880 |
|
|
+ * ZipCPU---We don't need these yet, so this isn't yet relevant. (These ints
|
6881 |
|
|
+ * are wider than DImode ...)
|
6882 |
|
|
+ */
|
6883 |
|
|
+#define TARGET_SUPPORTS_WIDE_INT 0
|
6884 |
|
|
+
|
6885 |
|
|
+
|
6886 |
|
|
+/* Now, for the prototype functions ...*/
|
6887 |
|
|
+// These have been moved to zip-protos.h
|
6888 |
|
|
+
|
6889 |
|
|
+// extern void zip_init_builtins(void);
|
6890 |
|
|
+// extern void zip_asm_output_anchor(rtx x);
|
6891 |
|
|
+// extern bool zip_legitimate_address_p(enum machine_mode mode, rtx x, bool string);
|
6892 |
|
|
+// extern void zip_asm_trampoline_template(FILE *);
|
6893 |
|
|
+// extern void zip_initial_elimination_offset(int from, int to);
|
6894 |
|
|
+// extern void zip_print_operand(FILE *stream, rtx *x, int code);
|
6895 |
|
|
+// extern void zip_print_operand_address(FILE *stream, rtx *x);
|
6896 |
|
|
+// extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
|
6897 |
|
|
+// extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
|
6898 |
|
|
+// extern int zip_address_operand(rtx op);
|
6899 |
|
|
+// extern int zip_const_address_operand(rtx op);
|
6900 |
|
|
+// extern void zip_expand_prologue(void);
|
6901 |
|
|
+// extern void zip_expand_epilogue(void);
|
6902 |
|
|
+// extern bool zip_gen_move_rtl(rtx, rtx);
|
6903 |
|
|
+// extern bool zip_load_address_lod(rtx, rtx);
|
6904 |
|
|
+// extern bool zip_load_address_sto(rtx, rtx);
|
6905 |
|
|
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
|
6906 |
|
|
+// extern void zip_print_operand_address(FILE *fp, rtx x);
|
6907 |
|
|
+// extern bool zip_use_return_insn(void);
|
6908 |
|
|
+
|
6909 |
111 |
dgisselq |
+#define UQQmode USQmode
|
6910 |
|
|
+#define UHQmode USQmode
|
6911 |
|
|
+#define UHAmode USAmode
|
6912 |
|
|
+#define QQmode SQmode
|
6913 |
|
|
+#define HQmode SQmode
|
6914 |
102 |
dgisselq |
+#define QImode SImode
|
6915 |
|
|
+#define HImode SImode
|
6916 |
111 |
dgisselq |
+#define QAmode SAmode
|
6917 |
|
|
+#define HAmode SAmode
|
6918 |
102 |
dgisselq |
+
|
6919 |
|
|
+#include "insn-modes.h"
|
6920 |
|
|
+#include "zip-protos.h"
|
6921 |
|
|
+
|
6922 |
|
|
+#endif /* GCC_ZIP_H */
|
6923 |
|
|
+
|
6924 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
|
6925 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip.md 1969-12-31 19:00:00.000000000 -0500
|
6926 |
171 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-08-08 07:07:39.251163261 -0400
|
6927 |
|
|
@@ -0,0 +1,3254 @@
|
6928 |
102 |
dgisselq |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
6929 |
|
|
+;;
|
6930 |
|
|
+;; Filename: zip.md
|
6931 |
|
|
+;;
|
6932 |
|
|
+;; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
|
6933 |
|
|
+;;
|
6934 |
|
|
+;; Purpose: This is the machine description of the Zip CPU as needed by the
|
6935 |
|
|
+;; GNU compiler collection (GCC).
|
6936 |
|
|
+;;
|
6937 |
|
|
+;;
|
6938 |
|
|
+;; Creator: Dan Gisselquist, Ph.D.
|
6939 |
|
|
+;; Gisselquist Technology, LLC
|
6940 |
|
|
+;;
|
6941 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
6942 |
|
|
+;;
|
6943 |
|
|
+;; Copyright (C) 2015, Gisselquist Technology, LLC
|
6944 |
|
|
+;;
|
6945 |
|
|
+;; This program is free software (firmware): you can redistribute it and/or
|
6946 |
|
|
+;; modify it under the terms of the GNU General Public License as published
|
6947 |
|
|
+;; by the Free Software Foundation, either version 3 of the License, or (at
|
6948 |
|
|
+;; your option) any later version.
|
6949 |
|
|
+;;
|
6950 |
|
|
+;; This program is distributed in the hope that it will be useful, but WITHOUT
|
6951 |
|
|
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
6952 |
|
|
+;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
6953 |
|
|
+;; for more details.
|
6954 |
|
|
+;;
|
6955 |
|
|
+;; License: GPL, v3, as defined and found on www.gnu.org,
|
6956 |
|
|
+;; http://www.gnu.org/licenses/gpl.html
|
6957 |
|
|
+;;
|
6958 |
|
|
+;;
|
6959 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
6960 |
|
|
+;;
|
6961 |
|
|
+;;
|
6962 |
|
|
+;; - Immediate integer operand constraints
|
6963 |
|
|
+;; 'I' -2^22 ... 2^22-1, or -4194304 .. 4194303 (LDI insn)
|
6964 |
|
|
+;; 'M' -2^12 ... 2^12-1, or -4096 ... 4095 (MOV offset)
|
6965 |
|
|
+;; 'N' -2^14 ... 2^14-1, or -16384 ... 16383 (OpB offset)
|
6966 |
|
|
+;; 'O' -2^17 ... 2^17-1, or -131072 ... 131071 (OpB Immediate)
|
6967 |
|
|
+;; 'R' 0...31 (Shift value)
|
6968 |
|
|
+;; - Memory constraints
|
6969 |
111 |
dgisselq |
+;; "Q" Op-B capable references to memory
|
6970 |
|
|
+;; "S" References to constant memory
|
6971 |
102 |
dgisselq |
+;; - Address constraints
|
6972 |
111 |
dgisselq |
+;; "U" Op-B capable address that references to memory
|
6973 |
|
|
+;; "T" Constant memory addresses
|
6974 |
102 |
dgisselq |
+(define_constraint "M"
|
6975 |
|
|
+ "An 13-bit signed immediate such as a MOV instruction can handle"
|
6976 |
|
|
+ (and (match_code "const_int")
|
6977 |
|
|
+ (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
|
6978 |
|
|
+(define_constraint "N"
|
6979 |
|
|
+ "An 14-bit signed immediate offset such as an Op-B register offset"
|
6980 |
|
|
+ (and (match_code "const_int")
|
6981 |
|
|
+ (match_test "(ival < 0x2000) && (ival >= -0x2000)")))
|
6982 |
|
|
+(define_constraint "O"
|
6983 |
|
|
+ "An 18-bit signed immediate such as an Op-B Immediate can handle"
|
6984 |
|
|
+ (and (match_code "const_int")
|
6985 |
|
|
+ (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
|
6986 |
|
|
+(define_constraint "R"
|
6987 |
|
|
+ "Bits that a value may be shifted"
|
6988 |
|
|
+ (and (match_code "const_int")
|
6989 |
|
|
+ (match_test "(ival < 32) && (ival >= 0)")))
|
6990 |
|
|
+;;
|
6991 |
|
|
+;
|
6992 |
|
|
+;
|
6993 |
|
|
+; Our builtin functions, by identifier
|
6994 |
|
|
+;
|
6995 |
|
|
+(define_constants
|
6996 |
117 |
dgisselq |
+ [(UNSPEC_RTU 1)
|
6997 |
|
|
+ (UNSPEC_HALT 2)
|
6998 |
|
|
+ (UNSPEC_IDLE 3)
|
6999 |
|
|
+ (UNSPEC_SYSCALL 4)
|
7000 |
|
|
+ (UNSPEC_SAVE_CONTEXT 5)
|
7001 |
|
|
+ (UNSPEC_RESTORE_CONTEXT 6)
|
7002 |
|
|
+ (UNSPEC_BITREV 7)
|
7003 |
|
|
+ (UNSPEC_GETUCC 8)
|
7004 |
|
|
+ (UNSPEC_GETCC 9)
|
7005 |
|
|
+ (UNSPEC_LDILO 10)
|
7006 |
127 |
dgisselq |
+ ; (UNSPEC_RAW_CALL 11)
|
7007 |
102 |
dgisselq |
+ ])
|
7008 |
|
|
+;
|
7009 |
|
|
+;
|
7010 |
|
|
+; Registers by name
|
7011 |
|
|
+(define_constants
|
7012 |
|
|
+ [(RTN_REG 0) ; Return address register
|
7013 |
|
|
+ (RTNV_REG 1) ; Subroutine return value register
|
7014 |
|
|
+ (AP_REG 10) ; Hopefully never used
|
7015 |
|
|
+ (GBL_REG 11) ; Hopefully never used, but just in case ...
|
7016 |
|
|
+ (FP_REG 12)
|
7017 |
|
|
+ (SP_REG 13)
|
7018 |
|
|
+ (CC_REG 14)
|
7019 |
|
|
+ (PC_REG 15)
|
7020 |
|
|
+ ])
|
7021 |
|
|
+;
|
7022 |
|
|
+;
|
7023 |
|
|
+;
|
7024 |
|
|
+
|
7025 |
|
|
+;; Predicates
|
7026 |
|
|
+(define_predicate "zip_const_address_operand_p"
|
7027 |
|
|
+ (match_code "symbol_ref,const,label_ref,code_label")
|
7028 |
|
|
+{
|
7029 |
|
|
+ return zip_const_address_operand(op);
|
7030 |
|
|
+})
|
7031 |
|
|
+
|
7032 |
|
|
+(define_predicate "zip_address_operand_p"
|
7033 |
|
|
+ (match_code "reg,plus")
|
7034 |
|
|
+{
|
7035 |
111 |
dgisselq |
+ return zip_pd_opb_operand(op);
|
7036 |
102 |
dgisselq |
+})
|
7037 |
|
|
+
|
7038 |
111 |
dgisselq |
+(define_predicate "zip_opb_operand_p"
|
7039 |
122 |
dgisselq |
+ (match_code "reg,plus,const_int,subreg")
|
7040 |
111 |
dgisselq |
+{
|
7041 |
|
|
+ return zip_pd_opb_operand(op);
|
7042 |
|
|
+})
|
7043 |
|
|
+
|
7044 |
122 |
dgisselq |
+(define_predicate "zip_opb_immv_p"
|
7045 |
|
|
+ (match_code "const_int")
|
7046 |
|
|
+{
|
7047 |
|
|
+ return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
|
7048 |
|
|
+})
|
7049 |
|
|
+
|
7050 |
111 |
dgisselq |
+(define_predicate "zip_opb_single_operand_p"
|
7051 |
122 |
dgisselq |
+ (match_code "reg,subreg,const_int")
|
7052 |
111 |
dgisselq |
+{
|
7053 |
|
|
+ return zip_pd_opb_operand(op);
|
7054 |
|
|
+})
|
7055 |
|
|
+
|
7056 |
102 |
dgisselq |
+(define_predicate "zip_mov_operand_p"
|
7057 |
|
|
+ (match_code "reg,plus")
|
7058 |
|
|
+{
|
7059 |
|
|
+ return zip_pd_mov_operand(op);
|
7060 |
|
|
+})
|
7061 |
|
|
+
|
7062 |
|
|
+(define_predicate "zip_memory_operand_p"
|
7063 |
|
|
+ (match_code "mem")
|
7064 |
|
|
+{
|
7065 |
111 |
dgisselq |
+ return zip_pd_opb_operand(XEXP(op,0));
|
7066 |
102 |
dgisselq |
+})
|
7067 |
|
|
+
|
7068 |
111 |
dgisselq |
+(define_predicate "zip_imm_operand_p"
|
7069 |
|
|
+ (match_code "const_int")
|
7070 |
|
|
+{
|
7071 |
|
|
+ return zip_pd_imm_operand(op);
|
7072 |
|
|
+})
|
7073 |
|
|
+
|
7074 |
|
|
+(define_predicate "zip_mvimm_operand_p"
|
7075 |
|
|
+ (match_code "const_int")
|
7076 |
|
|
+{
|
7077 |
|
|
+ return zip_pd_mvimm_operand(op);
|
7078 |
|
|
+})
|
7079 |
|
|
+
|
7080 |
|
|
+(define_predicate "zip_movdst_operand_p"
|
7081 |
|
|
+ (match_code "mem,reg,subreg")
|
7082 |
|
|
+{
|
7083 |
|
|
+ if (MEM_P(op)) // Check for valid store address
|
7084 |
|
|
+ return zip_pd_opb_operand(XEXP(op,0));
|
7085 |
122 |
dgisselq |
+ else if (SUBREG_P(op))
|
7086 |
|
|
+ return 1;
|
7087 |
|
|
+ else if ((REG_P(op))||(SUBREG_P(op)))
|
7088 |
|
|
+ return register_operand(op, GET_MODE(op));
|
7089 |
111 |
dgisselq |
+ return 1;
|
7090 |
|
|
+})
|
7091 |
|
|
+
|
7092 |
|
|
+(define_predicate "zip_movsrc_operand_p"
|
7093 |
|
|
+ (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
|
7094 |
|
|
+{
|
7095 |
|
|
+ if (MEM_P(op))
|
7096 |
|
|
+ return zip_pd_opb_operand(XEXP(op,0));
|
7097 |
|
|
+ else if (GET_CODE(op)==PLUS)
|
7098 |
|
|
+ return zip_pd_opb_operand(op);
|
7099 |
122 |
dgisselq |
+ else if (SUBREG_P(op)) {
|
7100 |
|
|
+ //; As far as predicates are concerned, subregs must be valid.
|
7101 |
|
|
+ //; The details of them are settled within the constraints.
|
7102 |
|
|
+ return 1;
|
7103 |
|
|
+ } else if ((REG_P(op))||(SUBREG_P(op)))
|
7104 |
|
|
+ return register_operand(op,SImode);
|
7105 |
|
|
+ else if (CONST_INT_P(op))
|
7106 |
|
|
+ return 1;
|
7107 |
111 |
dgisselq |
+ return 1;
|
7108 |
|
|
+})
|
7109 |
|
|
+
|
7110 |
102 |
dgisselq |
+;; Constraints
|
7111 |
|
|
+;
|
7112 |
|
|
+(define_memory_constraint "S"
|
7113 |
|
|
+ "Any memory referenced by a constant address, possibly unknown at compile time"
|
7114 |
|
|
+ (and (match_code "mem")
|
7115 |
|
|
+ (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
|
7116 |
|
|
+(define_memory_constraint "Q"
|
7117 |
|
|
+ "Any memory addressed suitably for a load or store instruction"
|
7118 |
|
|
+ (and (match_code "mem")
|
7119 |
|
|
+ (match_test "zip_ct_address_operand(XEXP(op,0))")))
|
7120 |
|
|
+(define_address_constraint "U"
|
7121 |
|
|
+ "An address suitable for a load or store instruction"
|
7122 |
|
|
+ (and (match_code "reg,plus")
|
7123 |
|
|
+ (match_test "zip_ct_address_operand(op)")))
|
7124 |
|
|
+(define_address_constraint "T"
|
7125 |
|
|
+ "Any constant address, to include those made by symbols unknown at compile time"
|
7126 |
|
|
+ (and (match_code "label_ref,code_label,symbol_ref,const")
|
7127 |
|
|
+ (match_test "zip_ct_const_address_operand(op)")))
|
7128 |
|
|
+;
|
7129 |
|
|
+;
|
7130 |
|
|
+;; Attributes
|
7131 |
|
|
+;
|
7132 |
|
|
+(define_attr "predicable" "no,yes" (const_string "yes"))
|
7133 |
|
|
+(define_attr "conditional" "no,yes" (const_string "no"))
|
7134 |
|
|
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
|
7135 |
|
|
+;
|
7136 |
|
|
+; Mode attributes
|
7137 |
|
|
+; (define_mode_iterator ZI [QI HI SI])
|
7138 |
|
|
+; (define_mode_attr zipa [(QI "") (HI "") (SI "")])
|
7139 |
|
|
+(define_mode_iterator ZI [SI])
|
7140 |
|
|
+(define_mode_attr zipa [(SI "")])
|
7141 |
|
|
+;
|
7142 |
|
|
+;
|
7143 |
|
|
+;
|
7144 |
|
|
+;; Instructions
|
7145 |
|
|
+;
|
7146 |
|
|
+; (define_insn
|
7147 |
|
|
+; optional name
|
7148 |
|
|
+; RTL template -- a vector of incomplete RTL expressions describing the
|
7149 |
|
|
+; semantics of the instruction. It is incomplete because it may
|
7150 |
|
|
+; contain match_operand, match_operator, and match_dup expressions
|
7151 |
|
|
+; The condition --- contains a C expression, may be an empty string
|
7152 |
|
|
+; output template or output statement--fragment of C code returning a str
|
7153 |
|
|
+; Attributes --
|
7154 |
|
|
+; )
|
7155 |
|
|
+;
|
7156 |
|
|
+; (match_operand:m n predicate constraint)
|
7157 |
|
|
+; Placeholder for operand #n of the instruction
|
7158 |
|
|
+; Predicate string that is the name of a fucntion w/ 2 arguments:
|
7159 |
|
|
+; (expression, machine mode)
|
7160 |
|
|
+; we can build functions:
|
7161 |
|
|
+; "isregister" to describe a register
|
7162 |
|
|
+; "isimmediate" to describe an immediate
|
7163 |
|
|
+; "offsetreg" to describe a register plus offset
|
7164 |
|
|
+; "anyregister" to describe *ANY* register (uRx or Rx)
|
7165 |
|
|
+; But ... functions "address_operand", "immediate_operand",
|
7166 |
|
|
+; "register_operand", "indirect_operand"
|
7167 |
|
|
+; "comparison_operatot" and "ordered_comparison_operator"
|
7168 |
|
|
+; are also available--be aware, they include more comparisons
|
7169 |
|
|
+; than Zip CPU can do.
|
7170 |
|
|
+;
|
7171 |
|
|
+;
|
7172 |
|
|
+;
|
7173 |
|
|
+;
|
7174 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7175 |
|
|
+;;
|
7176 |
|
|
+;; Move instructions: both
|
7177 |
|
|
+; (arbitrary) from variables to variables, but this gets
|
7178 |
|
|
+; expanded into:
|
7179 |
|
|
+; from registers to registers
|
7180 |
|
|
+; from immediates to registers
|
7181 |
|
|
+;;
|
7182 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7183 |
|
|
+;
|
7184 |
|
|
+;
|
7185 |
|
|
+;
|
7186 |
|
|
+(define_expand "mov<mode>"
|
7187 |
111 |
dgisselq |
+ [(set (match_operand:ZI 0 "nonimmediate_operand" "")
|
7188 |
|
|
+ (match_operand:ZI 1 "general_operand" ""))]
|
7189 |
102 |
dgisselq |
+ ""
|
7190 |
111 |
dgisselq |
+ {//; Everything except mem=const or mem=mem can be done easily
|
7191 |
|
|
+ //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
7192 |
|
|
+ //; fprintf(stderr, "ZIP-GEN-MOVE\n");
|
7193 |
|
|
+ //; zip_debug_rtx_pfx("FROM: ", operands[1]);
|
7194 |
|
|
+ //; zip_debug_rtx_pfx("TO : ", operands[0]);
|
7195 |
|
|
+
|
7196 |
|
|
+ //; Need to load into a register between memory slots
|
7197 |
|
|
+ if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
|
7198 |
|
|
+ //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
|
7199 |
|
|
+ if (can_create_pseudo_p()) {
|
7200 |
|
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
|
7201 |
|
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
7202 |
|
|
+ operands[1] = tmp;
|
7203 |
|
|
+ }
|
7204 |
102 |
dgisselq |
+ }
|
7205 |
111 |
dgisselq |
+
|
7206 |
|
|
+ //; Op[0] has a bad address, need to legitimize it
|
7207 |
|
|
+ if ((MEM_P(operands[0]))&&
|
7208 |
|
|
+ ((zip_const_address_operand(XEXP(operands[0],0)))
|
7209 |
|
|
+ ||(!zip_pd_opb_operand(XEXP(operands[0],0))))
|
7210 |
|
|
+ )
|
7211 |
|
|
+ {
|
7212 |
|
|
+ //; fprintf(stderr, "GEN-MOVSI: Not to a MEM(REG)\n");
|
7213 |
|
|
+ if (can_create_pseudo_p()) {
|
7214 |
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
7215 |
|
|
+ //; Load the address into a register
|
7216 |
|
|
+ emit_insn(gen_movsi(tmp,XEXP(operands[0],0)));
|
7217 |
|
|
+ XEXP(operands[0],0) = tmp;
|
7218 |
|
|
+ mark_reg_pointer(tmp,1);
|
7219 |
|
|
+ }
|
7220 |
|
|
+ }
|
7221 |
|
|
+ //; Op[1] is a constant. Need to load into a register before we can
|
7222 |
|
|
+ //; place it into memory.
|
7223 |
|
|
+ if ((MEM_P(operands[0]))&&
|
7224 |
|
|
+ ((CONSTANT_P(operands[1]))
|
7225 |
|
|
+ ||(CONST_INT_P(operands[1])))) {
|
7226 |
|
|
+ //; fprintf(stderr, "GEN-MOVSI: CONST -> MEM\n");
|
7227 |
|
|
+ //; zip_debug_rtx_pfx("MEM : ", operands[0]);
|
7228 |
|
|
+ //; zip_debug_rtx_pfx("CONST: ", operands[1]);
|
7229 |
|
|
+ if (can_create_pseudo_p()) {
|
7230 |
|
|
+ rtx tmp = gen_reg_rtx(GET_MODE(operands[0]));
|
7231 |
|
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
7232 |
|
|
+ operands[1] = tmp;
|
7233 |
|
|
+ }
|
7234 |
|
|
+ }
|
7235 |
|
|
+ //; Op[1] has a bad address, need to legitimize it
|
7236 |
|
|
+ if ((MEM_P(operands[1]))&&
|
7237 |
|
|
+ //; (!REG_P(XEXP(operands[1],0)))
|
7238 |
|
|
+ ((zip_const_address_operand(XEXP(operands[1],0)))
|
7239 |
122 |
dgisselq |
+ ||(!zip_pd_opb_operand(XEXP(operands[1],0))))) {
|
7240 |
111 |
dgisselq |
+ //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
|
7241 |
|
|
+ if (can_create_pseudo_p()) {
|
7242 |
|
|
+ rtx tmp = gen_reg_rtx(Pmode);
|
7243 |
|
|
+ emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
|
7244 |
|
|
+ XEXP(operands[1],0) = tmp;
|
7245 |
|
|
+ } else if (REG_P(operands[0])) { //; Can we steal Op[0]'s reg?
|
7246 |
|
|
+ rtx tmp = operands[0];
|
7247 |
|
|
+ emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
|
7248 |
|
|
+ XEXP(operands[1],0) = tmp;
|
7249 |
|
|
+ }
|
7250 |
|
|
+ }
|
7251 |
|
|
+ }
|
7252 |
102 |
dgisselq |
+ [(set_attr "ccresult" "unchanged")])
|
7253 |
111 |
dgisselq |
+(define_insn "movsi_raw"
|
7254 |
|
|
+ [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
|
7255 |
|
|
+ (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
|
7256 |
122 |
dgisselq |
+ "(register_operand(operands[0],SImode))||(register_operand(operands[1],SImode))"
|
7257 |
111 |
dgisselq |
+ "@
|
7258 |
|
|
+ MOV\t%1,%0
|
7259 |
|
|
+ STO\t%1,%0
|
7260 |
|
|
+ LOD\t%1,%0
|
7261 |
|
|
+ LDI\t%1,%0"
|
7262 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
7263 |
102 |
dgisselq |
+(define_insn "mov<mode>_reg" ; Register to register move
|
7264 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7265 |
|
|
+ (match_operand:ZI 1 "register_operand" "r"))]
|
7266 |
|
|
+ ""
|
7267 |
|
|
+ "MOV %1,%0"
|
7268 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
7269 |
124 |
dgisselq |
+(define_insn "mov<mode>_reg_off" ; Register to register move, used by prologue
|
7270 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7271 |
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "r")
|
7272 |
111 |
dgisselq |
+ (match_operand:ZI 2 "zip_mvimm_operand_p" "M")))
|
7273 |
|
|
+ ]
|
7274 |
102 |
dgisselq |
+ ""
|
7275 |
|
|
+ "MOV %2(%1),%0"
|
7276 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
7277 |
103 |
dgisselq |
+;(define_insn "mov<mode>_lod" ; Load from memory
|
7278 |
|
|
+; [(set (match_operand:ZI 0 "register_operand" "=r")
|
7279 |
|
|
+; (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
|
7280 |
|
|
+; ""
|
7281 |
|
|
+; "LOD %1,%0"
|
7282 |
|
|
+; [(set_attr "ccresult" "unchanged")])
|
7283 |
|
|
+;(define_insn "mov<mode>_sto" ; Store into memory
|
7284 |
|
|
+; [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
|
7285 |
|
|
+; (match_operand:ZI 1 "register_operand" "r"))]
|
7286 |
|
|
+; ""
|
7287 |
|
|
+; "STO %1,%0"
|
7288 |
|
|
+; [(set_attr "ccresult" "unchanged")])
|
7289 |
|
|
+(define_expand "mov<mode>_lod" ; Load from memory
|
7290 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7291 |
|
|
+ (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
|
7292 |
103 |
dgisselq |
+ "")
|
7293 |
|
|
+(define_insn "*movsi_lod"
|
7294 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7295 |
111 |
dgisselq |
+ (match_operand:SI 1 "zip_memory_operand_p" ""))]
|
7296 |
102 |
dgisselq |
+ ""
|
7297 |
103 |
dgisselq |
+ "LOD\t%1,%0"
|
7298 |
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
7299 |
124 |
dgisselq |
+(define_insn "movsi_lod_off" ; used by epilogue code
|
7300 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7301 |
|
|
+ (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
|
7302 |
|
|
+ (match_operand:SI 2 "const_int_operand" "N"))))]
|
7303 |
|
|
+ ""
|
7304 |
|
|
+ "LOD\t%2(%1),%0"
|
7305 |
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
7306 |
103 |
dgisselq |
+(define_expand "mov<mode>_sto" ; Store into memory
|
7307 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
|
7308 |
|
|
+ (match_operand:ZI 1 "register_operand" "r"))]
|
7309 |
103 |
dgisselq |
+ "")
|
7310 |
|
|
+(define_insn "*movsi_sto"
|
7311 |
111 |
dgisselq |
+ [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
|
7312 |
103 |
dgisselq |
+ (match_operand:SI 1 "register_operand" "r"))]
|
7313 |
102 |
dgisselq |
+ ""
|
7314 |
111 |
dgisselq |
+ "STO\t%1,%0"
|
7315 |
103 |
dgisselq |
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
7316 |
124 |
dgisselq |
+(define_insn "movsi_sto_off" ; used by prologue code
|
7317 |
|
|
+ [(set (mem:SI (plus:SI
|
7318 |
|
|
+ (match_operand:SI 0 "register_operand" "r")
|
7319 |
|
|
+ (match_operand:SI 1 "const_int_operand" "N")))
|
7320 |
|
|
+ (match_operand:SI 2 "register_operand" "r"))]
|
7321 |
|
|
+ ""
|
7322 |
|
|
+ "STO\t%2,%1(%0)"
|
7323 |
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
7324 |
102 |
dgisselq |
+(define_insn "mov<mode>_ldi" ; Load immediate
|
7325 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7326 |
|
|
+ (match_operand:ZI 1 "immediate_operand" "ipU"))]
|
7327 |
|
|
+ ""
|
7328 |
|
|
+ "LDI %1,%0"
|
7329 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
7330 |
|
|
+;
|
7331 |
|
|
+;
|
7332 |
|
|
+;
|
7333 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7334 |
|
|
+;;
|
7335 |
|
|
+;; Load and store multiple values
|
7336 |
|
|
+;;
|
7337 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7338 |
|
|
+;
|
7339 |
|
|
+; So far, from the code I've seen from GCC's output,
|
7340 |
|
|
+; these instructions do not appear to be necessary.
|
7341 |
|
|
+;
|
7342 |
|
|
+;(define_insn "load_multiple"
|
7343 |
|
|
+; for(a=0; a<%2; a++)
|
7344 |
|
|
+; LOD a(%1),%0+a
|
7345 |
|
|
+;(define_insn "store_multiple"
|
7346 |
|
|
+; for(a=0; a<%2; a++)
|
7347 |
|
|
+; STO %0+a,a(%1)
|
7348 |
|
|
+; pushsi -- Do not define, compiler will work around it nicely w/o our help
|
7349 |
|
|
+;
|
7350 |
|
|
+;
|
7351 |
|
|
+;
|
7352 |
|
|
+;
|
7353 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7354 |
|
|
+;;
|
7355 |
127 |
dgisselq |
+;; Substitution Pattern
|
7356 |
|
|
+;;
|
7357 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7358 |
|
|
+;
|
7359 |
|
|
+;
|
7360 |
|
|
+(define_subst "cc_substitution"
|
7361 |
|
|
+ ; The pattern may not have any match_dup expressions.
|
7362 |
|
|
+ [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
|
7363 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7364 |
|
|
+ ""
|
7365 |
|
|
+ [(set (match_dup 0) (match_dup 1))
|
7366 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
|
7367 |
|
|
+ ])
|
7368 |
|
|
+;
|
7369 |
|
|
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
|
7370 |
|
|
+;
|
7371 |
|
|
+;
|
7372 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7373 |
|
|
+;;
|
7374 |
102 |
dgisselq |
+;; General arithmetic instructions
|
7375 |
|
|
+;;
|
7376 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
7377 |
|
|
+;
|
7378 |
|
|
+;
|
7379 |
|
|
+;
|
7380 |
|
|
+;
|
7381 |
111 |
dgisselq |
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
|
7382 |
127 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7383 |
103 |
dgisselq |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7384 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
7385 |
127 |
dgisselq |
+ ])
|
7386 |
|
|
+(define_insn_and_split "add<mode>3_split_reg"
|
7387 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7388 |
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7389 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
7390 |
|
|
+ ""
|
7391 |
|
|
+ "#" ; This code means the instruction *must* be split
|
7392 |
|
|
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
|
7393 |
|
|
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) (match_dup 2)))
|
7394 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7395 |
|
|
+ ""
|
7396 |
|
|
+ [(set_attr "predicable" "yes")])
|
7397 |
|
|
+(define_insn_and_split "add<mode>3_split_off"
|
7398 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7399 |
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7400 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7401 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
7402 |
|
|
+ ""
|
7403 |
|
|
+ "#" ; This code means the instruction *must* be split
|
7404 |
|
|
+ "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
|
7405 |
|
|
+ [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1)
|
7406 |
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
7407 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7408 |
|
|
+ ""
|
7409 |
|
|
+ [(set_attr "predicable" "yes")])
|
7410 |
|
|
+(define_insn "addsi3_reg_clobber"
|
7411 |
122 |
dgisselq |
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7412 |
|
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
7413 |
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7414 |
127 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
7415 |
|
|
+ ""
|
7416 |
|
|
+ "ADD %2,%0"
|
7417 |
|
|
+ [(set_attr "ccresult" "set")])
|
7418 |
|
|
+(define_insn "addsi3_reg_raw"
|
7419 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7420 |
|
|
+ (plus:SI (match_operand:SI 1 "register_operand" "0")
|
7421 |
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7422 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7423 |
102 |
dgisselq |
+ ""
|
7424 |
|
|
+ "ADD %2,%0"
|
7425 |
|
|
+ [(set_attr "ccresult" "set")])
|
7426 |
127 |
dgisselq |
+(define_insn "add<mode>3_off_raw"
|
7427 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7428 |
103 |
dgisselq |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7429 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7430 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7431 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7432 |
102 |
dgisselq |
+ ""
|
7433 |
|
|
+ "ADD %3+%2,%0"
|
7434 |
|
|
+ [(set_attr "ccresult" "set")])
|
7435 |
127 |
dgisselq |
+(define_insn "add<mode>3_off_clobber"
|
7436 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7437 |
|
|
+ (plus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7438 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7439 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7440 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7441 |
|
|
+ ""
|
7442 |
|
|
+ "ADD %3+%2,%0"
|
7443 |
|
|
+ [(set_attr "ccresult" "set")])
|
7444 |
102 |
dgisselq |
+;
|
7445 |
|
|
+;
|
7446 |
|
|
+;
|
7447 |
103 |
dgisselq |
+(define_expand "sub<mode>3"
|
7448 |
138 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7449 |
103 |
dgisselq |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7450 |
138 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
7451 |
127 |
dgisselq |
+(define_insn_and_split "sub<mode>3_split_reg"
|
7452 |
103 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7453 |
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7454 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
7455 |
|
|
+ ""
|
7456 |
|
|
+ "#"
|
7457 |
|
|
+ "(reload_completed)"
|
7458 |
|
|
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) (match_dup 2)))
|
7459 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7460 |
|
|
+ ""
|
7461 |
138 |
dgisselq |
+ [(set_attr "ccresult" "set") (set_attr "predicable" "yes")])
|
7462 |
127 |
dgisselq |
+(define_insn "sub<mode>3_reg_raw"
|
7463 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7464 |
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7465 |
111 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7466 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7467 |
102 |
dgisselq |
+ ""
|
7468 |
|
|
+ "SUB %2,%0"
|
7469 |
|
|
+ [(set_attr "ccresult" "set")])
|
7470 |
127 |
dgisselq |
+(define_insn "sub<mode>3_reg_clobber"
|
7471 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7472 |
103 |
dgisselq |
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7473 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7474 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7475 |
|
|
+ ""
|
7476 |
|
|
+ "SUB %2,%0"
|
7477 |
|
|
+ [(set_attr "ccresult" "set")])
|
7478 |
|
|
+(define_insn_and_split "sub<mode>3_off_split"
|
7479 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7480 |
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7481 |
103 |
dgisselq |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
7482 |
127 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
7483 |
|
|
+ ""
|
7484 |
|
|
+ "#"
|
7485 |
|
|
+ "(reload_completed)"
|
7486 |
|
|
+ [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1)
|
7487 |
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
7488 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7489 |
|
|
+ ""
|
7490 |
|
|
+ [(set_attr "ccresult" "set")])
|
7491 |
|
|
+(define_insn "sub<mode>3_off_raw"
|
7492 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7493 |
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7494 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
7495 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7496 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7497 |
102 |
dgisselq |
+ ""
|
7498 |
|
|
+ "SUB %3+%2,%0"
|
7499 |
|
|
+ [(set_attr "ccresult" "set")])
|
7500 |
127 |
dgisselq |
+(define_insn "sub<mode>3_off_clobber"
|
7501 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7502 |
|
|
+ (minus:ZI (match_operand:ZI 1 "register_operand" "0")
|
7503 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
|
7504 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7505 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7506 |
|
|
+ ""
|
7507 |
|
|
+ "SUB %3+%2,%0"
|
7508 |
|
|
+ [(set_attr "ccresult" "set")])
|
7509 |
138 |
dgisselq |
+(define_insn "mul<mode>3_oldstyle"
|
7510 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7511 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "%r")
|
7512 |
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
7513 |
122 |
dgisselq |
+ (clobber (match_scratch:ZI 3 "=r"))
|
7514 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7515 |
102 |
dgisselq |
+ ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
|
7516 |
138 |
dgisselq |
+ "(!ZIP_LONGMPY)"
|
7517 |
102 |
dgisselq |
+ "MOV %1,%0
|
7518 |
|
|
+ MPYS %2,%0
|
7519 |
|
|
+ MOV %1,%3
|
7520 |
|
|
+ ROL 16,%3
|
7521 |
|
|
+ MPYS %2,%3
|
7522 |
|
|
+ ROL 16,%3
|
7523 |
|
|
+ AND 0x0ffff,%3
|
7524 |
|
|
+ ADD %3,%0
|
7525 |
|
|
+ MOV %2,%3
|
7526 |
|
|
+ ROL 16,%3
|
7527 |
|
|
+ MPYS %1,%3
|
7528 |
|
|
+ ROL 16,%3
|
7529 |
|
|
+ AND 0x0ffff,%3
|
7530 |
|
|
+ ADD %3,%0"
|
7531 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
7532 |
138 |
dgisselq |
+;
|
7533 |
|
|
+;
|
7534 |
|
|
+(define_expand "mul<mode>3"
|
7535 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7536 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7537 |
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))]
|
7538 |
|
|
+ "(ZIP_LONGMPY)")
|
7539 |
|
|
+(define_insn_and_split "mul<mode>3_split_reg"
|
7540 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7541 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7542 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
7543 |
|
|
+ "(ZIP_LONGMPY)"
|
7544 |
|
|
+ "#"
|
7545 |
|
|
+ "(reload_completed)"
|
7546 |
|
|
+ [(parallel [(set (match_dup 0) (mult:ZI (match_dup 1) (match_dup 2)))
|
7547 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7548 |
|
|
+ ""
|
7549 |
|
|
+ [(set_attr "ccresult" "set")])
|
7550 |
|
|
+(define_insn_and_split "mul<mode>3_split_off"
|
7551 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7552 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7553 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7554 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
7555 |
|
|
+ "(ZIP_LONGMPY)"
|
7556 |
|
|
+ "#"
|
7557 |
|
|
+ "(reload_completed)"
|
7558 |
|
|
+ [(parallel [(set (match_dup 0) (mult:ZI (match_dup 1)
|
7559 |
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
7560 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7561 |
|
|
+ ""
|
7562 |
|
|
+ [(set_attr "ccresult" "set")])
|
7563 |
|
|
+(define_insn "mul<mode>3_reg_clobber"
|
7564 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7565 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7566 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7567 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7568 |
|
|
+ "(ZIP_LONGMPY)"
|
7569 |
|
|
+ "MPY\t%2,%0"
|
7570 |
|
|
+ [(set_attr "ccresult" "set")])
|
7571 |
|
|
+(define_insn "mul<mode>3_reg_raw"
|
7572 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7573 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7574 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7575 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7576 |
|
|
+ "(ZIP_LONGMPY)"
|
7577 |
|
|
+ "MPY\t%2,%0"
|
7578 |
|
|
+ [(set_attr "ccresult" "set")])
|
7579 |
|
|
+(define_insn "mul<mode>3_off_raw"
|
7580 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7581 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7582 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7583 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7584 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7585 |
|
|
+ "(ZIP_LONGMPY)"
|
7586 |
|
|
+ "MPY\t%3+%2,%0"
|
7587 |
|
|
+ [(set_attr "ccresult" "set")])
|
7588 |
|
|
+(define_insn "mul<mode>3_off_clobber"
|
7589 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7590 |
|
|
+ (mult:ZI (match_operand:ZI 1 "register_operand" "0")
|
7591 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7592 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7593 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7594 |
|
|
+ "(ZIP_LONGMPY)"
|
7595 |
|
|
+ "MPY\t%3+%2,%0"
|
7596 |
|
|
+ [(set_attr "ccresult" "set")])
|
7597 |
|
|
+;
|
7598 |
|
|
+;
|
7599 |
|
|
+(define_expand "smulsi3_highpart"
|
7600 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7601 |
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
7602 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7603 |
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
|
7604 |
|
|
+ (const_int 32))))]
|
7605 |
|
|
+ "(ZIP_LONGMPY)")
|
7606 |
|
|
+(define_insn_and_split "smulsi3_highpart_split_reg"
|
7607 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7608 |
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
7609 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7610 |
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7611 |
|
|
+ (const_int 32))))]
|
7612 |
|
|
+ "(ZIP_LONGMPY)"
|
7613 |
|
|
+ "#"
|
7614 |
|
|
+ "(reload_completed)"
|
7615 |
|
|
+ [(parallel [(set (match_dup 0)
|
7616 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7617 |
|
|
+ (mult:DI
|
7618 |
|
|
+ (sign_extend:DI (match_dup 1))
|
7619 |
|
|
+ (sign_extend:DI (match_dup 2)))
|
7620 |
|
|
+ (const_int 32))))
|
7621 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7622 |
|
|
+ ""
|
7623 |
|
|
+ [(set_attr "ccresult" "set")])
|
7624 |
|
|
+(define_insn_and_split "smulsi3_highpart_split_off"
|
7625 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7626 |
|
|
+ (truncate:SI (ashift:DI (mult:DI
|
7627 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7628 |
|
|
+ (sign_extend:DI
|
7629 |
|
|
+ (plus:SI (match_operand:SI 2 "register_operand" "r")
|
7630 |
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
7631 |
|
|
+ (const_int 32))))]
|
7632 |
|
|
+ "(ZIP_LONGMPY)"
|
7633 |
|
|
+ "#"
|
7634 |
|
|
+ "(reload_completed)"
|
7635 |
|
|
+ [(parallel [(set (match_dup 0)
|
7636 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7637 |
|
|
+ (mult:SI
|
7638 |
|
|
+ (sign_extend:DI (match_dup 1))
|
7639 |
|
|
+ (sign_extend:DI
|
7640 |
|
|
+ (plus:SI (match_dup 2) (match_dup 3))))
|
7641 |
|
|
+ (const_int 32))))
|
7642 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7643 |
|
|
+ ""
|
7644 |
|
|
+ [(set_attr "ccresult" "set")])
|
7645 |
|
|
+(define_insn "smulsi3_highpart_reg_clobber"
|
7646 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7647 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7648 |
|
|
+ (mult:SI
|
7649 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7650 |
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7651 |
|
|
+ (const_int 32))))
|
7652 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7653 |
|
|
+ "(ZIP_LONGMPY)"
|
7654 |
|
|
+ "MPYSHI\t%2,%0"
|
7655 |
|
|
+ [(set_attr "ccresult" "set")])
|
7656 |
|
|
+(define_insn "smulsi3_highpart_reg_raw"
|
7657 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7658 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7659 |
|
|
+ (mult:SI
|
7660 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7661 |
|
|
+ (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7662 |
|
|
+ (const_int 32))))
|
7663 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7664 |
|
|
+ "(ZIP_LONGMPY)"
|
7665 |
|
|
+ "MPYSHI\t%2,%0"
|
7666 |
|
|
+ [(set_attr "ccresult" "set")])
|
7667 |
|
|
+(define_insn "smulsi3_highpart_off_raw"
|
7668 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7669 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7670 |
|
|
+ (mult:SI
|
7671 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7672 |
|
|
+ (sign_extend:DI (plus:SI
|
7673 |
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
7674 |
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
7675 |
|
|
+ (const_int 32))))
|
7676 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7677 |
|
|
+ "(ZIP_LONGMPY)"
|
7678 |
|
|
+ "MPYSHI\t%3+%2,%0"
|
7679 |
|
|
+ [(set_attr "ccresult" "set")])
|
7680 |
|
|
+(define_insn "smulsi3_highpart_off_clobber"
|
7681 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7682 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7683 |
|
|
+ (mult:SI
|
7684 |
|
|
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7685 |
|
|
+ (sign_extend:DI (plus:SI
|
7686 |
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
7687 |
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
7688 |
|
|
+ (const_int 32))))
|
7689 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7690 |
|
|
+ "(ZIP_LONGMPY)"
|
7691 |
|
|
+ "MPYSHI\t%3+%2,%0"
|
7692 |
|
|
+ [(set_attr "ccresult" "set")])
|
7693 |
|
|
+;
|
7694 |
|
|
+;
|
7695 |
|
|
+(define_expand "umulsi3_highpart"
|
7696 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7697 |
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
7698 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7699 |
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
|
7700 |
|
|
+ (const_int 32))))]
|
7701 |
|
|
+ "(ZIP_LONGMPY)")
|
7702 |
|
|
+(define_insn_and_split "umulsi3_highpart_split_reg"
|
7703 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7704 |
|
|
+ (truncate:SI (ashiftrt:DI (mult:DI
|
7705 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7706 |
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7707 |
|
|
+ (const_int 32))))]
|
7708 |
|
|
+ "(ZIP_LONGMPY)"
|
7709 |
|
|
+ "#"
|
7710 |
|
|
+ "(reload_completed)"
|
7711 |
|
|
+ [(parallel [(set (match_dup 0)
|
7712 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7713 |
|
|
+ (mult:SI
|
7714 |
|
|
+ (zero_extend:DI (match_dup 1))
|
7715 |
|
|
+ (zero_extend:DI (match_dup 2)))
|
7716 |
|
|
+ (const_int 32))))
|
7717 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7718 |
|
|
+ ""
|
7719 |
|
|
+ [(set_attr "ccresult" "set")])
|
7720 |
|
|
+(define_insn_and_split "umulsi3_highpart_split_off"
|
7721 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7722 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7723 |
|
|
+ (mult:DI
|
7724 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7725 |
|
|
+ (zero_extend:DI
|
7726 |
|
|
+ (plus:SI (match_operand:SI 2 "register_operand" "r")
|
7727 |
|
|
+ (match_operand:SI 3 "zip_opb_immv_p" "N"))))
|
7728 |
|
|
+ (const_int 32))))]
|
7729 |
|
|
+ "(ZIP_LONGMPY)"
|
7730 |
|
|
+ "#"
|
7731 |
|
|
+ "(reload_completed)"
|
7732 |
|
|
+ [(parallel [(set (match_dup 0)
|
7733 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7734 |
|
|
+ (mult:DI
|
7735 |
|
|
+ (zero_extend:DI (match_dup 1))
|
7736 |
|
|
+ (zero_extend:DI
|
7737 |
|
|
+ (plus:SI (match_dup 2) (match_dup 3))))
|
7738 |
|
|
+ (const_int 32))))
|
7739 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7740 |
|
|
+ ""
|
7741 |
|
|
+ [(set_attr "ccresult" "set")])
|
7742 |
|
|
+(define_insn "umulsi3_highpart_reg_clobber"
|
7743 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7744 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7745 |
|
|
+ (mult:DI
|
7746 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7747 |
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7748 |
|
|
+ (const_int 32))))
|
7749 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7750 |
|
|
+ "(ZIP_LONGMPY)"
|
7751 |
|
|
+ "MPYSHI\t%2,%0"
|
7752 |
|
|
+ [(set_attr "ccresult" "set")])
|
7753 |
|
|
+(define_insn "umulsi3_highpart_reg_raw"
|
7754 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7755 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7756 |
|
|
+ (mult:DI
|
7757 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7758 |
|
|
+ (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
|
7759 |
|
|
+ (const_int 32))))
|
7760 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7761 |
|
|
+ "(ZIP_LONGMPY)"
|
7762 |
|
|
+ "MPYSHI\t%2,%0"
|
7763 |
|
|
+ [(set_attr "ccresult" "set")])
|
7764 |
|
|
+(define_insn "umulsi3_highpart_off_raw"
|
7765 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7766 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7767 |
|
|
+ (mult:DI
|
7768 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7769 |
|
|
+ (zero_extend:DI (plus:SI
|
7770 |
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
7771 |
|
|
+ (match_operand:DI 3 "zip_opb_immv_p" "N"))))
|
7772 |
|
|
+ (const_int 32))))
|
7773 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7774 |
|
|
+ "(ZIP_LONGMPY)"
|
7775 |
|
|
+ "MPYSHI\t%3+%2,%0"
|
7776 |
|
|
+ [(set_attr "ccresult" "set")])
|
7777 |
|
|
+(define_insn "umulsi3_highpart_off_clobber"
|
7778 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
7779 |
|
|
+ (truncate:SI (ashiftrt:DI
|
7780 |
|
|
+ (mult:DI
|
7781 |
|
|
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
|
7782 |
|
|
+ (zero_extend:DI (plus:SI
|
7783 |
|
|
+ (match_operand:SI 2 "register_operand" "r")
|
7784 |
|
|
+ (match_operand:DI 3 "zip_opb_immv_p" "N"))))
|
7785 |
|
|
+ (const_int 32))))
|
7786 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7787 |
|
|
+ "(ZIP_LONGMPY)"
|
7788 |
|
|
+ "MPYSHI\t%3+%2,%0"
|
7789 |
|
|
+ [(set_attr "ccresult" "set")])
|
7790 |
|
|
+;
|
7791 |
|
|
+;
|
7792 |
111 |
dgisselq |
+(define_expand "div<mode>3"
|
7793 |
122 |
dgisselq |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
7794 |
103 |
dgisselq |
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
|
7795 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
7796 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
7797 |
111 |
dgisselq |
+ "(ZIP_DIVIDE)")
|
7798 |
|
|
+(define_insn "div<mode>3_reg"
|
7799 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7800 |
|
|
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
|
7801 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7802 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7803 |
111 |
dgisselq |
+ "(ZIP_DIVIDE)"
|
7804 |
102 |
dgisselq |
+ "DIVS %2,%0"
|
7805 |
|
|
+ [(set_attr "ccresult" "set")])
|
7806 |
|
|
+(define_insn "div<mode>3_off"
|
7807 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7808 |
103 |
dgisselq |
+ (div:ZI (match_operand:ZI 1 "register_operand" "0")
|
7809 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7810 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7811 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7812 |
111 |
dgisselq |
+ "(ZIP_DIVIDE)"
|
7813 |
102 |
dgisselq |
+ "DIVS %3+%2,%0"
|
7814 |
|
|
+ [(set_attr "ccresult" "set")])
|
7815 |
111 |
dgisselq |
+(define_expand "udiv<mode>3"
|
7816 |
122 |
dgisselq |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
7817 |
103 |
dgisselq |
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
|
7818 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
7819 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
7820 |
111 |
dgisselq |
+ "(ZIP_DIVIDE)")
|
7821 |
|
|
+(define_insn "udiv<mode>3_reg"
|
7822 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7823 |
|
|
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
|
7824 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7825 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7826 |
111 |
dgisselq |
+ "(ZIP_DIVIDE)"
|
7827 |
102 |
dgisselq |
+ "DIVU %2,%0"
|
7828 |
|
|
+ [(set_attr "ccresult" "set")])
|
7829 |
|
|
+(define_insn "udiv<mode>3_off"
|
7830 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7831 |
103 |
dgisselq |
+ (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
|
7832 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7833 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7834 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7835 |
111 |
dgisselq |
+ "(ZIP_DIVIDE)"
|
7836 |
102 |
dgisselq |
+ "DIVU %3+%2,%0"
|
7837 |
|
|
+ [(set_attr "ccresult" "set")])
|
7838 |
|
|
+;;
|
7839 |
|
|
+;; modsi3
|
7840 |
|
|
+;; umodsi3
|
7841 |
|
|
+;;
|
7842 |
|
|
+(define_insn "umin<mode>3"
|
7843 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7844 |
|
|
+ (umin:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7845 |
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
7846 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
7847 |
102 |
dgisselq |
+ ]
|
7848 |
|
|
+ ""
|
7849 |
|
|
+ "CMP %0,%2
|
7850 |
|
|
+ MOV.C %2,%0"
|
7851 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
7852 |
|
|
+(define_insn "umax<mode>3"
|
7853 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7854 |
|
|
+ (umax:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7855 |
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
7856 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
7857 |
102 |
dgisselq |
+ ]
|
7858 |
|
|
+ ""
|
7859 |
|
|
+ "CMP %2,%0
|
7860 |
|
|
+ MOV.C %2,%0"
|
7861 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
7862 |
|
|
+(define_insn "smin<mode>3"
|
7863 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7864 |
|
|
+ (smin:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7865 |
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
7866 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
7867 |
102 |
dgisselq |
+ ]
|
7868 |
|
|
+ ""
|
7869 |
|
|
+ "CMP %2,%0
|
7870 |
|
|
+ MOV.GT %2,%0"
|
7871 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
7872 |
|
|
+(define_insn "smax<mode>3"
|
7873 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7874 |
|
|
+ (smax:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7875 |
|
|
+ (match_operand:ZI 2 "register_operand" "r")))
|
7876 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
7877 |
102 |
dgisselq |
+ ]
|
7878 |
|
|
+ ""
|
7879 |
|
|
+ "CMP %0,%2
|
7880 |
|
|
+ MOV.LT %2,%0"
|
7881 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
7882 |
127 |
dgisselq |
+;
|
7883 |
|
|
+;
|
7884 |
111 |
dgisselq |
+(define_expand "and<mode>3"
|
7885 |
127 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7886 |
102 |
dgisselq |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7887 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
7888 |
|
|
+(define_insn_and_split "and<mode>3_reg_split"
|
7889 |
111 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7890 |
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7891 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
7892 |
|
|
+ ""
|
7893 |
|
|
+ "#"
|
7894 |
|
|
+ "(reload_completed)"
|
7895 |
|
|
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) (match_dup 2)))
|
7896 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7897 |
|
|
+ ""
|
7898 |
|
|
+ [(set_attr "ccresult" "set")])
|
7899 |
|
|
+(define_insn "and<mode>3_reg_raw"
|
7900 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7901 |
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7902 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7903 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7904 |
102 |
dgisselq |
+ ""
|
7905 |
|
|
+ "AND %2,%0"
|
7906 |
|
|
+ [(set_attr "ccresult" "set")])
|
7907 |
127 |
dgisselq |
+(define_insn "and<mode>3_reg_clobber"
|
7908 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7909 |
127 |
dgisselq |
+ (and:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7910 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7911 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7912 |
|
|
+ ""
|
7913 |
|
|
+ "AND %2,%0"
|
7914 |
|
|
+ [(set_attr "ccresult" "set")])
|
7915 |
|
|
+(define_insn_and_split "and<mode>3_off_split"
|
7916 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7917 |
102 |
dgisselq |
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
7918 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7919 |
127 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
7920 |
|
|
+ ""
|
7921 |
|
|
+ "#"
|
7922 |
|
|
+ "(reload_completed)"
|
7923 |
|
|
+ [(parallel [(set (match_dup 0) (and:ZI (match_dup 1)
|
7924 |
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
7925 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7926 |
|
|
+ ""
|
7927 |
|
|
+ [(set_attr "ccresult" "set")])
|
7928 |
|
|
+(define_insn "and<mode>3_off_raw"
|
7929 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7930 |
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
7931 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7932 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7933 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7934 |
102 |
dgisselq |
+ ""
|
7935 |
|
|
+ "AND %3+%2,%0"
|
7936 |
|
|
+ [(set_attr "ccresult" "set")])
|
7937 |
127 |
dgisselq |
+(define_insn "and<mode>3_off_clobber"
|
7938 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7939 |
|
|
+ (and:ZI (match_operand:ZI 1 "register_operand" "0")
|
7940 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7941 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7942 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7943 |
|
|
+ ""
|
7944 |
|
|
+ "AND %3+%2,%0"
|
7945 |
|
|
+ [(set_attr "ccresult" "set")])
|
7946 |
|
|
+;
|
7947 |
|
|
+;
|
7948 |
111 |
dgisselq |
+(define_expand "ior<mode>3"
|
7949 |
127 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7950 |
102 |
dgisselq |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7951 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))])
|
7952 |
|
|
+(define_insn_and_split "ior<mode>3_reg_split"
|
7953 |
111 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7954 |
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7955 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
7956 |
|
|
+ ""
|
7957 |
|
|
+ "#"
|
7958 |
|
|
+ "(reload_completed)"
|
7959 |
|
|
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) (match_dup 2)))
|
7960 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7961 |
|
|
+ ""
|
7962 |
|
|
+ [(set_attr "ccresult" "set")])
|
7963 |
|
|
+(define_insn "ior<mode>3_reg_raw"
|
7964 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7965 |
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7966 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7967 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7968 |
102 |
dgisselq |
+ ""
|
7969 |
|
|
+ "OR %2,%0"
|
7970 |
|
|
+ [(set_attr "ccresult" "set")])
|
7971 |
127 |
dgisselq |
+(define_insn "ior<mode>3_reg_clobber"
|
7972 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7973 |
127 |
dgisselq |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
|
7974 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
7975 |
|
|
+ (clobber (reg:CC CC_REG))]
|
7976 |
|
|
+ ""
|
7977 |
|
|
+ "OR %2,%0"
|
7978 |
|
|
+ [(set_attr "ccresult" "set")])
|
7979 |
|
|
+(define_insn_and_split "ior<mode>3_off_split"
|
7980 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7981 |
102 |
dgisselq |
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
7982 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7983 |
127 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
7984 |
|
|
+ ""
|
7985 |
|
|
+ "#"
|
7986 |
|
|
+ "(reload_completed)"
|
7987 |
|
|
+ [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1)
|
7988 |
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
7989 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
7990 |
|
|
+ ""
|
7991 |
|
|
+ [(set_attr "ccresult" "set")])
|
7992 |
|
|
+(define_insn "ior<mode>3_off_raw"
|
7993 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
7994 |
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
7995 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
7996 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
7997 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
7998 |
102 |
dgisselq |
+ ""
|
7999 |
|
|
+ "OR %3+%2,%0"
|
8000 |
|
|
+ [(set_attr "ccresult" "set")])
|
8001 |
127 |
dgisselq |
+(define_insn "ior<mode>3_off_clobber"
|
8002 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8003 |
|
|
+ (ior:ZI (match_operand:ZI 1 "register_operand" "0")
|
8004 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
8005 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
8006 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8007 |
|
|
+ ""
|
8008 |
|
|
+ "OR %3+%2,%0"
|
8009 |
|
|
+ [(set_attr "ccresult" "set")])
|
8010 |
|
|
+;
|
8011 |
|
|
+;
|
8012 |
|
|
+;
|
8013 |
111 |
dgisselq |
+(define_expand "xor<mode>3"
|
8014 |
122 |
dgisselq |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
8015 |
102 |
dgisselq |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
8016 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_operand_p" "")))
|
8017 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
|
8018 |
|
|
+ "")
|
8019 |
127 |
dgisselq |
+(define_insn_and_split "xor<mode>3_reg_split"
|
8020 |
111 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8021 |
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
8022 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
|
8023 |
|
|
+ ""
|
8024 |
|
|
+ "#"
|
8025 |
|
|
+ "(reload_completed)"
|
8026 |
|
|
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) (match_dup 2)))
|
8027 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
8028 |
|
|
+ ""
|
8029 |
|
|
+ [(set_attr "ccresult" "set")])
|
8030 |
|
|
+(define_insn "xor<mode>3_reg_raw"
|
8031 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8032 |
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
8033 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
8034 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8035 |
102 |
dgisselq |
+ ""
|
8036 |
|
|
+ "XOR %2,%0"
|
8037 |
|
|
+ [(set_attr "ccresult" "set")])
|
8038 |
127 |
dgisselq |
+(define_insn "xor<mode>3_reg_clobber"
|
8039 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8040 |
127 |
dgisselq |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
|
8041 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
8042 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8043 |
|
|
+ ""
|
8044 |
|
|
+ "XOR %2,%0"
|
8045 |
|
|
+ [(set_attr "ccresult" "set")])
|
8046 |
|
|
+(define_insn_and_split "xor<mode>3_off_split"
|
8047 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8048 |
102 |
dgisselq |
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
8049 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
8050 |
127 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
|
8051 |
|
|
+ ""
|
8052 |
|
|
+ "#"
|
8053 |
|
|
+ "(reload_completed)"
|
8054 |
|
|
+ [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1)
|
8055 |
|
|
+ (plus:ZI (match_dup 2) (match_dup 3))))
|
8056 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
8057 |
|
|
+ ""
|
8058 |
|
|
+ [(set_attr "ccresult" "set")])
|
8059 |
|
|
+(define_insn "xor<mode>3_off_raw"
|
8060 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8061 |
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
8062 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
8063 |
122 |
dgisselq |
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
8064 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8065 |
102 |
dgisselq |
+ ""
|
8066 |
|
|
+ "XOR %3+%2,%0"
|
8067 |
|
|
+ [(set_attr "ccresult" "set")])
|
8068 |
127 |
dgisselq |
+(define_insn "xor<mode>3_off_clobber"
|
8069 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8070 |
|
|
+ (xor:ZI (match_operand:ZI 1 "register_operand" "0")
|
8071 |
|
|
+ (plus:ZI (match_operand:ZI 2 "register_operand" "r")
|
8072 |
|
|
+ (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
|
8073 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8074 |
|
|
+ ""
|
8075 |
|
|
+ "XOR %3+%2,%0"
|
8076 |
|
|
+ [(set_attr "ccresult" "set")])
|
8077 |
102 |
dgisselq |
+;(define_insn "addv<mode>4"
|
8078 |
|
|
+ ;[(set (match_operand:ZI 0 "register_operand" "=r")
|
8079 |
|
|
+ ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
|
8080 |
|
|
+ ;(match_operand:ZI 2 "general_operand" "rO")))
|
8081 |
122 |
dgisselq |
+ ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
8082 |
102 |
dgisselq |
+ ;(label_ref (match_operand 3))
|
8083 |
|
|
+ ;(pc)))]
|
8084 |
|
|
+ ;""
|
8085 |
|
|
+ ;"MOV %1,%0
|
8086 |
|
|
+ ;ADD %2,%0
|
8087 |
|
|
+ ;BV %3"
|
8088 |
|
|
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
8089 |
|
|
+;;(define_insn "subvsi4"
|
8090 |
|
|
+;; MOV %1,%0
|
8091 |
|
|
+;; SUB %2,%0
|
8092 |
|
|
+;; BV %3
|
8093 |
|
|
+;;(mulvsi4)
|
8094 |
|
|
+;;(define_insn "uaddvsi4"
|
8095 |
|
|
+;; ADD %2,%0
|
8096 |
|
|
+;; BC %3
|
8097 |
|
|
+;;(define_insn "usubvsi4"
|
8098 |
|
|
+;; MOV %1,%0
|
8099 |
|
|
+;; SUB %2,%0
|
8100 |
|
|
+;; BC %3
|
8101 |
|
|
+;;
|
8102 |
|
|
+;; (define_insn "umulvsi4"
|
8103 |
|
|
+;; ... ???)
|
8104 |
|
|
+;;
|
8105 |
127 |
dgisselq |
+(define_expand "ashr<mode>3"
|
8106 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8107 |
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8108 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
8109 |
|
|
+(define_insn_and_split "ashr<mode>3_split"
|
8110 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8111 |
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8112 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
8113 |
|
|
+ ""
|
8114 |
|
|
+ "#"
|
8115 |
|
|
+ "(reload_completed)"
|
8116 |
|
|
+ [(parallel [(set (match_dup 0) (ashiftrt:ZI (match_dup 1) (match_dup 2)))
|
8117 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
8118 |
|
|
+ ""
|
8119 |
|
|
+ [(set_attr "ccresult" "set")])
|
8120 |
|
|
+(define_insn "ashr<mode>3_raw"
|
8121 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8122 |
|
|
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8123 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8124 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8125 |
102 |
dgisselq |
+ ""
|
8126 |
|
|
+ "ASR %2,%0"
|
8127 |
|
|
+ [(set_attr "ccresult" "set")])
|
8128 |
127 |
dgisselq |
+(define_insn "ashr<mode>3_clobber"
|
8129 |
111 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8130 |
127 |
dgisselq |
+ (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8131 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8132 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8133 |
|
|
+ ""
|
8134 |
|
|
+ "ASR %2,%0"
|
8135 |
|
|
+ [(set_attr "ccresult" "set")])
|
8136 |
|
|
+;
|
8137 |
|
|
+;
|
8138 |
|
|
+(define_expand "ashl<mode>3"
|
8139 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8140 |
111 |
dgisselq |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
8141 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
8142 |
|
|
+(define_insn_and_split "ashl<mode>3_split"
|
8143 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8144 |
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
8145 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
8146 |
|
|
+ ""
|
8147 |
|
|
+ "#"
|
8148 |
|
|
+ "(reload_completed)"
|
8149 |
|
|
+ [(parallel [(set (match_dup 0) (ashift:ZI (match_dup 1) (match_dup 2)))
|
8150 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
8151 |
|
|
+ ""
|
8152 |
|
|
+ [(set_attr "ccresult" "set")])
|
8153 |
|
|
+(define_insn "ashl<mode>3_raw"
|
8154 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8155 |
|
|
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
8156 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8157 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8158 |
111 |
dgisselq |
+ ""
|
8159 |
122 |
dgisselq |
+ "LSL %2,%0"
|
8160 |
111 |
dgisselq |
+ [(set_attr "ccresult" "set")])
|
8161 |
127 |
dgisselq |
+(define_insn "ashl<mode>3_clobber"
|
8162 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8163 |
127 |
dgisselq |
+ (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
|
8164 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8165 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8166 |
|
|
+ ""
|
8167 |
|
|
+ "LSL %2,%0"
|
8168 |
|
|
+ [(set_attr "ccresult" "set")])
|
8169 |
|
|
+;
|
8170 |
|
|
+;
|
8171 |
|
|
+(define_expand "lshr<mode>3"
|
8172 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8173 |
102 |
dgisselq |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8174 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
8175 |
|
|
+(define_insn_and_split "lshr<mode>3_split"
|
8176 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8177 |
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8178 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
8179 |
|
|
+ ""
|
8180 |
|
|
+ "#"
|
8181 |
|
|
+ "(reload_completed)"
|
8182 |
|
|
+ [(parallel [(set (match_dup 0) (lshiftrt:ZI (match_dup 1) (match_dup 2)))
|
8183 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
8184 |
|
|
+ ""
|
8185 |
|
|
+ [(set_attr "ccresult" "set")])
|
8186 |
|
|
+(define_insn "lshr<mode>3_raw"
|
8187 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8188 |
|
|
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8189 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8190 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8191 |
102 |
dgisselq |
+ ""
|
8192 |
|
|
+ "LSR %2,%0"
|
8193 |
|
|
+ [(set_attr "ccresult" "set")])
|
8194 |
127 |
dgisselq |
+(define_insn "lshr<mode>3_clobber"
|
8195 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8196 |
127 |
dgisselq |
+ (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
|
8197 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8198 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8199 |
|
|
+ ""
|
8200 |
|
|
+ "LSR %2,%0"
|
8201 |
|
|
+ [(set_attr "ccresult" "set")])
|
8202 |
|
|
+;
|
8203 |
|
|
+;
|
8204 |
|
|
+(define_expand "rotl<mode>3"
|
8205 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8206 |
102 |
dgisselq |
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
8207 |
127 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
|
8208 |
|
|
+(define_insn_and_split "rotl<mode>3_split"
|
8209 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8210 |
|
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
8211 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
|
8212 |
|
|
+ ""
|
8213 |
|
|
+ "#"
|
8214 |
|
|
+ "(reload_completed)"
|
8215 |
|
|
+ [(parallel [(set (match_dup 0) (rotate:ZI (match_dup 1) (match_dup 2)))
|
8216 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
8217 |
|
|
+ ""
|
8218 |
|
|
+ [(set_attr "ccresult" "set")])
|
8219 |
|
|
+(define_insn "rotl<mode>3_raw"
|
8220 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8221 |
|
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
8222 |
122 |
dgisselq |
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8223 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8224 |
102 |
dgisselq |
+ ""
|
8225 |
|
|
+ "ROL %2,%0"
|
8226 |
|
|
+ [(set_attr "ccresult" "set")])
|
8227 |
127 |
dgisselq |
+(define_insn "rotl<mode>3_clobber"
|
8228 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8229 |
|
|
+ (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
|
8230 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
|
8231 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8232 |
|
|
+ ""
|
8233 |
|
|
+ "ROL %2,%0"
|
8234 |
|
|
+ [(set_attr "ccresult" "set")])
|
8235 |
102 |
dgisselq |
+;
|
8236 |
127 |
dgisselq |
+;
|
8237 |
|
|
+;
|
8238 |
102 |
dgisselq |
+(define_insn "neg<mode>2"
|
8239 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8240 |
|
|
+ (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
|
8241 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
8242 |
102 |
dgisselq |
+ ""
|
8243 |
|
|
+ "NEG %1,%0"
|
8244 |
|
|
+ [(set_attr "ccresult" "validzn")])
|
8245 |
|
|
+(define_insn "abs<mode>2"
|
8246 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8247 |
|
|
+ (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
|
8248 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
8249 |
102 |
dgisselq |
+ ""
|
8250 |
|
|
+ "TEST %0
|
8251 |
|
|
+ NEG.LT %0"
|
8252 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8253 |
|
|
+(define_insn "popcount<mode>2"
|
8254 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8255 |
|
|
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
|
8256 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8257 |
102 |
dgisselq |
+ ""
|
8258 |
|
|
+ "POPC %1,%0"
|
8259 |
|
|
+ [(set_attr "ccresult" "set")])
|
8260 |
|
|
+(define_expand "parity<mode>2"
|
8261 |
122 |
dgisselq |
+ [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
|
8262 |
102 |
dgisselq |
+ (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
|
8263 |
127 |
dgisselq |
+ (clobber (reg:CC CC_REG))])
|
8264 |
122 |
dgisselq |
+ (parallel [
|
8265 |
|
|
+ (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
|
8266 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
8267 |
102 |
dgisselq |
+ ])
|
8268 |
|
|
+(define_insn "one_cmpl<mode>2"
|
8269 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8270 |
|
|
+ (not:ZI (match_operand:ZI 1 "register_operand" "0")))
|
8271 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
8272 |
102 |
dgisselq |
+ ""
|
8273 |
|
|
+ "XOR -1,%0"
|
8274 |
|
|
+ [(set_attr "ccresult" "set")])
|
8275 |
|
|
+;
|
8276 |
|
|
+;
|
8277 |
|
|
+;
|
8278 |
|
|
+;
|
8279 |
117 |
dgisselq |
+;
|
8280 |
102 |
dgisselq |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8281 |
|
|
+;;
|
8282 |
|
|
+;; General arithmetic instructions -- double words
|
8283 |
|
|
+;;
|
8284 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8285 |
|
|
+;
|
8286 |
|
|
+;
|
8287 |
|
|
+;
|
8288 |
111 |
dgisselq |
+(define_expand "movdi3"
|
8289 |
|
|
+ [(set (match_operand:DI 0 "nonimmediate_operand" "")
|
8290 |
|
|
+ (match_operand:DI 1 "general_operand" ""))])
|
8291 |
|
|
+(define_insn "movdi_lod"
|
8292 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8293 |
122 |
dgisselq |
+ (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
|
8294 |
111 |
dgisselq |
+ ""
|
8295 |
|
|
+ {
|
8296 |
122 |
dgisselq |
+ if (REG_P(operands[1]))
|
8297 |
111 |
dgisselq |
+ return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
|
8298 |
122 |
dgisselq |
+ else if (GET_CODE(operands[1])==PLUS) {
|
8299 |
|
|
+ if ((REG_P(XEXP(operands[1],0)))
|
8300 |
|
|
+ &&(CONST_INT_P(XEXP(operands[1],1)))) {
|
8301 |
111 |
dgisselq |
+ static char buf[64];
|
8302 |
|
|
+ sprintf(buf,
|
8303 |
|
|
+ "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
|
8304 |
138 |
dgisselq |
+ (long)INTVAL(XEXP(operands[1],1)),
|
8305 |
|
|
+ (long)INTVAL(XEXP(operands[1],1)+1));
|
8306 |
111 |
dgisselq |
+ return buf;
|
8307 |
|
|
+ }
|
8308 |
122 |
dgisselq |
+ } return "BREAK";
|
8309 |
111 |
dgisselq |
+ }
|
8310 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8311 |
|
|
+(define_insn "movdi_sto"
|
8312 |
|
|
+ [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
|
8313 |
|
|
+ (match_operand:DI 1 "register_operand" "r"))]
|
8314 |
|
|
+ ""
|
8315 |
|
|
+ {
|
8316 |
|
|
+ if (REG_P(operands[0]))
|
8317 |
|
|
+ return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
|
8318 |
|
|
+ else if (GET_CODE(operands[0])==PLUS) {
|
8319 |
|
|
+ if ((REG_P(XEXP(operands[0],0)))
|
8320 |
|
|
+ &&(CONST_INT_P(XEXP(operands[0],1)))) {
|
8321 |
|
|
+ static char buf[64];
|
8322 |
|
|
+ sprintf(buf,
|
8323 |
|
|
+ "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
|
8324 |
138 |
dgisselq |
+ (long)INTVAL(XEXP(operands[0],1)),
|
8325 |
|
|
+ (long)INTVAL(XEXP(operands[0],1)+1));
|
8326 |
111 |
dgisselq |
+ return buf;
|
8327 |
|
|
+ }
|
8328 |
127 |
dgisselq |
+ } return "BREAK";
|
8329 |
111 |
dgisselq |
+ }
|
8330 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8331 |
|
|
+(define_insn "movdi_ldi"
|
8332 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8333 |
|
|
+ (match_operand:DI 1 "immediate_operand" "i"))]
|
8334 |
|
|
+ ""
|
8335 |
|
|
+ "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
|
8336 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8337 |
102 |
dgisselq |
+(define_insn "adddi3" ; Fastest/best instruction always goes first
|
8338 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8339 |
103 |
dgisselq |
+ (plus:DI (match_operand:DI 1 "register_operand" "0")
|
8340 |
102 |
dgisselq |
+ (match_operand:DI 2 "register_operand" "r")))
|
8341 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8342 |
102 |
dgisselq |
+ ]
|
8343 |
|
|
+ ""
|
8344 |
|
|
+ "ADD %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
|
8345 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8346 |
|
|
+;
|
8347 |
|
|
+(define_insn "subdi3"
|
8348 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8349 |
103 |
dgisselq |
+ (minus:DI (match_operand:DI 1 "register_operand" "0")
|
8350 |
102 |
dgisselq |
+ (match_operand:DI 2 "register_operand" "r")))
|
8351 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8352 |
102 |
dgisselq |
+ ]
|
8353 |
|
|
+ ""
|
8354 |
|
|
+ "SUB %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
|
8355 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8356 |
|
|
+;
|
8357 |
|
|
+(define_insn "anddi3"
|
8358 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8359 |
|
|
+ (and:DI (match_operand:DI 1 "register_operand" "%0")
|
8360 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
8361 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8362 |
102 |
dgisselq |
+ ]
|
8363 |
|
|
+ ""
|
8364 |
|
|
+ "AND %L2,%L0\n\tAND\t%H2,%H0"
|
8365 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8366 |
|
|
+;
|
8367 |
|
|
+(define_insn "iordi3"
|
8368 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8369 |
|
|
+ (ior:DI (match_operand:DI 1 "register_operand" "%0")
|
8370 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
8371 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8372 |
102 |
dgisselq |
+ ]
|
8373 |
|
|
+ ""
|
8374 |
|
|
+ "OR %2,%0\n\tOR\t%H2,%H0"
|
8375 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8376 |
|
|
+;
|
8377 |
|
|
+(define_insn "xordi3"
|
8378 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8379 |
|
|
+ (xor:DI (match_operand:DI 1 "register_operand" "%0")
|
8380 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
8381 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8382 |
102 |
dgisselq |
+ ]
|
8383 |
|
|
+ ""
|
8384 |
|
|
+ "XOR %2,%0\n\tXOR\t%H2,%H0"
|
8385 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8386 |
|
|
+;
|
8387 |
|
|
+(define_insn "negdi2"
|
8388 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8389 |
122 |
dgisselq |
+ (neg:DI (match_operand:DI 1 "register_operand" "0")))
|
8390 |
|
|
+ (clobber (reg:CC CC_REG))
|
8391 |
|
|
+ ]
|
8392 |
102 |
dgisselq |
+ ""
|
8393 |
|
|
+ "XOR -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
|
8394 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8395 |
|
|
+;
|
8396 |
|
|
+(define_insn "absdi2"
|
8397 |
122 |
dgisselq |
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8398 |
|
|
+ (abs:DI (match_operand:DI 1 "register_operand" "0")))
|
8399 |
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
8400 |
|
|
+ (clobber (reg:CC CC_REG))
|
8401 |
|
|
+ ]
|
8402 |
102 |
dgisselq |
+ ""
|
8403 |
|
|
+ "CLR %2
|
8404 |
|
|
+ TEST %H0 ; Problem, we can't tell conditions
|
8405 |
|
|
+ LDILO.LT 1,%2
|
8406 |
|
|
+ XOR.LT -1,%L0
|
8407 |
|
|
+ XOR.LT -1,%H0
|
8408 |
|
|
+ ADD %2,%L0
|
8409 |
122 |
dgisselq |
+ ADD.C 1,%H0"
|
8410 |
102 |
dgisselq |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8411 |
|
|
+(define_insn "one_cmpldi2"
|
8412 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8413 |
|
|
+ (not:DI (match_operand:DI 1 "register_operand" "0")))
|
8414 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8415 |
102 |
dgisselq |
+ ]
|
8416 |
|
|
+ ""
|
8417 |
|
|
+ "XOR -1,%L0\n\tXOR\t-1,%H0"
|
8418 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8419 |
|
|
+(define_insn "umindi3"
|
8420 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8421 |
|
|
+ (umin:DI (match_operand:DI 1 "register_operand" "%0")
|
8422 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
8423 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8424 |
102 |
dgisselq |
+ ]
|
8425 |
|
|
+ ""
|
8426 |
|
|
+ "CMP %H0,%H2
|
8427 |
|
|
+ CMP.Z %L0,%L2
|
8428 |
|
|
+ MOV.C %H2,%H0
|
8429 |
|
|
+ MOV.C %L2,%L0"
|
8430 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8431 |
|
|
+(define_insn "umaxdi3"
|
8432 |
|
|
+ [(set (match_operand:DI 0 "register_operand" "=r")
|
8433 |
|
|
+ (umax:DI (match_operand:DI 1 "register_operand" "%0")
|
8434 |
|
|
+ (match_operand:DI 2 "register_operand" "r")))
|
8435 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8436 |
102 |
dgisselq |
+ ]
|
8437 |
|
|
+ ""
|
8438 |
|
|
+ "CMP %H2,%H0
|
8439 |
|
|
+ CMP.Z %L2,%L0
|
8440 |
|
|
+ MOV.C %H2,%H0
|
8441 |
|
|
+ MOV.C %L2,%L0"
|
8442 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8443 |
|
|
+(define_insn "popcountdi2"
|
8444 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
8445 |
122 |
dgisselq |
+ (popcount:SI (match_operand:DI 1 "register_operand" "r")))
|
8446 |
102 |
dgisselq |
+ (clobber (match_scratch:SI 2 "=r"))
|
8447 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))
|
8448 |
102 |
dgisselq |
+ ]
|
8449 |
|
|
+ ""
|
8450 |
|
|
+ "POPC %L1,%0
|
8451 |
|
|
+ POPC %H1,%2
|
8452 |
|
|
+ ADD %2,%0"
|
8453 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
|
8454 |
|
|
+(define_expand "paritydi2"
|
8455 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
8456 |
|
|
+ (popcount (match_operand:DI 1 "register_operand" "r")))
|
8457 |
|
|
+ (set (match_dup 0) (and:SI (match_dup 0) (const_int -2)))
|
8458 |
|
|
+ ])
|
8459 |
117 |
dgisselq |
+;(define_insn "extendsidi2"
|
8460 |
|
|
+; [(set (match_operand:DI 0 "register_operand" "=r")
|
8461 |
|
|
+; (sign_extend:DI (match_operand:SI 0 "register_operand" "r")))]
|
8462 |
|
|
+; ""
|
8463 |
|
|
+; "TEST\t%1\nMOV\t%1,%L0\nCLR\t%L1\nLDI.LT\t-1,%L1"
|
8464 |
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8465 |
|
|
+;(define_insn "mulsidi3"
|
8466 |
|
|
+; [(set (match_operand:DI 0 "register_operand" "=r")
|
8467 |
|
|
+; (mult:SI (match_operand:SI 1 "register_operand" "%r")
|
8468 |
|
|
+; (match_operand:SI 2 "register_operand" "r")))
|
8469 |
|
|
+; (clobber (match_scratch:SI 3 "=r"))]
|
8470 |
|
|
+; ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
|
8471 |
|
|
+; ""
|
8472 |
|
|
+; "MOV %1,%L0
|
8473 |
|
|
+; MPYS %2,%L0 ; L0 = R2 * R1
|
8474 |
|
|
+; MOV %1,%3 ; R3 = R1
|
8475 |
|
|
+; ROL 16,%3 ; R3 = (R1 <<< 16)
|
8476 |
|
|
+; MPYS %2,%3 ; R3 = (R1 <<< 16) * R2
|
8477 |
|
|
+; ROL 16,%3 ; R3 = upper bits of (R1<<<16)*R2
|
8478 |
|
|
+; AND 0x0ffff,%3
|
8479 |
|
|
+; ADD %3,%L0 ; L0 = L0 + R3 = L0 + (R1>>16)*R2
|
8480 |
|
|
+; MOV %2,%3
|
8481 |
|
|
+; ROL 16,%3
|
8482 |
|
|
+; MPYS %1,%3
|
8483 |
|
|
+; ROL 16,%3
|
8484 |
|
|
+; AND 0x0ffff,%3
|
8485 |
|
|
+; ADD %3,%0"
|
8486 |
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8487 |
|
|
+
|
8488 |
102 |
dgisselq |
+;
|
8489 |
|
|
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
|
8490 |
|
|
+; mult:di, div:di, divu:di
|
8491 |
|
|
+;
|
8492 |
|
|
+;
|
8493 |
|
|
+;
|
8494 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8495 |
|
|
+;;
|
8496 |
|
|
+;; Conditional arithmetic instructions
|
8497 |
|
|
+;;
|
8498 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8499 |
|
|
+;
|
8500 |
|
|
+;
|
8501 |
|
|
+;
|
8502 |
|
|
+;
|
8503 |
|
|
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3
|
8504 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 2 "register_operand" "r")
|
8505 |
|
|
+ (match_operand:ZI 3 "zip_opb_operand_p" "rO")))
|
8506 |
102 |
dgisselq |
+ (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
|
8507 |
|
|
+ (match_operator 1 "ordered_comparison_operator"
|
8508 |
122 |
dgisselq |
+ [(reg:CC CC_REG) (const_int 0)])
|
8509 |
102 |
dgisselq |
+ (const_int 1) (const_int 0)))]
|
8510 |
|
|
+ ""
|
8511 |
|
|
+ )
|
8512 |
|
|
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
|
8513 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
8514 |
|
|
+ (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
|
8515 |
122 |
dgisselq |
+ [(match_operand:DI 2 "register_operand" "r")
|
8516 |
|
|
+ (match_operand:DI 3 "register_operand" "r")])
|
8517 |
|
|
+ (const_int 1) (const_int 0)))
|
8518 |
|
|
+ (clobber (reg:CC CC_REG))]
|
8519 |
102 |
dgisselq |
+ ""
|
8520 |
|
|
+ {
|
8521 |
|
|
+ switch(GET_CODE(operands[1])) {
|
8522 |
|
|
+ case EQ: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
|
8523 |
|
|
+ case NE: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
|
8524 |
|
|
+ case LTU: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
|
8525 |
|
|
+ case LEU: return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
|
8526 |
|
|
+ case GTU: return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
|
8527 |
|
|
+ case GEU: return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
|
8528 |
|
|
+ default:
|
8529 |
|
|
+ gcc_unreachable();
|
8530 |
|
|
+ }
|
8531 |
|
|
+ }
|
8532 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8533 |
|
|
+;
|
8534 |
|
|
+;
|
8535 |
|
|
+;
|
8536 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8537 |
|
|
+;;
|
8538 |
|
|
+;; Comparison instructions, both compare and test
|
8539 |
|
|
+;;
|
8540 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8541 |
|
|
+;
|
8542 |
|
|
+;
|
8543 |
|
|
+;
|
8544 |
|
|
+;; This will only work so well, since the direction of the compare is
|
8545 |
|
|
+;; important in unsigned compares.
|
8546 |
|
|
+;;
|
8547 |
122 |
dgisselq |
+(define_expand "cmp<mode>"
|
8548 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC
|
8549 |
|
|
+ (match_operand:ZI 0 "register_operand" "r")
|
8550 |
|
|
+ (match_operand:ZI 1 "nonmemory_operand" "")))]
|
8551 |
102 |
dgisselq |
+ ""
|
8552 |
122 |
dgisselq |
+ {
|
8553 |
|
|
+ if (!zip_opb_operand_p(operands[1],SImode)) {
|
8554 |
|
|
+ if (can_create_pseudo_p()) {
|
8555 |
|
|
+ //; fprintf(stderr, "Generating pseudo register for compare\n");
|
8556 |
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
8557 |
|
|
+ emit_insn(gen_movsi(tmp,operands[1]));
|
8558 |
|
|
+ operands[1] = tmp;
|
8559 |
|
|
+ } else FAIL;
|
8560 |
|
|
+ }
|
8561 |
|
|
+ })
|
8562 |
|
|
+(define_insn "cmp<mode>_reg"
|
8563 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC
|
8564 |
|
|
+ (match_operand:ZI 0 "register_operand" "r")
|
8565 |
|
|
+ (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")))]
|
8566 |
|
|
+ ""
|
8567 |
102 |
dgisselq |
+ "CMP\t%1,%0"
|
8568 |
|
|
+ [(set_attr "ccresult" "set")])
|
8569 |
|
|
+(define_insn "cmp<mode>_off"
|
8570 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
8571 |
|
|
+ (match_operand:ZI 0 "register_operand" "r")
|
8572 |
146 |
dgisselq |
+ (plus:ZI (match_operand:ZI 1 "register_operand" "r")
|
8573 |
122 |
dgisselq |
+ (match_operand 2 "zip_opb_immv_p" "N"))))]
|
8574 |
102 |
dgisselq |
+ ""
|
8575 |
|
|
+ "CMP\t%2+%1,%0"
|
8576 |
|
|
+ [(set_attr "ccresult" "set")])
|
8577 |
|
|
+(define_insn "test<mode>"
|
8578 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_operand:ZI 0 "register_operand" "r")
|
8579 |
|
|
+ (match_operand:ZI 1 "zip_opb_single_operand_p" "rO"))
|
8580 |
102 |
dgisselq |
+ (const_int 0)))]
|
8581 |
|
|
+ ""
|
8582 |
|
|
+ "TEST %1,%0"
|
8583 |
|
|
+ [(set_attr "ccresult" "set")])
|
8584 |
|
|
+(define_insn "test<mode>_off"
|
8585 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
8586 |
|
|
+ (and:ZI (match_operand:ZI 0 "register_operand" "r")
|
8587 |
|
|
+ (plus:ZI
|
8588 |
|
|
+ (match_operand:ZI 1 "register_operand" "r")
|
8589 |
|
|
+ (match_operand:ZI 2 "zip_opb_immv_p" "N")))
|
8590 |
|
|
+ (const_int 0)))]
|
8591 |
102 |
dgisselq |
+ ""
|
8592 |
|
|
+ "TEST %2+%1,%0"
|
8593 |
|
|
+ [(set_attr "ccresult" "set")])
|
8594 |
|
|
+(define_insn "nop"
|
8595 |
|
|
+ [(const_int 0)]
|
8596 |
|
|
+ ""
|
8597 |
|
|
+ "NOOP"
|
8598 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
8599 |
|
|
+;
|
8600 |
|
|
+;
|
8601 |
|
|
+;
|
8602 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8603 |
|
|
+;;
|
8604 |
|
|
+;; Conditional execution predicates
|
8605 |
|
|
+;;
|
8606 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8607 |
|
|
+;
|
8608 |
|
|
+; Sadly, these aren't complete like they should be. Although these are all of
|
8609 |
|
|
+; the conditional execution prefixes that the Zip CPU supports, GCC looks for
|
8610 |
|
|
+; other conditions then these. That is, (cond_exec ...) is not as well
|
8611 |
|
|
+; recognized as (if_then_else ...). So we have to duplicate things to support
|
8612 |
|
|
+; both methods.
|
8613 |
|
|
+;
|
8614 |
|
|
+(define_cond_exec
|
8615 |
122 |
dgisselq |
+ [(ne (reg:CC CC_REG) (const_int 0))]
|
8616 |
102 |
dgisselq |
+ ""
|
8617 |
|
|
+ "(NZ)"
|
8618 |
|
|
+ [(set_attr "conditional" "yes")])
|
8619 |
|
|
+(define_cond_exec
|
8620 |
122 |
dgisselq |
+ [(lt (reg:CC CC_REG) (const_int 0))]
|
8621 |
102 |
dgisselq |
+ ""
|
8622 |
|
|
+ "(LT)"
|
8623 |
|
|
+ [(set_attr "conditional" "yes")])
|
8624 |
|
|
+(define_cond_exec
|
8625 |
122 |
dgisselq |
+ [(eq (reg:CC CC_REG) (const_int 0))]
|
8626 |
102 |
dgisselq |
+ ""
|
8627 |
|
|
+ "(Z)"
|
8628 |
|
|
+ [(set_attr "conditional" "yes")])
|
8629 |
|
|
+(define_cond_exec
|
8630 |
122 |
dgisselq |
+ [(gt (reg:CC CC_REG) (const_int 0))]
|
8631 |
102 |
dgisselq |
+ ""
|
8632 |
|
|
+ "(GT)"
|
8633 |
|
|
+ [(set_attr "conditional" "yes")])
|
8634 |
|
|
+(define_cond_exec
|
8635 |
122 |
dgisselq |
+ [(ge (reg:CC CC_REG) (const_int 0))]
|
8636 |
102 |
dgisselq |
+ ""
|
8637 |
|
|
+ "(GE)"
|
8638 |
|
|
+ [(set_attr "conditional" "yes")])
|
8639 |
|
|
+(define_cond_exec
|
8640 |
122 |
dgisselq |
+ [(ltu (reg:CC CC_REG) (const_int 0))]
|
8641 |
102 |
dgisselq |
+ ""
|
8642 |
|
|
+ "(C)"
|
8643 |
|
|
+ [(set_attr "conditional" "yes")])
|
8644 |
|
|
+;
|
8645 |
|
|
+;
|
8646 |
|
|
+;
|
8647 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8648 |
|
|
+;;
|
8649 |
|
|
+;; Conditional move instructions, since these won't accept conditional
|
8650 |
|
|
+;; execution RTL
|
8651 |
|
|
+;;
|
8652 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8653 |
|
|
+;
|
8654 |
|
|
+; // Look for #define HAVE_conditional_move to understand how these might be
|
8655 |
|
|
+; // used.
|
8656 |
|
|
+;
|
8657 |
|
|
+(define_insn "set_zero_or_one<mode>"
|
8658 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
|
8659 |
|
|
+ (match_operator 1 "ordered_comparison_operator"
|
8660 |
122 |
dgisselq |
+ [(reg:CC CC_REG) (const_int 0)])
|
8661 |
102 |
dgisselq |
+ (const_int 1) (const_int 0)))]
|
8662 |
|
|
+ ""
|
8663 |
|
|
+ { return (zip_set_zero_or_one(operands[1], operands[0]));
|
8664 |
|
|
+ }
|
8665 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8666 |
127 |
dgisselq |
+(define_expand "mov<mode>cc"
|
8667 |
102 |
dgisselq |
+ [(set (match_operand:ZI 0 "register_operand" "=r")
|
8668 |
127 |
dgisselq |
+ (if_then_else:ZI (match_operand 1 "comparison_operator")
|
8669 |
102 |
dgisselq |
+ (match_operand:ZI 2 "general_operand" "rio")
|
8670 |
|
|
+ (match_operand:ZI 3 "nonmemory_operand" "rio")))]
|
8671 |
|
|
+ ""
|
8672 |
|
|
+ {
|
8673 |
142 |
dgisselq |
+ if (zip_expand_movsicc(operands[0], operands[1], operands[2], operands[3]))
|
8674 |
|
|
+ DONE;
|
8675 |
|
|
+ else
|
8676 |
|
|
+ FAIL;
|
8677 |
127 |
dgisselq |
+ })
|
8678 |
|
|
+(define_insn_and_split "movsicc_bare"
|
8679 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
8680 |
|
|
+ (if_then_else (match_operator 1 "ordered_comparison_operator"
|
8681 |
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
8682 |
|
|
+ (match_operand:SI 2 "general_operand" "rio")
|
8683 |
|
|
+ (match_operand:SI 3 "register_operand" "0")))]
|
8684 |
|
|
+ "(zip_supported_condition(GET_CODE(operands[1])))"
|
8685 |
|
|
+ "#"
|
8686 |
|
|
+ "(reload_completed)"
|
8687 |
|
|
+ [(cond_exec (match_operator 1 "ordered_comparison_operator"
|
8688 |
|
|
+ [(reg:CC CC_REG) (const_int 0)])
|
8689 |
|
|
+ (set (match_dup 0) (match_dup 2)))]
|
8690 |
|
|
+ "" [(set_attr "predicable" "no")])
|
8691 |
102 |
dgisselq |
+(define_insn "add<mode>cc"
|
8692 |
|
|
+ [(set (match_operand:ZI 0 "register_operand" "=r,r")
|
8693 |
|
|
+ (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
|
8694 |
122 |
dgisselq |
+ [(reg:CC CC_REG) (const_int 0)])
|
8695 |
102 |
dgisselq |
+ (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
|
8696 |
|
|
+ (match_operand:ZI 3 "nonmemory_operand" "rO,M"))
|
8697 |
|
|
+ (match_dup 0)))]
|
8698 |
|
|
+ ""
|
8699 |
|
|
+ {
|
8700 |
|
|
+ return zip_addsicc(operands[0], operands[1], operands[2], operands[3]);
|
8701 |
|
|
+ }
|
8702 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8703 |
|
|
+;
|
8704 |
|
|
+;
|
8705 |
|
|
+;
|
8706 |
|
|
+; While an interesting approach, the following suffers from problems when the
|
8707 |
|
|
+; move amount is constant. At anything less than four, moves should not require
|
8708 |
|
|
+; the movmemSI instruction. At anything greater, if constant, the initial tests
|
8709 |
|
|
+; are not required and should result in a hardcoded result. Practically,
|
8710 |
|
|
+; though, this should really be a define_expand instruction, calling on the
|
8711 |
127 |
dgisselq |
+; RTX's of all the respective subinstructions found below. Or, perhaps, it is
|
8712 |
|
|
+; better as a subroutine?
|
8713 |
102 |
dgisselq |
+;
|
8714 |
|
|
+;(define_insn "movmemSI"
|
8715 |
|
|
+; [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst
|
8716 |
|
|
+; (mem:BLK (match_operand 1 "register_operand" "+r")));Src
|
8717 |
|
|
+; (use (match_operand:SI 2 "register_operand" "+r"))]); Length
|
8718 |
|
|
+; (match_operand 3 "" "") ;Alignment
|
8719 |
|
|
+; (clobber (match_scratch:SI 4 "=r"))
|
8720 |
|
|
+; (clobber (match_scratch:SI 5 "=r"))
|
8721 |
|
|
+; (clobber (match_scratch:SI 6 "=r"))
|
8722 |
|
|
+; (clobber (match_scratch:SI 7 "=r"))]
|
8723 |
|
|
+; ""
|
8724 |
|
|
+; "TEST\t1,%2
|
8725 |
|
|
+; LOD.NZ\t%1,%4
|
8726 |
|
|
+; STO.NZ\t%4,%0
|
8727 |
|
|
+; ADD.NZ\t1,%0
|
8728 |
|
|
+; ADD.NZ\t1,%1
|
8729 |
|
|
+; TEST\t2,%2
|
8730 |
|
|
+; LOD.NZ\t%1,%4
|
8731 |
|
|
+; LOD.NZ\t1(%1),%5
|
8732 |
|
|
+; STO.NZ\t%4,(%0)
|
8733 |
|
|
+; STO.NZ\t%4,1(%0)
|
8734 |
|
|
+; ADD.NZ\t2,%0
|
8735 |
|
|
+; ADD.NZ\t2,%1
|
8736 |
|
|
+; AND\t-4,%2
|
8737 |
|
|
+; BZ\t.Lskp%=\n.Ltop%=:
|
8738 |
|
|
+; LOD\t(%1),%4
|
8739 |
|
|
+; LOD\t1(%1),%5
|
8740 |
|
|
+; LOD\t2(%1,%6
|
8741 |
|
|
+; LOD\t3(%1),%7
|
8742 |
|
|
+; STO\t%4,(%1)
|
8743 |
|
|
+; STO\t%5,1(%1)
|
8744 |
|
|
+; STO\t%6,2(%1)
|
8745 |
|
|
+; STO\t%7,3(%1)
|
8746 |
|
|
+; SUB\t4,%2
|
8747 |
|
|
+; BZ\t%.Lskp%=
|
8748 |
|
|
+; BRA\t.Ltop%=\n.Lskp%=:"
|
8749 |
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8750 |
|
|
+;(define_insn "setmemsi"
|
8751 |
|
|
+; [(parallel
|
8752 |
|
|
+; [(set (mem:BLK
|
8753 |
|
|
+; (match_operand 0 "register_operand" "+r")); Destination
|
8754 |
|
|
+; (match_operand:SI 2 "register_operand" "r")) ; Source
|
8755 |
|
|
+; (use (match_operand:SI 1 "register_operand" "+r"))]) ; Length
|
8756 |
|
|
+; (match_operand 3 "" "")]
|
8757 |
|
|
+; ""
|
8758 |
|
|
+; "TEST\t1,%1
|
8759 |
|
|
+; STO.NZ\t%2,(%0)
|
8760 |
|
|
+; ADD.NZ\t1,%0
|
8761 |
|
|
+; TEST\t2,%1
|
8762 |
|
|
+; STO.NZ\t%2,(%0)
|
8763 |
|
|
+; STO.NZ\t%2,1(%0)
|
8764 |
|
|
+; ADD.NZ\t2,%0
|
8765 |
|
|
+; AND\t-4,%1
|
8766 |
|
|
+; BZ\t.Lskp%=\n.Ltop%=:\n
|
8767 |
|
|
+; STO\t%2,(%0)
|
8768 |
|
|
+; STO\t%2,1(%0)
|
8769 |
|
|
+; STO\t%2,2(%0)
|
8770 |
|
|
+; STO\t%2,3(%0)
|
8771 |
|
|
+; SUB\t%4,%0
|
8772 |
|
|
+; BZ\t.Lskp%=
|
8773 |
|
|
+; BRA\t.Ltop%=\n.Lskp%=:"
|
8774 |
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
8775 |
|
|
+;;
|
8776 |
|
|
+;
|
8777 |
|
|
+;
|
8778 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8779 |
|
|
+;;
|
8780 |
|
|
+;; Control flow instructions
|
8781 |
|
|
+;;
|
8782 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
8783 |
|
|
+;
|
8784 |
|
|
+;
|
8785 |
|
|
+;
|
8786 |
|
|
+(define_expand "jump"
|
8787 |
|
|
+ [(set (pc)
|
8788 |
|
|
+ (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro"
|
8789 |
127 |
dgisselq |
+(define_insn "jump_const"
|
8790 |
|
|
+ [(set (pc)
|
8791 |
102 |
dgisselq |
+ (match_operand:SI 0 "zip_const_address_operand_p" ""))]
|
8792 |
|
|
+ ""
|
8793 |
|
|
+ "BRA %0"
|
8794 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8795 |
|
|
+(define_insn "jump_label" ; Must be modeless, VOIDmode, not SI or any othr
|
8796 |
|
|
+ [(set (pc) ; Otherwise it won't accept jumps to labels
|
8797 |
|
|
+ (label_ref (match_operand 0 "" "")))]
|
8798 |
|
|
+ ""
|
8799 |
|
|
+ "BRA %0"
|
8800 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
8801 |
|
|
+;
|
8802 |
|
|
+; This is really the same thing as an indirect jump ... the big difference
|
8803 |
|
|
+; is that the zip_address_operand_p checks for an "N" type condition, not an
|
8804 |
|
|
+; "M" type condition ... a bug, but one that works for now. (The assembler
|
8805 |
|
|
+; should be able to catch and except on it ...)
|
8806 |
|
|
+;
|
8807 |
|
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
8808 |
|
|
+(define_insn "jump_variable"
|
8809 |
|
|
+ [(set (pc)
|
8810 |
|
|
+ (match_operand:SI 0 "zip_address_operand_p" ""))]
|
8811 |
|
|
+ ""
|
8812 |
|
|
+ "JMP %0"
|
8813 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
8814 |
|
|
+;
|
8815 |
|
|
+; Indirect jumps ... both to registers, and registers plus offsets
|
8816 |
|
|
+;
|
8817 |
|
|
+(define_insn "indirect_jump"
|
8818 |
|
|
+ [(set (pc)
|
8819 |
|
|
+ (match_operand:SI 0 "register_operand" "r"))]
|
8820 |
|
|
+ ""
|
8821 |
|
|
+ "JMP %0"
|
8822 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
8823 |
|
|
+(define_insn "indirect_jump_mem"
|
8824 |
|
|
+ [(set (pc) (match_operand:SI 0 "zip_memory_operand_p" "o"))]
|
8825 |
|
|
+ ""
|
8826 |
|
|
+ "LOD %0,PC"
|
8827 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
8828 |
|
|
+(define_insn "indirect_jump_off"
|
8829 |
|
|
+ [(set (pc)
|
8830 |
|
|
+ (plus:SI (match_operand:SI 0 "register_operand" "r")
|
8831 |
|
|
+ (match_operand:SI 1 "const_int_operand" "M")))]
|
8832 |
|
|
+ ""
|
8833 |
|
|
+ "JMP %1(%0)"
|
8834 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
8835 |
|
|
+;;
|
8836 |
|
|
+; cbranchsi4
|
8837 |
|
|
+;; Op 0 = the comparison operator (le,lt,eq,ne,gt,ge,and usgn ltu,geu,etc.)
|
8838 |
|
|
+;; Op 1&2 the operands of the compare instruction
|
8839 |
|
|
+;; Op 3 is the jump label
|
8840 |
|
|
+;;
|
8841 |
|
|
+;;
|
8842 |
|
|
+;; #warning Need to adjust this so that the "LT" code doesnt get generated ...
|
8843 |
|
|
+;;
|
8844 |
|
|
+(define_expand "cbranch<mode>4"
|
8845 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
|
8846 |
|
|
+ (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
|
8847 |
102 |
dgisselq |
+ (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
|
8848 |
122 |
dgisselq |
+ [(reg:CC CC_REG) (const_int 0)])
|
8849 |
102 |
dgisselq |
+ (label_ref (match_operand 3 "" ""))
|
8850 |
|
|
+ (pc)))]
|
8851 |
|
|
+ ""
|
8852 |
|
|
+ {
|
8853 |
125 |
dgisselq |
+ if (true) {
|
8854 |
117 |
dgisselq |
+ extern void zip_debug_rtx_pfx(const char *, const_rtx);
|
8855 |
102 |
dgisselq |
+ //; Two branches give us no end of difficulty when implementing.
|
8856 |
|
|
+ //; Let's check for these two branch codes, and swap the
|
8857 |
|
|
+ //; comparison to simplify them.
|
8858 |
122 |
dgisselq |
+ //; fprintf(stderr, "CBRANCH\n");
|
8859 |
|
|
+ //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
|
8860 |
|
|
+ //; zip_debug_rtx_pfx("- A : ", operands[1]);
|
8861 |
|
|
+ //; zip_debug_rtx_pfx("- B : ", operands[2]);
|
8862 |
|
|
+ //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
|
8863 |
117 |
dgisselq |
+ //; Can we do better if we reverse some compares?
|
8864 |
102 |
dgisselq |
+ if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) {
|
8865 |
122 |
dgisselq |
+ //; fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n");
|
8866 |
|
|
+ emit_insn(gen_cmpsi(operands[2], operands[1]));
|
8867 |
102 |
dgisselq |
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
8868 |
|
|
+ DONE;
|
8869 |
|
|
+ } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
|
8870 |
122 |
dgisselq |
+ //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
|
8871 |
|
|
+ emit_insn(gen_cmpsi_off(operands[2], operands[1],
|
8872 |
|
|
+ GEN_INT(1)));
|
8873 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
8874 |
102 |
dgisselq |
+ DONE;
|
8875 |
117 |
dgisselq |
+ } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
|
8876 |
122 |
dgisselq |
+ //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
|
8877 |
117 |
dgisselq |
+ //; Swap operands, turn into a GTE compare
|
8878 |
122 |
dgisselq |
+ emit_insn(gen_cmpsi(operands[2], operands[1]));
|
8879 |
117 |
dgisselq |
+ emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
|
8880 |
|
|
+ DONE;
|
8881 |
102 |
dgisselq |
+ } // ; Otherwise ... just handle the branch normally
|
8882 |
|
|
+
|
8883 |
|
|
+ //; Except ... we can do better for some instructions, such as
|
8884 |
|
|
+ //; LE. While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
|
8885 |
|
|
+ //; would be difficult to explain to users why MIN_INT didn't
|
8886 |
|
|
+ //; compare properly. Hence we only adjust constant integers.
|
8887 |
|
|
+ //;
|
8888 |
122 |
dgisselq |
+ if (GET_CODE(operands[0])==LE) {
|
8889 |
|
|
+ if ((CONST_INT_P(operands[2]))
|
8890 |
117 |
dgisselq |
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
8891 |
122 |
dgisselq |
+ //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
|
8892 |
|
|
+ emit_insn(gen_cmpsi(operands[1],
|
8893 |
|
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
8894 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
8895 |
|
|
+ DONE;
|
8896 |
|
|
+ //; Now for the controversial ones--where we add one
|
8897 |
|
|
+ //; when it may or may not be permissable. For now, we
|
8898 |
|
|
+ //; just do it anyway and postpone the philosophical
|
8899 |
|
|
+ //; discussion for later.
|
8900 |
|
|
+ } else if (REG_P(operands[2])) {
|
8901 |
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
8902 |
|
|
+ operands[2],GEN_INT(1)));
|
8903 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
8904 |
|
|
+ DONE;
|
8905 |
|
|
+ } else if ((GET_CODE(operands[2])==PLUS)
|
8906 |
|
|
+ &&(REG_P(XEXP(operands[2],0)))
|
8907 |
|
|
+ &&(CONST_INT_P(XEXP(operands[2],1)))
|
8908 |
|
|
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
|
8909 |
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
8910 |
|
|
+ XEXP(operands[2],0),
|
8911 |
|
|
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
|
8912 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
|
8913 |
|
|
+ DONE;
|
8914 |
|
|
+ }
|
8915 |
|
|
+ } else if (GET_CODE(operands[0])==LEU) {
|
8916 |
|
|
+ if ((CONST_INT_P(operands[2]))
|
8917 |
102 |
dgisselq |
+ &&(INTVAL(operands[2])<(1<<17)-2)) {
|
8918 |
122 |
dgisselq |
+ //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
|
8919 |
|
|
+ emit_insn(gen_cmpsi(operands[1],
|
8920 |
|
|
+ GEN_INT(INTVAL(operands[2])+1)));
|
8921 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
8922 |
|
|
+ DONE;
|
8923 |
|
|
+ //; Now for the controversial ones--this time having
|
8924 |
|
|
+ //; to do with unsigned compares.
|
8925 |
|
|
+ } else if (REG_P(operands[2])) {
|
8926 |
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
8927 |
|
|
+ operands[2],GEN_INT(1)));
|
8928 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
8929 |
|
|
+ DONE;
|
8930 |
|
|
+ } else if ((GET_CODE(operands[2])==PLUS)
|
8931 |
|
|
+ &&(REG_P(XEXP(operands[2],0)))
|
8932 |
|
|
+ &&(CONST_INT_P(XEXP(operands[2],1)))
|
8933 |
|
|
+ &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
|
8934 |
|
|
+ emit_insn(gen_cmpsi_off(operands[1],
|
8935 |
|
|
+ XEXP(operands[2],0),
|
8936 |
|
|
+ GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
|
8937 |
|
|
+ emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
|
8938 |
|
|
+ DONE;
|
8939 |
|
|
+ }
|
8940 |
124 |
dgisselq |
+ }}
|
8941 |
102 |
dgisselq |
+ })
|
8942 |
|
|
+(define_insn "cbranch_jmp_eq"
|
8943 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
|
8944 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
8945 |
|
|
+ (pc)))]
|
8946 |
|
|
+ ""
|
8947 |
|
|
+ "BZ\t%0"
|
8948 |
|
|
+ [(set_attr "predicable" "no")
|
8949 |
|
|
+ (set_attr "conditional" "yes")
|
8950 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
8951 |
|
|
+(define_insn "cbranch_jmp_neq"
|
8952 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
|
8953 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
8954 |
|
|
+ (pc)))]
|
8955 |
|
|
+ ""
|
8956 |
|
|
+ "BNZ\t%0"
|
8957 |
|
|
+ [(set_attr "predicable" "no")
|
8958 |
|
|
+ (set_attr "conditional" "yes")
|
8959 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
8960 |
|
|
+(define_insn "cbranch_jmp_lt"
|
8961 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
8962 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
8963 |
|
|
+ (pc)))]
|
8964 |
|
|
+ ""
|
8965 |
|
|
+ "BLT\t%0"
|
8966 |
|
|
+ [(set_attr "predicable" "no")
|
8967 |
|
|
+ (set_attr "conditional" "yes")
|
8968 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
8969 |
|
|
+(define_insn "cbranch_jmp_le"
|
8970 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
|
8971 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
8972 |
|
|
+ (pc)))]
|
8973 |
|
|
+ ""
|
8974 |
|
|
+ "BLT\t%0
|
8975 |
|
|
+ BZ\t%0"
|
8976 |
|
|
+ [(set_attr "predicable" "no")
|
8977 |
|
|
+ (set_attr "conditional" "yes")
|
8978 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
8979 |
|
|
+(define_insn "cbranch_jmp_gt"
|
8980 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
|
8981 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
8982 |
|
|
+ (pc)))]
|
8983 |
|
|
+ ""
|
8984 |
|
|
+ "BGT\t%0"
|
8985 |
|
|
+ [(set_attr "predicable" "no")
|
8986 |
|
|
+ (set_attr "conditional" "yes")
|
8987 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
8988 |
|
|
+(define_insn "cbranch_jmp_ge"
|
8989 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
8990 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
8991 |
|
|
+ (pc)))]
|
8992 |
|
|
+ ""
|
8993 |
|
|
+ "BGE\t%0"
|
8994 |
|
|
+ [(set_attr "predicable" "no")
|
8995 |
|
|
+ (set_attr "conditional" "yes")
|
8996 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
8997 |
|
|
+(define_insn "cbranch_jmp_ltu"
|
8998 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
8999 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
9000 |
|
|
+ (pc)))]
|
9001 |
|
|
+ ""
|
9002 |
|
|
+ "BC\t%0"
|
9003 |
|
|
+ [(set_attr "predicable" "no")
|
9004 |
|
|
+ (set_attr "conditional" "yes")
|
9005 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
9006 |
|
|
+(define_insn "cbranch_jmp_gtu"
|
9007 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
9008 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
9009 |
122 |
dgisselq |
+ (pc)))
|
9010 |
|
|
+ ;(clobber (reg:CC CC_REG))
|
9011 |
|
|
+ ]
|
9012 |
102 |
dgisselq |
+ "" ; Flip the condition, and then we can jump
|
9013 |
127 |
dgisselq |
+ "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
|
9014 |
102 |
dgisselq |
+ [(set_attr "predicable" "no")
|
9015 |
|
|
+ (set_attr "conditional" "yes")
|
9016 |
|
|
+ (set_attr "ccresult" "unknown")])
|
9017 |
|
|
+(define_insn "cbranch_jmp_leu"
|
9018 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
9019 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
9020 |
|
|
+ (pc)))]
|
9021 |
|
|
+ "" ; Need to check for both LTU (i.e. C) and Z
|
9022 |
|
|
+ "BC\t%0
|
9023 |
|
|
+ BZ\t%0"
|
9024 |
|
|
+ [(set_attr "predicable" "no")
|
9025 |
|
|
+ (set_attr "conditional" "yes")
|
9026 |
|
|
+ (set_attr "ccresult" "unchanged")])
|
9027 |
|
|
+(define_insn "cbranch_jmp_geu"
|
9028 |
122 |
dgisselq |
+ [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
9029 |
102 |
dgisselq |
+ (label_ref (match_operand 0 "" ""))
|
9030 |
122 |
dgisselq |
+ (pc)))
|
9031 |
|
|
+ ;(clobber (reg:CC CC_REG))
|
9032 |
|
|
+ ]
|
9033 |
127 |
dgisselq |
+ ""
|
9034 |
|
|
+ "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
|
9035 |
102 |
dgisselq |
+ [(set_attr "predicable" "no")
|
9036 |
|
|
+ (set_attr "conditional" "yes")
|
9037 |
|
|
+ (set_attr "ccresult" "unknown")])
|
9038 |
|
|
+(define_insn "cbranchdi4"
|
9039 |
|
|
+ [(set (pc) (if_then_else
|
9040 |
|
|
+ (match_operator 0 "ordered_comparison_operator"
|
9041 |
|
|
+ [(match_operand:DI 1 "register_operand" "r")
|
9042 |
122 |
dgisselq |
+ (match_operand:DI 2 "register_operand" "r")])
|
9043 |
102 |
dgisselq |
+ (label_ref (match_operand 3 "" ""))
|
9044 |
|
|
+ (pc)))
|
9045 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
9046 |
102 |
dgisselq |
+ ""
|
9047 |
|
|
+ {
|
9048 |
|
|
+ switch(GET_CODE(operands[0])) {
|
9049 |
|
|
+ case EQ:
|
9050 |
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
|
9051 |
|
|
+ case NE:
|
9052 |
|
|
+ return "CMP\t%H2,%H1\n\tCMP.NZ\t%L2,%L1\n\tBNZ\t%3";
|
9053 |
|
|
+ case LE:
|
9054 |
|
|
+ return "CMP\t%H2,%H1\n\tBLT\t%3\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
|
9055 |
|
|
+ case GT:
|
9056 |
|
|
+ return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
|
9057 |
|
|
+ case LT:
|
9058 |
|
|
+ return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n.Ldi%=:";
|
9059 |
|
|
+ case GE:
|
9060 |
|
|
+ return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\nBZ\t%3\n.Ldi%=:";
|
9061 |
|
|
+ case LTU:
|
9062 |
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n";
|
9063 |
|
|
+ case LEU:
|
9064 |
|
|
+ return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
|
9065 |
|
|
+ case GTU:
|
9066 |
|
|
+ return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\n";
|
9067 |
|
|
+ case GEU:
|
9068 |
|
|
+ return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\nBZ\t%3";
|
9069 |
|
|
+ default:
|
9070 |
|
|
+ gcc_unreachable();
|
9071 |
|
|
+ }
|
9072 |
|
|
+ }
|
9073 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9074 |
|
|
+;
|
9075 |
|
|
+;
|
9076 |
|
|
+;
|
9077 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9078 |
|
|
+;;
|
9079 |
|
|
+;; Subroutine call
|
9080 |
|
|
+;;
|
9081 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9082 |
|
|
+;
|
9083 |
|
|
+;
|
9084 |
|
|
+; There are two types of calls: "call" and "call_value".
|
9085 |
|
|
+;
|
9086 |
|
|
+; Each of these types of calls are then expanded into one of:
|
9087 |
|
|
+;
|
9088 |
|
|
+; _const - A call to a constant address, such as a symbol
|
9089 |
|
|
+; reference or a fixed location
|
9090 |
|
|
+;
|
9091 |
|
|
+; _label - This should be the same as _const, except that for
|
9092 |
|
|
+; some reason the RTL and matching rules are separate.
|
9093 |
|
|
+; Hence we have a separate rule for this.
|
9094 |
|
|
+;
|
9095 |
|
|
+; _mem - The memory address we wish to jump to is stored in
|
9096 |
|
|
+; memory somewhere, and we have only a pointer. In this
|
9097 |
|
|
+; case, we load that pointer straight to the PC and go.
|
9098 |
|
|
+;
|
9099 |
|
|
+; _var - The address to jump to is given as an offset to a
|
9100 |
|
|
+; register, such as X+R3. This is an indirect jump.
|
9101 |
|
|
+; Although we support it, it does require different RTL
|
9102 |
|
|
+; code.
|
9103 |
|
|
+;
|
9104 |
|
|
+(define_expand "call"
|
9105 |
|
|
+ [(call (match_operand 0 "" "")
|
9106 |
|
|
+ (match_operand 1 "" ""))]
|
9107 |
|
|
+ ""
|
9108 |
|
|
+ {
|
9109 |
|
|
+ if (MEM_P(operands[0])) {
|
9110 |
|
|
+ // This should always be the case
|
9111 |
|
|
+ rtx addr = XEXP(operands[0],0);
|
9112 |
|
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
9113 |
122 |
dgisselq |
+ //; fprintf(stderr, "Generating gen_void_call_const()\n");
|
9114 |
102 |
dgisselq |
+ emit_call_insn(gen_void_call_const(addr,
|
9115 |
|
|
+ operands[1]));
|
9116 |
|
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(
|
9117 |
|
|
+ XEXP(addr,0)))) {
|
9118 |
|
|
+ emit_call_insn(gen_void_call_mem(XEXP(addr,0),
|
9119 |
|
|
+ operands[1]));
|
9120 |
|
|
+ } else {
|
9121 |
|
|
+ emit_call_insn(gen_void_call_var(addr,
|
9122 |
|
|
+ operands[1]));
|
9123 |
|
|
+ }
|
9124 |
|
|
+ DONE;
|
9125 |
|
|
+ }
|
9126 |
|
|
+ })
|
9127 |
|
|
+;
|
9128 |
|
|
+;
|
9129 |
|
|
+;
|
9130 |
|
|
+; How do we want to do this better?
|
9131 |
|
|
+; Replace the RTL w/
|
9132 |
|
|
+; return_label= gen_label_rtx();
|
9133 |
|
|
+; emit_movsi(gen_rtx_REG(zip_R0),plus_constant(
|
9134 |
|
|
+; gen_rtx_REG(zip_PC),return_label));
|
9135 |
|
|
+; emit_jump(label_rtx(
|
9136 |
|
|
+;
|
9137 |
|
|
+; emit_label(return_label);
|
9138 |
|
|
+;
|
9139 |
|
|
+; The problem is: we can't! GCC distinguishes between jumps and calls when
|
9140 |
|
|
+; optimizing, and it doesn't see the need to keep the label around. Thus, the
|
9141 |
|
|
+; label gets removed and the call gets lost. Hence we do it this way (below).
|
9142 |
|
|
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
|
9143 |
|
|
+; recognize as such, but for now we'll use .Lcall# as our label.
|
9144 |
|
|
+;
|
9145 |
|
|
+(define_insn "void_call_const"
|
9146 |
122 |
dgisselq |
+ [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
9147 |
111 |
dgisselq |
+ (match_operand 1 "const_int_operand" "n"))
|
9148 |
122 |
dgisselq |
+ (clobber (reg:SI RTN_REG))
|
9149 |
|
|
+ (clobber (reg:CC CC_REG))]
|
9150 |
102 |
dgisselq |
+ ""
|
9151 |
|
|
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
|
9152 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9153 |
|
|
+(define_insn "void_call_mem"
|
9154 |
122 |
dgisselq |
+ [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
|
9155 |
111 |
dgisselq |
+ (match_operand 1 "const_int_operand" "n"))
|
9156 |
122 |
dgisselq |
+ (clobber (reg:SI RTN_REG))
|
9157 |
|
|
+ (clobber (reg:CC CC_REG))]
|
9158 |
102 |
dgisselq |
+ ""
|
9159 |
|
|
+ "MOV .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
|
9160 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9161 |
|
|
+;
|
9162 |
|
|
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
9163 |
|
|
+(define_insn "void_call_var"
|
9164 |
122 |
dgisselq |
+ [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
|
9165 |
111 |
dgisselq |
+ (match_operand 1 "const_int_operand" "n"))
|
9166 |
122 |
dgisselq |
+ (clobber (reg:SI RTN_REG))
|
9167 |
|
|
+ (clobber (reg:CC CC_REG))]
|
9168 |
102 |
dgisselq |
+ ""
|
9169 |
|
|
+ "MOV .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
|
9170 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9171 |
|
|
+(define_expand "call_value"
|
9172 |
122 |
dgisselq |
+ [(parallel [(set (reg:SI RTNV_REG)
|
9173 |
102 |
dgisselq |
+ (call (match_operand:SI 1 "" "")
|
9174 |
111 |
dgisselq |
+ (match_operand 2 "const_int_operand" "n")))
|
9175 |
122 |
dgisselq |
+ (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))
|
9176 |
|
|
+ (clobber (reg:CC CC_REG))])]
|
9177 |
102 |
dgisselq |
+ ""
|
9178 |
|
|
+ {
|
9179 |
122 |
dgisselq |
+ //; extern void zip_debug_rtx(const_rtx);
|
9180 |
|
|
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
|
9181 |
|
|
+ //; zip_debug_rtx(operands[1]);
|
9182 |
102 |
dgisselq |
+ if (MEM_P(operands[1])) {
|
9183 |
122 |
dgisselq |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n");
|
9184 |
|
|
+ //; zip_debug_rtx(operands[1]);
|
9185 |
|
|
+ //; This should always be the case
|
9186 |
102 |
dgisselq |
+ rtx addr = XEXP(operands[1],0);
|
9187 |
|
|
+ if (zip_const_address_operand_p(addr, SImode)) {
|
9188 |
122 |
dgisselq |
+ //; fprintf(stderr, "Generating gen_reg_call_const()\n");
|
9189 |
102 |
dgisselq |
+ emit_call_insn(gen_reg_call_const(addr, operands[2]));
|
9190 |
|
|
+ } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
|
9191 |
122 |
dgisselq |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
|
9192 |
102 |
dgisselq |
+ emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2]));
|
9193 |
|
|
+ } else {
|
9194 |
122 |
dgisselq |
+ //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
|
9195 |
102 |
dgisselq |
+ emit_call_insn(gen_reg_call_var(addr, operands[2]));
|
9196 |
|
|
+ }
|
9197 |
|
|
+ DONE;
|
9198 |
|
|
+ }
|
9199 |
|
|
+ })
|
9200 |
|
|
+(define_insn "reg_call_const"
|
9201 |
122 |
dgisselq |
+ [(set (reg:SI RTNV_REG)
|
9202 |
102 |
dgisselq |
+ (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
|
9203 |
111 |
dgisselq |
+ (match_operand 1 "const_int_operand" "n")))
|
9204 |
122 |
dgisselq |
+ (clobber (reg:SI RTN_REG))
|
9205 |
|
|
+ (clobber (reg:CC CC_REG))]
|
9206 |
102 |
dgisselq |
+ ""
|
9207 |
|
|
+ "MOV .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
|
9208 |
|
|
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9209 |
|
|
+(define_insn "reg_call_mem"
|
9210 |
|
|
+ [(set (reg:SI RTNV_REG)
|
9211 |
111 |
dgisselq |
+ (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
|
9212 |
|
|
+ (match_operand 1 "const_int_operand" "n")))
|
9213 |
122 |
dgisselq |
+ (clobber (reg:SI RTN_REG))
|
9214 |
|
|
+ (clobber (reg:CC CC_REG))]
|
9215 |
102 |
dgisselq |
+ ""
|
9216 |
111 |
dgisselq |
+ "MOV .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
|
9217 |
102 |
dgisselq |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9218 |
111 |
dgisselq |
+;
|
9219 |
102 |
dgisselq |
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
|
9220 |
|
|
+(define_insn "reg_call_var"
|
9221 |
122 |
dgisselq |
+ [(set (reg:SI RTNV_REG)
|
9222 |
102 |
dgisselq |
+ (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
|
9223 |
111 |
dgisselq |
+ (match_operand 1 "const_int_operand" "n")))
|
9224 |
122 |
dgisselq |
+ (clobber (reg:SI RTN_REG))
|
9225 |
|
|
+ (clobber (reg:CC CC_REG))]
|
9226 |
102 |
dgisselq |
+ ""
|
9227 |
111 |
dgisselq |
+ "MOV .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
|
9228 |
102 |
dgisselq |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
9229 |
|
|
+;
|
9230 |
|
|
+;
|
9231 |
|
|
+;
|
9232 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9233 |
|
|
+;;
|
9234 |
|
|
+;; Frame manipulation RTX
|
9235 |
|
|
+;;
|
9236 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9237 |
|
|
+;
|
9238 |
|
|
+;
|
9239 |
|
|
+;
|
9240 |
|
|
+(define_expand "prologue"
|
9241 |
|
|
+ [(const_int 0)]
|
9242 |
|
|
+ ""
|
9243 |
|
|
+ "{ zip_expand_prologue(); DONE; }")
|
9244 |
|
|
+(define_expand "epilogue"
|
9245 |
|
|
+ [(return)]
|
9246 |
|
|
+ ""
|
9247 |
|
|
+ "{ zip_expand_epilogue(); DONE; }")
|
9248 |
|
|
+(define_expand "return" ; In order to use the function predicate, this *must*
|
9249 |
|
|
+ [(return)] ; be a define_expand
|
9250 |
|
|
+ "zip_use_return_insn()")
|
9251 |
|
|
+ ; "JMP R0"
|
9252 |
|
|
+ ; [(set_attr "ccresult" "unchanged")])
|
9253 |
|
|
+(define_insn "*return" ; A "*" -- means it cannot be called from C
|
9254 |
|
|
+ [(return)]
|
9255 |
|
|
+ ""
|
9256 |
|
|
+ "JMP R0"
|
9257 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
9258 |
|
|
+(define_insn "simple_return" ; A "*" -- means it cannot be called from C
|
9259 |
|
|
+ [(simple_return)]
|
9260 |
|
|
+ ""
|
9261 |
|
|
+ "JMP R0"
|
9262 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
9263 |
|
|
+;
|
9264 |
|
|
+;
|
9265 |
|
|
+;
|
9266 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9267 |
|
|
+;;
|
9268 |
|
|
+;; Zip Builtin Functions
|
9269 |
|
|
+;;
|
9270 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9271 |
|
|
+;
|
9272 |
|
|
+;
|
9273 |
|
|
+;
|
9274 |
|
|
+(define_insn "zip_rtu"
|
9275 |
|
|
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU)
|
9276 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
9277 |
102 |
dgisselq |
+ "(!ZIP_USER)"
|
9278 |
|
|
+ "RTU"
|
9279 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9280 |
171 |
dgisselq |
+(define_insn "zip_busy"
|
9281 |
|
|
+ [(set (pc) (minus:SI (pc) (const_int 1)))]
|
9282 |
|
|
+ ""
|
9283 |
|
|
+ "BUSY"
|
9284 |
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
9285 |
102 |
dgisselq |
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out
|
9286 |
|
|
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT)
|
9287 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
9288 |
102 |
dgisselq |
+ "(!ZIP_USER)"
|
9289 |
|
|
+ "HALT"
|
9290 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9291 |
|
|
+(define_insn "zip_idle"
|
9292 |
|
|
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE)
|
9293 |
122 |
dgisselq |
+ (clobber (reg:CC CC_REG))]
|
9294 |
102 |
dgisselq |
+ ""
|
9295 |
|
|
+ "WAIT"
|
9296 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9297 |
|
|
+(define_insn "zip_syscall"
|
9298 |
|
|
+ [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_SYSCALL)]
|
9299 |
|
|
+ ""
|
9300 |
|
|
+ "CLR\tCC"
|
9301 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9302 |
|
|
+;
|
9303 |
|
|
+;
|
9304 |
|
|
+; Operator "save_context"
|
9305 |
|
|
+;
|
9306 |
117 |
dgisselq |
+; Okay, so we're not really reading and writing operand 0, %0, however
|
9307 |
|
|
+; if we don't list it as a "+r" register, the compiler may allocate it
|
9308 |
|
|
+; among the other registers, thus we clobber it in the middle of the
|
9309 |
|
|
+; operation before the task is complete.
|
9310 |
102 |
dgisselq |
+;
|
9311 |
|
|
+(define_insn "zip_save_context"
|
9312 |
117 |
dgisselq |
+ [(unspec_volatile
|
9313 |
|
|
+ [ (match_operand:SI 0 "register_operand" "+r") ]
|
9314 |
102 |
dgisselq |
+ UNSPEC_SAVE_CONTEXT)
|
9315 |
|
|
+ (clobber (match_scratch:SI 1 "=r"))
|
9316 |
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
9317 |
|
|
+ (clobber (match_scratch:SI 3 "=r"))
|
9318 |
117 |
dgisselq |
+ (clobber (match_scratch:SI 4 "=r"))]
|
9319 |
102 |
dgisselq |
+ "(!ZIP_USER)"
|
9320 |
|
|
+ "MOV\tuR0,%1
|
9321 |
|
|
+ MOV\tuR1,%2
|
9322 |
|
|
+ MOV\tuR2,%3
|
9323 |
|
|
+ MOV\tuR3,%4
|
9324 |
|
|
+ STO\t%1,%0
|
9325 |
|
|
+ STO\t%2,1(%0)
|
9326 |
|
|
+ STO\t%3,2(%0)
|
9327 |
|
|
+ STO\t%4,3(%0)
|
9328 |
|
|
+ MOV\tuR4,%1
|
9329 |
|
|
+ MOV\tuR5,%2
|
9330 |
|
|
+ MOV\tuR6,%3
|
9331 |
|
|
+ MOV\tuR7,%4
|
9332 |
|
|
+ STO\t%1,4(%0)
|
9333 |
|
|
+ STO\t%2,5(%0)
|
9334 |
|
|
+ STO\t%3,6(%0)
|
9335 |
|
|
+ STO\t%4,7(%0)
|
9336 |
|
|
+ MOV\tuR8,%1
|
9337 |
|
|
+ MOV\tuR9,%2
|
9338 |
|
|
+ MOV\tuR10,%3
|
9339 |
|
|
+ MOV\tuR11,%4
|
9340 |
|
|
+ STO\t%1,8(%0)
|
9341 |
|
|
+ STO\t%2,9(%0)
|
9342 |
|
|
+ STO\t%3,10(%0)
|
9343 |
|
|
+ STO\t%4,11(%0)
|
9344 |
|
|
+ MOV\tuR12,%1
|
9345 |
|
|
+ MOV\tuSP,%2
|
9346 |
|
|
+ MOV\tuCC,%3
|
9347 |
|
|
+ MOV\tuPC,%4
|
9348 |
|
|
+ STO\t%1,12(%0)
|
9349 |
|
|
+ STO\t%2,13(%0)
|
9350 |
|
|
+ STO\t%3,14(%0)
|
9351 |
|
|
+ STO\t%4,15(%0)"
|
9352 |
122 |
dgisselq |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
9353 |
117 |
dgisselq |
+;
|
9354 |
|
|
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
|
9355 |
|
|
+; even though we don't really read (or change) its value throughout this
|
9356 |
|
|
+; operation.
|
9357 |
|
|
+;
|
9358 |
102 |
dgisselq |
+(define_insn "zip_restore_context"
|
9359 |
|
|
+ [(unspec_volatile [
|
9360 |
117 |
dgisselq |
+ (match_operand:SI 0 "register_operand" "+r")] UNSPEC_RESTORE_CONTEXT)
|
9361 |
102 |
dgisselq |
+ (clobber (match_scratch:SI 1 "=r"))
|
9362 |
|
|
+ (clobber (match_scratch:SI 2 "=r"))
|
9363 |
|
|
+ (clobber (match_scratch:SI 3 "=r"))
|
9364 |
117 |
dgisselq |
+ (clobber (match_scratch:SI 4 "=r"))]
|
9365 |
102 |
dgisselq |
+ "(!ZIP_USER)"
|
9366 |
|
|
+ "LOD\t0(%0),%1
|
9367 |
|
|
+ LOD\t1(%0),%2
|
9368 |
|
|
+ LOD\t2(%0),%3
|
9369 |
|
|
+ LOD\t3(%0),%4
|
9370 |
|
|
+ MOV\t%1,uR0
|
9371 |
|
|
+ MOV\t%2,uR1
|
9372 |
|
|
+ MOV\t%3,uR2
|
9373 |
|
|
+ MOV\t%4,uR3
|
9374 |
|
|
+ LOD\t4(%0),%1
|
9375 |
|
|
+ LOD\t5(%0),%2
|
9376 |
|
|
+ LOD\t6(%0),%3
|
9377 |
|
|
+ LOD\t7(%0),%4
|
9378 |
|
|
+ MOV\t%1,uR4
|
9379 |
|
|
+ MOV\t%2,uR5
|
9380 |
|
|
+ MOV\t%3,uR6
|
9381 |
|
|
+ MOV\t%4,uR7
|
9382 |
|
|
+ LOD\t8(%0),%1
|
9383 |
|
|
+ LOD\t9(%0),%2
|
9384 |
|
|
+ LOD\t10(%0),%3
|
9385 |
|
|
+ LOD\t11(%0),%4
|
9386 |
|
|
+ MOV\t%1,uR8
|
9387 |
|
|
+ MOV\t%2,uR9
|
9388 |
|
|
+ MOV\t%3,uR10
|
9389 |
|
|
+ MOV\t%4,uR11
|
9390 |
|
|
+ LOD\t12(%0),%1
|
9391 |
|
|
+ LOD\t13(%0),%2
|
9392 |
|
|
+ LOD\t14(%0),%3
|
9393 |
|
|
+ LOD\t15(%0),%4
|
9394 |
|
|
+ MOV\t%1,uR12
|
9395 |
|
|
+ MOV\t%2,uSP
|
9396 |
|
|
+ MOV\t%3,uCC
|
9397 |
|
|
+ MOV\t%4,uPC"
|
9398 |
122 |
dgisselq |
+ [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
|
9399 |
102 |
dgisselq |
+(define_insn "zip_bitrev"
|
9400 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
9401 |
|
|
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV))
|
9402 |
|
|
+ ]
|
9403 |
|
|
+ ""
|
9404 |
|
|
+ "BREV\t%1,%0"
|
9405 |
122 |
dgisselq |
+ [(set_attr "ccresult" "unchanged")])
|
9406 |
102 |
dgisselq |
+(define_insn "zip_cc"
|
9407 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
9408 |
|
|
+ (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
9409 |
|
|
+ ""
|
9410 |
|
|
+ "MOV\tCC,%0"
|
9411 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
9412 |
117 |
dgisselq |
+(define_insn "zip_ucc"
|
9413 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
9414 |
|
|
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETUCC))]
|
9415 |
|
|
+ ""
|
9416 |
|
|
+ "MOV\tuCC,%0"
|
9417 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
9418 |
111 |
dgisselq |
+(define_insn "zip_cc_sto"
|
9419 |
|
|
+ [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
|
9420 |
117 |
dgisselq |
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
9421 |
111 |
dgisselq |
+ ""
|
9422 |
|
|
+ "STO\tCC,(%0)"
|
9423 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
9424 |
|
|
+(define_insn "zip_cc_sto_off"
|
9425 |
|
|
+ [(set (mem:SI (plus:SI
|
9426 |
|
|
+ (match_operand:SI 0 "register_operand" "r")
|
9427 |
|
|
+ (match_operand:SI 1 "const_int_operand" "N")))
|
9428 |
117 |
dgisselq |
+ (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
|
9429 |
111 |
dgisselq |
+ ""
|
9430 |
|
|
+ "STO\tCC,%1(%0)"
|
9431 |
|
|
+ [(set_attr "ccresult" "unchanged")])
|
9432 |
102 |
dgisselq |
+(define_insn "ldilo"
|
9433 |
|
|
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
9434 |
|
|
+ (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
|
9435 |
|
|
+ ""
|
9436 |
|
|
+ "LDILO %1,%0"
|
9437 |
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
9438 |
|
|
+
|
9439 |
|
|
+;
|
9440 |
|
|
+;
|
9441 |
171 |
dgisselq |
+; Missing still: zip_break(idno)
|
9442 |
|
|
+; Would also be nice to have a zip_reg builtin, allowing us to read or write
|
9443 |
|
|
+; a register, as in zip_reg(5)=40;. Not sure what this means, though, when the
|
9444 |
|
|
+; number placed into this is not constant, or how to specify that it must *only*
|
9445 |
|
|
+; be constant. Thats actually the problem with both proposals, zip_break(id)
|
9446 |
|
|
+; and zip_reg(regno)--both depend upon a compile time constant to work.
|
9447 |
102 |
dgisselq |
+;
|
9448 |
171 |
dgisselq |
+;
|
9449 |
|
|
+
|
9450 |
|
|
+;
|
9451 |
|
|
+;
|
9452 |
|
|
+;
|
9453 |
102 |
dgisselq |
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9454 |
|
|
+;;
|
9455 |
|
|
+;; Floating point Op-codes
|
9456 |
|
|
+;;
|
9457 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9458 |
|
|
+;
|
9459 |
|
|
+;
|
9460 |
|
|
+;
|
9461 |
|
|
+(define_insn "addsf3"
|
9462 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
9463 |
|
|
+ (plus:SF (match_operand:SF 1 "register_operand" "0")
|
9464 |
122 |
dgisselq |
+ (match_operand:SF 2 "register_operand" "r")))
|
9465 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
9466 |
102 |
dgisselq |
+ "(ZIP_FPU)"
|
9467 |
|
|
+ "FPADD %2,%0"
|
9468 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9469 |
|
|
+(define_insn "subsf3"
|
9470 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
9471 |
|
|
+ (minus:SF (match_operand:SF 1 "register_operand" "0")
|
9472 |
122 |
dgisselq |
+ (match_operand:SF 2 "register_operand" "r")))
|
9473 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
9474 |
102 |
dgisselq |
+ "(ZIP_FPU)"
|
9475 |
|
|
+ "FPSUB %2,%0"
|
9476 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9477 |
|
|
+(define_insn "mulsf3"
|
9478 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
9479 |
|
|
+ (mult:SF (match_operand:SF 1 "register_operand" "0")
|
9480 |
122 |
dgisselq |
+ (match_operand:SF 2 "register_operand" "r")))
|
9481 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
9482 |
102 |
dgisselq |
+ "(ZIP_FPU)"
|
9483 |
|
|
+ "FPMUL %2,%0"
|
9484 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9485 |
|
|
+(define_insn "divsf3"
|
9486 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
9487 |
|
|
+ (div:SF (match_operand:SF 1 "register_operand" "0")
|
9488 |
122 |
dgisselq |
+ (match_operand:SF 2 "register_operand" "r")))
|
9489 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
9490 |
102 |
dgisselq |
+ "(ZIP_FPU)"
|
9491 |
|
|
+ "FPDIV %2,%0"
|
9492 |
|
|
+ [(set_attr "ccresult" "unknown")])
|
9493 |
111 |
dgisselq |
+(define_expand "negsf2"
|
9494 |
|
|
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
9495 |
|
|
+ (neg:SF (match_operand:SF 1 "register_operand" "0")))
|
9496 |
|
|
+ ]
|
9497 |
|
|
+ ""
|
9498 |
|
|
+ {
|
9499 |
|
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
9500 |
|
|
+ if (can_create_pseudo_p()) {
|
9501 |
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
9502 |
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
|
9503 |
122 |
dgisselq |
+ emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
|
9504 |
111 |
dgisselq |
+ DONE;
|
9505 |
|
|
+ } else {
|
9506 |
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
9507 |
122 |
dgisselq |
+ emit_insn(gen_iorsi3(operands[0], operands[0],
|
9508 |
|
|
+ gen_int_mode(1,SImode)));
|
9509 |
111 |
dgisselq |
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
9510 |
|
|
+ DONE;
|
9511 |
|
|
+ }
|
9512 |
|
|
+ })
|
9513 |
|
|
+(define_expand "abssf2"
|
9514 |
122 |
dgisselq |
+ [(set (match_operand:SF 0 "register_operand" "=r")
|
9515 |
|
|
+ (abs:SF (match_operand:SF 1 "register_operand" "0")))
|
9516 |
111 |
dgisselq |
+ ]
|
9517 |
|
|
+ ""
|
9518 |
|
|
+ {
|
9519 |
|
|
+ operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
|
9520 |
|
|
+ if (can_create_pseudo_p()) {
|
9521 |
|
|
+ rtx tmp = gen_reg_rtx(SImode);
|
9522 |
|
|
+ emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
|
9523 |
122 |
dgisselq |
+ emit_insn(gen_andsi3(operands[0], operands[0], tmp));
|
9524 |
111 |
dgisselq |
+ DONE;
|
9525 |
|
|
+ } else {
|
9526 |
|
|
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
9527 |
122 |
dgisselq |
+ emit_insn(gen_andsi3(operands[0], operands[0],
|
9528 |
|
|
+ gen_int_mode(-2,SImode)));
|
9529 |
111 |
dgisselq |
+ emit_insn(gen_zip_bitrev(operands[0],operands[0]));
|
9530 |
|
|
+ DONE;
|
9531 |
|
|
+ }
|
9532 |
|
|
+ })
|
9533 |
102 |
dgisselq |
+;
|
9534 |
|
|
+;
|
9535 |
|
|
+;
|
9536 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9537 |
|
|
+;;
|
9538 |
|
|
+;; Trap Instruction
|
9539 |
|
|
+;;
|
9540 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9541 |
|
|
+;
|
9542 |
|
|
+;
|
9543 |
|
|
+; The ZipCPU doesn't really have a "trap" instruction per se. The goal is that
|
9544 |
|
|
+; *nothing* should ever trap, and so we should never get here. However, the
|
9545 |
|
|
+; compiler seems to want a trap instruction for some reason. (It keeps us
|
9546 |
|
|
+; from calling the abort() function, if we don't define these ...) So let's
|
9547 |
|
|
+; just grab onto the break instruction and declare it to be a trap instruction
|
9548 |
|
|
+; for our purposes. Alternatively, we might've used a syscall, but ... this
|
9549 |
|
|
+; will work for both user and system instructions.
|
9550 |
|
|
+;
|
9551 |
|
|
+(define_insn "trap"
|
9552 |
|
|
+ [(trap_if (const_int 1) (const_int 0))]
|
9553 |
|
|
+ ""
|
9554 |
|
|
+ "BREAK"
|
9555 |
|
|
+ [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
|
9556 |
|
|
+;
|
9557 |
|
|
+(define_expand "ctrap<mode>4"
|
9558 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
9559 |
|
|
+ (match_operand:ZI 1 "register_operand" "r")
|
9560 |
|
|
+ (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
|
9561 |
102 |
dgisselq |
+ (trap_if (match_operator 0 "ordered_comparison_operator"
|
9562 |
122 |
dgisselq |
+ [(reg:CC CC_REG) (const_int 0)])
|
9563 |
102 |
dgisselq |
+ (match_operand 3 "const_int_operand" "O"))]
|
9564 |
|
|
+ ""
|
9565 |
|
|
+ )
|
9566 |
|
|
+(define_insn "trapif"
|
9567 |
|
|
+ [(trap_if (match_operator 0 "ordered_comparison_operator"
|
9568 |
122 |
dgisselq |
+ [(reg:CC CC_REG) (const_int 0)])
|
9569 |
102 |
dgisselq |
+ (match_operand 1 "const_int_operand" "O"))]
|
9570 |
|
|
+ ""
|
9571 |
|
|
+ "BREAK\t%1"
|
9572 |
|
|
+ [(set_attr "predicable" "no")])
|
9573 |
|
|
+;
|
9574 |
|
|
+;
|
9575 |
|
|
+;
|
9576 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9577 |
|
|
+;;
|
9578 |
|
|
+;; Unimplemented (or not yet implemented) RTL Codes
|
9579 |
|
|
+;;
|
9580 |
|
|
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
9581 |
|
|
+;
|
9582 |
|
|
+;
|
9583 |
|
|
+;
|
9584 |
|
|
+;(define_insn "sync_compare_and_swapsi"
|
9585 |
|
|
+; [(set ...
|
9586 |
|
|
+; )]
|
9587 |
|
|
+; "(ZIP_ATMOC)"
|
9588 |
|
|
+; LOCK (alu) // Hmmm ... need to modify if I will
|
9589 |
|
|
+; LOD %1,%0 OP-VALID // operate on the value before the store
|
9590 |
|
|
+; CMP %0,%2 DCD-valid
|
9591 |
|
|
+; STO.Z %2,%1 PF-valid
|
9592 |
|
|
+;
|
9593 |
|
|
+;(define_insn "sync_lock_test_and_setsi"
|
9594 |
|
|
+; LOCK
|
9595 |
|
|
+; LOD %1,%0
|
9596 |
|
|
+; STO %0,%1
|
9597 |
|
|
+;
|
9598 |
|
|
+;(define_insn "sync_lock_releasesi"
|
9599 |
|
|
+; STO %1,%0
|
9600 |
|
|
+;
|
9601 |
|
|
+;
|
9602 |
|
|
+;(define_insn "negvsi3"
|
9603 |
|
|
+; "MOV %1,%0
|
9604 |
|
|
+; XOR -1,%0
|
9605 |
|
|
+; ADD 1,%0
|
9606 |
|
|
+; BV %2"
|
9607 |
|
|
+; "")
|
9608 |
124 |
dgisselq |
+;
|
9609 |
|
|
+; Match:
|
9610 |
|
|
+; CMP R1,R0
|
9611 |
|
|
+; BGTU lbl
|
9612 |
|
|
+; Transform to:
|
9613 |
|
|
+; CMP R0,R1
|
9614 |
|
|
+; BC lbl
|
9615 |
|
|
+;
|
9616 |
117 |
dgisselq |
+(define_peephole2
|
9617 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
9618 |
|
|
+ (match_operand:SI 0 "register_operand")
|
9619 |
|
|
+ (match_operand:SI 1 "register_operand")))
|
9620 |
|
|
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
9621 |
|
|
+ (label_ref (match_operand 2 ""))
|
9622 |
117 |
dgisselq |
+ (pc)))]
|
9623 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)"
|
9624 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
|
9625 |
|
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
9626 |
117 |
dgisselq |
+ (label_ref (match_dup 2))
|
9627 |
|
|
+ (pc)))]
|
9628 |
|
|
+ "")
|
9629 |
127 |
dgisselq |
+(define_peephole2
|
9630 |
|
|
+ [(match_scratch:SI 3 "=r")
|
9631 |
|
|
+ (set (reg:CC CC_REG) (compare:CC
|
9632 |
|
|
+ (match_operand:SI 0 "register_operand")
|
9633 |
|
|
+ (match_operand 1 "const_int_operand")))
|
9634 |
|
|
+ (match_dup 3)
|
9635 |
|
|
+ (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
9636 |
|
|
+ (label_ref (match_operand 2 ""))
|
9637 |
|
|
+ (pc)))]
|
9638 |
|
|
+ "(ZIP_PEEPHOLE)"
|
9639 |
|
|
+ [(set (match_dup 3) (match_dup 1))
|
9640 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))
|
9641 |
|
|
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
9642 |
|
|
+ (label_ref (match_dup 2))
|
9643 |
|
|
+ (pc)))]
|
9644 |
|
|
+ "")
|
9645 |
|
|
+;(define_peephole2
|
9646 |
|
|
+; [(set (reg:CC CC_REG) (compare:CC
|
9647 |
|
|
+; (match_operand:SI 0 "register_operand")
|
9648 |
|
|
+; (match_operand 1 "const_int_operand")))
|
9649 |
|
|
+; (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
|
9650 |
|
|
+; (label_ref (match_operand 2 ""))
|
9651 |
|
|
+; (pc)))]
|
9652 |
|
|
+; ""
|
9653 |
|
|
+; [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
|
9654 |
|
|
+; (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
9655 |
|
|
+; (label_ref (match_dup 2))
|
9656 |
|
|
+; (pc)))]
|
9657 |
|
|
+; "operands[1] = GEN_INT(INTVAL(operands[1])-1);")
|
9658 |
124 |
dgisselq |
+;
|
9659 |
|
|
+;
|
9660 |
|
|
+; Match:
|
9661 |
|
|
+; CMP R1,R0
|
9662 |
|
|
+; BGEU lbl
|
9663 |
|
|
+; Transform to:
|
9664 |
|
|
+; CMP 1(R0),R1
|
9665 |
|
|
+; BC lbl
|
9666 |
|
|
+;
|
9667 |
117 |
dgisselq |
+(define_peephole2
|
9668 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
9669 |
|
|
+ (match_operand:SI 0 "register_operand")
|
9670 |
|
|
+ (match_operand:SI 1 "register_operand")))
|
9671 |
|
|
+ (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
|
9672 |
|
|
+ (label_ref (match_operand 2 ""))
|
9673 |
117 |
dgisselq |
+ (pc)))]
|
9674 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)"
|
9675 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
9676 |
146 |
dgisselq |
+ (match_dup 1) (plus:SI (match_dup 0) (const_int 1))))
|
9677 |
122 |
dgisselq |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
9678 |
117 |
dgisselq |
+ (label_ref (match_dup 2))
|
9679 |
|
|
+ (pc)))]
|
9680 |
|
|
+ "")
|
9681 |
124 |
dgisselq |
+;
|
9682 |
|
|
+;
|
9683 |
|
|
+; Match:
|
9684 |
|
|
+; CMP R1,R0
|
9685 |
|
|
+; BGE lbl
|
9686 |
|
|
+; Transform to:
|
9687 |
|
|
+; CMP 1(R0),R1
|
9688 |
|
|
+; BLT lbl
|
9689 |
142 |
dgisselq |
+; ... why? when we support a BGE instruction?
|
9690 |
|
|
+;(define_peephole2
|
9691 |
|
|
+ ;[(set (reg:CC CC_REG) (compare:CC
|
9692 |
|
|
+ ;(match_operand:SI 0 "register_operand")
|
9693 |
|
|
+ ;(match_operand:SI 1 "register_operand")))
|
9694 |
|
|
+ ;(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
|
9695 |
|
|
+ ;(label_ref (match_operand 2 ""))
|
9696 |
|
|
+ ;(pc)))]
|
9697 |
|
|
+ ;"(ZIP_PEEPHOLE)"
|
9698 |
|
|
+ ;[(set (reg:CC CC_REG) (compare:CC (match_dup 1)
|
9699 |
|
|
+ ;(plus:SI (match_dup 0) (const_int 1))))
|
9700 |
|
|
+ ;(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
9701 |
|
|
+ ;(label_ref (match_dup 2))
|
9702 |
|
|
+ ;(pc)))]
|
9703 |
|
|
+ ;"")
|
9704 |
124 |
dgisselq |
+;
|
9705 |
|
|
+;
|
9706 |
|
|
+; Match:
|
9707 |
|
|
+; CMP R1,R0
|
9708 |
|
|
+; BLEU lbl
|
9709 |
|
|
+; Transform to:
|
9710 |
|
|
+; CMP 1(R1),R0
|
9711 |
142 |
dgisselq |
+; BC lbl
|
9712 |
124 |
dgisselq |
+;
|
9713 |
117 |
dgisselq |
+(define_peephole2
|
9714 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC
|
9715 |
|
|
+ (match_operand:SI 0 "register_operand" "")
|
9716 |
117 |
dgisselq |
+ (match_operand:SI 1 "register_operand" "")))
|
9717 |
122 |
dgisselq |
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
9718 |
117 |
dgisselq |
+ (label_ref (match_operand 2 "" ""))
|
9719 |
|
|
+ (pc)))]
|
9720 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)"
|
9721 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
|
9722 |
146 |
dgisselq |
+ (plus:SI (match_dup 1) (const_int 1))))
|
9723 |
122 |
dgisselq |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
9724 |
117 |
dgisselq |
+ (label_ref (match_dup 2))
|
9725 |
|
|
+ (pc)))]
|
9726 |
|
|
+ "")
|
9727 |
|
|
+;
|
9728 |
142 |
dgisselq |
+;
|
9729 |
|
|
+;
|
9730 |
|
|
+; Match:
|
9731 |
|
|
+; CMP R1,R0
|
9732 |
|
|
+; BLE lbl
|
9733 |
|
|
+; Transform to:
|
9734 |
|
|
+; CMP 1(R1),R0
|
9735 |
|
|
+; BLT lbl
|
9736 |
|
|
+;
|
9737 |
127 |
dgisselq |
+(define_peephole2
|
9738 |
|
|
+ [(set (reg:CC CC_REG)
|
9739 |
|
|
+ (compare:CC (match_operand:SI 0 "register_operand" "")
|
9740 |
|
|
+ (match_operand:SI 1 "const_int_operand" "")))
|
9741 |
|
|
+ (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
|
9742 |
|
|
+ (label_ref (match_operand 2 "" ""))
|
9743 |
|
|
+ (pc)))]
|
9744 |
|
|
+ "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
|
9745 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
|
9746 |
|
|
+ (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
|
9747 |
|
|
+ (label_ref (match_dup 2))
|
9748 |
|
|
+ (pc)))]
|
9749 |
|
|
+ "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
|
9750 |
142 |
dgisselq |
+;
|
9751 |
|
|
+; Match:
|
9752 |
|
|
+; CMP R1,R0
|
9753 |
|
|
+; BLEU lbl
|
9754 |
|
|
+; Transform to:
|
9755 |
|
|
+; CMP 1(R1),R0
|
9756 |
|
|
+; BC(LTU) lbl
|
9757 |
|
|
+;
|
9758 |
127 |
dgisselq |
+(define_peephole2
|
9759 |
|
|
+ [(set (reg:CC CC_REG)
|
9760 |
|
|
+ (compare:CC (match_operand:SI 0 "register_operand" "")
|
9761 |
|
|
+ (match_operand:SI 1 "const_int_operand" "")))
|
9762 |
|
|
+ (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
|
9763 |
|
|
+ (label_ref (match_operand 2 "" ""))
|
9764 |
|
|
+ (pc)))]
|
9765 |
|
|
+ "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
|
9766 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
|
9767 |
142 |
dgisselq |
+ (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
|
9768 |
127 |
dgisselq |
+ (label_ref (match_dup 2))
|
9769 |
|
|
+ (pc)))]
|
9770 |
|
|
+ "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
|
9771 |
102 |
dgisselq |
+;
|
9772 |
117 |
dgisselq |
+;
|
9773 |
|
|
+;
|
9774 |
|
|
+;
|
9775 |
127 |
dgisselq |
+; Match:
|
9776 |
|
|
+; (parallel [(set () ()) (clobber (CC))])
|
9777 |
|
|
+; (compare () ())
|
9778 |
|
|
+; Transform to:
|
9779 |
|
|
+; (parallel [(set () ()) (set (CC) (0))]
|
9780 |
|
|
+; (compare () ())
|
9781 |
117 |
dgisselq |
+;
|
9782 |
127 |
dgisselq |
+(define_peephole2
|
9783 |
|
|
+ [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
|
9784 |
|
|
+ (clobber (reg:CC CC_REG))])
|
9785 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "")
|
9786 |
|
|
+ (match_operand:SI 3 "")))]
|
9787 |
|
|
+ "(ZIP_PEEPHOLE)&&zip_insn_sets_cc(insn)"
|
9788 |
|
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
9789 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9790 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (match_dup 3)))]
|
9791 |
|
|
+ "")
|
9792 |
|
|
+;
|
9793 |
|
|
+;
|
9794 |
|
|
+;
|
9795 |
122 |
dgisselq |
+; Match:
|
9796 |
127 |
dgisselq |
+; (parallel [(set () ()) (clobber (CC))])
|
9797 |
|
|
+; (set () ())
|
9798 |
|
|
+; (compare () ())
|
9799 |
|
|
+; Transform to:
|
9800 |
|
|
+; (parallel [(set () ()) (set (CC) (0))]
|
9801 |
|
|
+; (set () ())
|
9802 |
|
|
+; (compare () ())
|
9803 |
|
|
+;
|
9804 |
|
|
+(define_peephole2
|
9805 |
|
|
+ [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
|
9806 |
|
|
+ (clobber (reg:CC CC_REG))])
|
9807 |
|
|
+ (set (match_operand 2 "") (match_operand 3 ""))
|
9808 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_operand:SI 4 "")
|
9809 |
|
|
+ (match_operand:SI 5 "")))]
|
9810 |
|
|
+ "(ZIP_PEEPHOLE)&&(zip_insn_sets_cc(insn))&&((!REG_P(operands[2]))||(REGNO(operands[2])!=CC_REG))"
|
9811 |
|
|
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
9812 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9813 |
|
|
+ (set (match_dup 2) (match_dup 3))
|
9814 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 4) (match_dup 5)))]
|
9815 |
|
|
+ "")
|
9816 |
|
|
+;
|
9817 |
|
|
+;
|
9818 |
|
|
+;
|
9819 |
|
|
+; Match:
|
9820 |
122 |
dgisselq |
+; MOV A(R1),R3
|
9821 |
|
|
+; CMP R3,R0
|
9822 |
|
|
+; (R3 is dead)
|
9823 |
|
|
+; Transform to:
|
9824 |
|
|
+; CMP A(R1),R0
|
9825 |
|
|
+;
|
9826 |
|
|
+(define_peephole2
|
9827 |
|
|
+ [(set (match_operand:SI 3 "register_operand")
|
9828 |
|
|
+ (plus:SI (match_operand:SI 1 "register_operand")
|
9829 |
|
|
+ (match_operand:SI 2 "zip_mvimm_operand_p")))
|
9830 |
|
|
+ (set (reg:CC CC_REG)
|
9831 |
|
|
+ (compare:CC (match_operand:SI 0 "register_operand")
|
9832 |
|
|
+ (match_dup 3)))]
|
9833 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&peep2_regno_dead_p(2, REGNO(operands[3]))"
|
9834 |
122 |
dgisselq |
+ [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
|
9835 |
|
|
+ (plus:SI (match_dup 1) (match_dup 2))))]
|
9836 |
|
|
+ "")
|
9837 |
|
|
+;
|
9838 |
|
|
+;
|
9839 |
|
|
+; Match:
|
9840 |
|
|
+; ALU OpB,R0
|
9841 |
|
|
+; CMP 0,R0
|
9842 |
|
|
+; Transform to:
|
9843 |
|
|
+; ALU OpB,R0
|
9844 |
|
|
+;
|
9845 |
|
|
+(define_peephole2
|
9846 |
124 |
dgisselq |
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
9847 |
|
|
+ (match_operand:SI 1 ""))
|
9848 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9849 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
9850 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)"
|
9851 |
122 |
dgisselq |
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
9852 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9853 |
|
|
+ ])
|
9854 |
|
|
+;
|
9855 |
|
|
+;
|
9856 |
|
|
+; Match:
|
9857 |
|
|
+; ALU OpB,R0
|
9858 |
|
|
+; MOV R1,R2 // Can be LDI, LOD, STO, etc.
|
9859 |
127 |
dgisselq |
+; CMP 0,R0
|
9860 |
122 |
dgisselq |
+; Transform to:
|
9861 |
|
|
+; ALU OpB,R0
|
9862 |
|
|
+; MOV R0,R1
|
9863 |
|
|
+;
|
9864 |
|
|
+(define_peephole2
|
9865 |
124 |
dgisselq |
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
9866 |
|
|
+ (match_operand:SI 1 ""))
|
9867 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9868 |
124 |
dgisselq |
+ (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 ""))
|
9869 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
|
9870 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&((!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>=FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG))))"
|
9871 |
122 |
dgisselq |
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
9872 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9873 |
|
|
+ (set (match_dup 2) (match_dup 3))
|
9874 |
|
|
+ ])
|
9875 |
|
|
+;
|
9876 |
|
|
+;
|
9877 |
|
|
+; Match:
|
9878 |
|
|
+; ALU OpB,R0
|
9879 |
|
|
+; MOV R0,R1
|
9880 |
|
|
+; CMP 0,R1
|
9881 |
|
|
+; Transform to:
|
9882 |
|
|
+; ALU OpB,R0
|
9883 |
|
|
+; MOV R0,R1
|
9884 |
|
|
+;
|
9885 |
|
|
+(define_peephole2
|
9886 |
124 |
dgisselq |
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
9887 |
|
|
+ (match_operand:SI 1 ""))
|
9888 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9889 |
124 |
dgisselq |
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))
|
9890 |
122 |
dgisselq |
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
|
9891 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)"
|
9892 |
122 |
dgisselq |
+ [(parallel [(set (match_dup 0) (match_dup 1))
|
9893 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9894 |
|
|
+ (set (match_dup 2) (match_dup 3))
|
9895 |
|
|
+ ])
|
9896 |
|
|
+;
|
9897 |
124 |
dgisselq |
+;
|
9898 |
|
|
+; Match:
|
9899 |
|
|
+; MOV R1,R0
|
9900 |
|
|
+; ADD $x,R0
|
9901 |
|
|
+; (CCREG is dead, and x is within range ...)
|
9902 |
|
|
+; Transform to:
|
9903 |
127 |
dgisselq |
+; MOV $x(R1),R0
|
9904 |
124 |
dgisselq |
+(define_peephole2
|
9905 |
|
|
+ [(set (match_operand:SI 0 "register_operand")
|
9906 |
|
|
+ (match_operand:SI 1 "register_operand"))
|
9907 |
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
|
9908 |
|
|
+ (match_operand 2 "zip_mvimm_operand_p")))
|
9909 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9910 |
|
|
+ ]
|
9911 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))"
|
9912 |
124 |
dgisselq |
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
|
9913 |
|
|
+;
|
9914 |
127 |
dgisselq |
+; Match:
|
9915 |
|
|
+; MOV A(R0),R0
|
9916 |
|
|
+; ADD $x,R1
|
9917 |
|
|
+; (CCREG is dead, and (A+x) is within range ...)
|
9918 |
|
|
+; Transform to:
|
9919 |
|
|
+; MOV $x(R1),R0
|
9920 |
124 |
dgisselq |
+;
|
9921 |
127 |
dgisselq |
+(define_peephole2
|
9922 |
|
|
+ [(set (match_operand:SI 0 "register_operand")
|
9923 |
|
|
+ (plus:SI (match_operand:SI 1 "register_operand")
|
9924 |
|
|
+ (match_operand 2 "zip_mvimm_operand_p")))
|
9925 |
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
|
9926 |
|
|
+ (match_operand 3 "zip_mvimm_operand_p")))
|
9927 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9928 |
|
|
+ ]
|
9929 |
|
|
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
|
9930 |
|
|
+ &&(INTVAL(operands[2])+INTVAL(operands[3])<((1<<17)))
|
9931 |
|
|
+ &&(INTVAL(operands[2])+INTVAL(operands[3])>=-(1<<17))"
|
9932 |
|
|
+ [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
|
9933 |
|
|
+ "operands[2]=GEN_INT(INTVAL(operands[2])+INTVAL(operands[3]));")
|
9934 |
124 |
dgisselq |
+;
|
9935 |
127 |
dgisselq |
+;
|
9936 |
|
|
+;
|
9937 |
124 |
dgisselq |
+; Match:
|
9938 |
|
|
+; ADD $x,R0
|
9939 |
|
|
+; MOV R0,R1
|
9940 |
|
|
+; (CCREG is dead, and R0 is dead)
|
9941 |
|
|
+; Transform to:
|
9942 |
|
|
+; MOV (A+$x)(R0),R1
|
9943 |
|
|
+; ... again, how do I build this plus?
|
9944 |
|
|
+;
|
9945 |
|
|
+(define_peephole2
|
9946 |
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
9947 |
|
|
+ (plus:SI (match_dup 0)
|
9948 |
|
|
+ (match_operand 1 "zip_mvimm_operand_p")))
|
9949 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9950 |
|
|
+ (set (match_operand:SI 2 "register_operand") (match_dup 0))]
|
9951 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))"
|
9952 |
124 |
dgisselq |
+ [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])
|
9953 |
|
|
+;
|
9954 |
|
|
+;
|
9955 |
127 |
dgisselq |
+;
|
9956 |
124 |
dgisselq |
+; Match:
|
9957 |
127 |
dgisselq |
+; ADD $x,R0
|
9958 |
|
|
+; MOV A(R0),R1
|
9959 |
|
|
+; (CCREG is dead, and R0 is dead)
|
9960 |
|
|
+; Transform to:
|
9961 |
|
|
+; MOV (A+$x)(R0),R1
|
9962 |
|
|
+;
|
9963 |
|
|
+(define_peephole2
|
9964 |
|
|
+ [(parallel [
|
9965 |
|
|
+ (set (match_operand:SI 0 "register_operand")
|
9966 |
|
|
+ (plus:SI (match_dup 0)
|
9967 |
|
|
+ (match_operand 1 "zip_mvimm_operand_p")))
|
9968 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9969 |
|
|
+ (set (match_operand:SI 2 "register_operand")
|
9970 |
|
|
+ (plus:SI (match_dup 0)
|
9971 |
|
|
+ (match_operand 3 "zip_mvimm_operand_p")))
|
9972 |
|
|
+ ]
|
9973 |
|
|
+ "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
|
9974 |
|
|
+ &&(peep2_regno_dead_p(1,REGNO(operands[0])))
|
9975 |
|
|
+ &&(INTVAL(operands[1])+INTVAL(operands[3])<((1<<17)))
|
9976 |
|
|
+ &&(INTVAL(operands[1])+INTVAL(operands[3])>=-(1<<17))"
|
9977 |
|
|
+ [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
|
9978 |
|
|
+ "operands[3]=GEN_INT(INTVAL(operands[1])+INTVAL(operands[3]));")
|
9979 |
|
|
+;
|
9980 |
|
|
+;
|
9981 |
|
|
+;
|
9982 |
|
|
+; Match:
|
9983 |
124 |
dgisselq |
+; ADD $x,R0
|
9984 |
|
|
+; ADD R0,Rn
|
9985 |
|
|
+; (R0 is dead, if R0 is not Rn)
|
9986 |
|
|
+; Transform to:
|
9987 |
|
|
+; ADD $x(R0),Rn
|
9988 |
|
|
+;
|
9989 |
|
|
+(define_peephole2
|
9990 |
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
9991 |
|
|
+ (plus:SI (match_dup 0)
|
9992 |
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
9993 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
9994 |
|
|
+ (parallel [(set (match_operand:SI 2 "register_operand")
|
9995 |
|
|
+ (plus:SI (match_dup 2) (match_dup 0)))
|
9996 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
|
9997 |
|
|
+ ]
|
9998 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
|
9999 |
124 |
dgisselq |
+ [(parallel [(set (match_dup 2)
|
10000 |
|
|
+ (plus:SI (match_dup 2)
|
10001 |
|
|
+ (plus:SI (match_dup 0)
|
10002 |
|
|
+ (match_dup 1))))
|
10003 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
|
10004 |
|
|
+ ])
|
10005 |
|
|
+;
|
10006 |
|
|
+; Match:
|
10007 |
|
|
+; ADD $x,R0
|
10008 |
|
|
+; LOD -x(R0),R1
|
10009 |
|
|
+; Transform to:
|
10010 |
|
|
+; LOD (R0),R1
|
10011 |
|
|
+; ADD $x,R0
|
10012 |
|
|
+;
|
10013 |
|
|
+(define_peephole2
|
10014 |
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
10015 |
|
|
+ (plus:SI (match_dup 0)
|
10016 |
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
10017 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10018 |
|
|
+ (set (match_operand:SI 3 "register_operand")
|
10019 |
|
|
+ (mem:SI (plus:SI (match_dup 0)
|
10020 |
|
|
+ (match_operand 2 "zip_opb_immv_p"))))
|
10021 |
|
|
+ ]
|
10022 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
10023 |
124 |
dgisselq |
+ [(set (match_dup 3) (mem:SI (match_dup 0)))
|
10024 |
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
10025 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10026 |
|
|
+ ])
|
10027 |
127 |
dgisselq |
+(define_peephole2
|
10028 |
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
10029 |
|
|
+ (plus:SI (match_dup 0)
|
10030 |
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
10031 |
|
|
+ (clobber (reg:CC CC_REG))])
|
10032 |
|
|
+ (set (match_operand:SI 3 "register_operand")
|
10033 |
|
|
+ (mem:SI (plus:SI (match_dup 0)
|
10034 |
|
|
+ (match_operand 2 "zip_opb_immv_p"))))
|
10035 |
|
|
+ ]
|
10036 |
|
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
10037 |
|
|
+ [(set (match_dup 3) (mem:SI (match_dup 0)))
|
10038 |
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
10039 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10040 |
|
|
+ ])
|
10041 |
124 |
dgisselq |
+;
|
10042 |
|
|
+;
|
10043 |
|
|
+;
|
10044 |
|
|
+; Match:
|
10045 |
|
|
+; ADD $x,R0
|
10046 |
|
|
+; STO R1,-x(R0)
|
10047 |
|
|
+; Transform to:
|
10048 |
|
|
+; STO R1,(R0)
|
10049 |
|
|
+; ADD $x,R0
|
10050 |
|
|
+;
|
10051 |
|
|
+(define_peephole2
|
10052 |
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
10053 |
|
|
+ (plus:SI (match_dup 0)
|
10054 |
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
10055 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10056 |
|
|
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
|
10057 |
|
|
+ (match_operand:SI 3 "register_operand"))
|
10058 |
|
|
+ ]
|
10059 |
127 |
dgisselq |
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
10060 |
124 |
dgisselq |
+ [(set (mem:SI (match_dup 0)) (match_dup 3))
|
10061 |
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
10062 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10063 |
|
|
+ ])
|
10064 |
127 |
dgisselq |
+(define_peephole2
|
10065 |
|
|
+ [(parallel [(set (match_operand:SI 0 "register_operand")
|
10066 |
|
|
+ (plus:SI (match_dup 0)
|
10067 |
|
|
+ (match_operand 1 "zip_opb_immv_p")))
|
10068 |
|
|
+ (clobber (reg:CC CC_REG))])
|
10069 |
|
|
+ (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
|
10070 |
|
|
+ (match_operand:SI 3 "register_operand"))
|
10071 |
|
|
+ ]
|
10072 |
|
|
+ "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
|
10073 |
|
|
+ [(set (mem:SI (match_dup 0)) (match_dup 3))
|
10074 |
|
|
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
10075 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10076 |
|
|
+ ])
|
10077 |
124 |
dgisselq |
+;
|
10078 |
|
|
+;
|
10079 |
|
|
+; Match:
|
10080 |
|
|
+; ADD $x,R0
|
10081 |
|
|
+; ANY R1,R2 (destination is not R0, source does not reference R0)
|
10082 |
|
|
+; ADD R0,Rn (could be 1 or 2, not 0)
|
10083 |
|
|
+; (R0 is dead)
|
10084 |
|
|
+; Transform to:
|
10085 |
|
|
+; ANY R1,R2
|
10086 |
|
|
+; ADD $x(R0),Rn
|
10087 |
|
|
+;
|
10088 |
|
|
+;
|
10089 |
|
|
+;
|
10090 |
127 |
dgisselq |
+; Match:
|
10091 |
|
|
+; MOV R1,R0
|
10092 |
|
|
+; AND #/R2,R0
|
10093 |
|
|
+; (Ry dead ...)
|
10094 |
|
|
+; Transform to:
|
10095 |
|
|
+; TEST #/Rz,Rx
|
10096 |
124 |
dgisselq |
+;
|
10097 |
127 |
dgisselq |
+(define_peephole2
|
10098 |
|
|
+ [(set (match_operand:SI 0 "register_operand")
|
10099 |
|
|
+ (match_operand:SI 1 "register_operand"))
|
10100 |
|
|
+ (parallel [(set (match_dup 0)
|
10101 |
|
|
+ (and:SI (match_dup 0)
|
10102 |
|
|
+ (match_operand:SI 2 "zip_opb_single_operand_p")))
|
10103 |
|
|
+ (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
|
10104 |
|
|
+ ]
|
10105 |
|
|
+ "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
|
10106 |
|
|
+ [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_dup 1) (match_dup 2))
|
10107 |
|
|
+ (const_int 0)))])
|
10108 |
|
|
+;
|
10109 |
|
|
+; Match:
|
10110 |
|
|
+; (call ...
|
10111 |
|
|
+; (set (pc) (label))
|
10112 |
|
|
+; or (in asm)
|
10113 |
|
|
+; MOV .Lcallx(PC),R0
|
10114 |
|
|
+; BRA (somewhere)
|
10115 |
|
|
+; .Lcallx
|
10116 |
|
|
+; BRA (somewhere-else)
|
10117 |
|
|
+; Transform to:
|
10118 |
|
|
+;
|
10119 |
|
|
+; (sequence [(call ...
|
10120 |
|
|
+; (set (pc) (label))])
|
10121 |
|
|
+; or (in asm)
|
10122 |
|
|
+; "LDI (somewhere-else),R0
|
10123 |
|
|
+; BRA subroutine"
|
10124 |
|
|
+;
|
10125 |
|
|
+; While the following looks good, it doesnt work. My guess is that the reason
|
10126 |
|
|
+; why it doesnt work is that the jump at the end crosses basic block boundaries.
|
10127 |
|
|
+;
|
10128 |
|
|
+;(define_insn "void_call_mem_unspec"
|
10129 |
|
|
+; [(call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p" ""))] UNSPEC_RAW_CALL)
|
10130 |
|
|
+; (match_operand 1 "const_int_operand" "n"))
|
10131 |
|
|
+; (clobber (reg:SI RTN_REG))
|
10132 |
|
|
+; (clobber (reg:CC CC_REG))]
|
10133 |
|
|
+; ""
|
10134 |
|
|
+; "BRA\t%0,PC"
|
10135 |
|
|
+; [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
10136 |
|
|
+;(define_peephole2
|
10137 |
|
|
+; [(parallel [(call (mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))
|
10138 |
|
|
+; (match_operand 1 "const_int_operand"))
|
10139 |
|
|
+; (clobber (reg:SI RTN_REG))
|
10140 |
|
|
+; (clobber (reg:CC CC_REG))])
|
10141 |
|
|
+; ; The match operand for the (set (pc) ...) cannot have anything but
|
10142 |
|
|
+; ; VOIDmode, or it wont match.
|
10143 |
|
|
+; (set (pc) (match_operand:VOID 2 "zip_const_address_operand_p"))]
|
10144 |
|
|
+; ""
|
10145 |
|
|
+; [(set (reg:SI RTN_REG) (match_dup 2))
|
10146 |
|
|
+; (call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))] UNSPEC_RAW_CALL)
|
10147 |
|
|
+; (match_operand 1 "const_int_operand"))
|
10148 |
|
|
+; (use (reg:SI RTN_REG))
|
10149 |
|
|
+; (clobber (reg:SI RTN_REG))
|
10150 |
|
|
+; (clobber (reg:CC CC_REG))]
|
10151 |
|
|
+; "fprintf(stderr, \"CALL-JUMP Matched\");")
|
10152 |
|
|
+;
|
10153 |
|
|
+;
|
10154 |
|
|
+;
|
10155 |
|
|
+; So, the following *should* have worked as well. However, this falls apart
|
10156 |
|
|
+; because the 'final' routine can't tell if we are calling a subroutine in this
|
10157 |
|
|
+; function or not.
|
10158 |
|
|
+;
|
10159 |
|
|
+;(define_peephole
|
10160 |
|
|
+ ;[(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p"))
|
10161 |
|
|
+ ;(match_operand 1 "const_int_operand"))
|
10162 |
|
|
+ ;(clobber (reg:SI RTN_REG))
|
10163 |
|
|
+ ;(clobber (reg:CC CC_REG))])
|
10164 |
|
|
+ ;(set (pc) (label_ref (match_operand 2 "")))]
|
10165 |
|
|
+ ;""
|
10166 |
|
|
+ ;"LDI\t%2,R0\;BRA\t%0"
|
10167 |
|
|
+ ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
|
10168 |
|
|
+;
|
10169 |
124 |
dgisselq |
+; and for
|
10170 |
|
|
+; BRA target
|
10171 |
|
|
+; BRA target ; two branches to the same identical target in a row ...
|
10172 |
|
|
+;
|
10173 |
|
|
+;
|
10174 |
|
|
+;
|
10175 |
102 |
dgisselq |
+; STILL MISSING:
|
10176 |
|
|
+; SYSCALL(ID)
|
10177 |
|
|
+; MOV %ID,R0
|
10178 |
|
|
+; CLR CC
|
10179 |
|
|
+; cmove ... the conditional move, created from a
|
10180 |
|
|
+; (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
|
10181 |
|
|
+; pattern
|
10182 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
|
10183 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def 1969-12-31 19:00:00.000000000 -0500
|
10184 |
111 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def 2016-03-08 12:10:21.982586940 -0500
|
10185 |
|
|
@@ -0,0 +1,23 @@
|
10186 |
102 |
dgisselq |
+/*
|
10187 |
|
|
+ * Commends in C-long comment form
|
10188 |
|
|
+ * class
|
10189 |
|
|
+ * Mode = "SI"
|
10190 |
|
|
+ * PRECISION, BYTESIZE, COUNT ??
|
10191 |
|
|
+ * FORMAT
|
10192 |
|
|
+ * EXPR
|
10193 |
111 |
dgisselq |
+ *
|
10194 |
|
|
+ * The manual says I need to define BITS_PER_UNIT here.
|
10195 |
102 |
dgisselq |
+ */
|
10196 |
|
|
+// INT_MODE(QI, 1);
|
10197 |
|
|
+// INT_MODE(HI, 1);
|
10198 |
|
|
+// INT_MODE(SI, 1);
|
10199 |
|
|
+// INT_MODE(DI, 2);
|
10200 |
|
|
+
|
10201 |
|
|
+// FLOAT_MODE(SF, 1, ieee_single_format);
|
10202 |
|
|
+// FLOAT_MODE(DF, 2, ieee_single_format);
|
10203 |
|
|
+
|
10204 |
|
|
+// We cannot override machmodes.def from here. Thus, even though our QI,
|
10205 |
|
|
+// HI, and SI modes are all 1-byte, we cant set them that way here. The
|
10206 |
|
|
+// change needed to be made in machmodes.def. Hence, here is a target
|
10207 |
|
|
+// configuration change--in machmodes.def--that properly belonged in the
|
10208 |
|
|
+// config directory.
|
10209 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
|
10210 |
|
|
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h 1969-12-31 19:00:00.000000000 -0500
|
10211 |
142 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h 2016-05-09 11:16:54.734258166 -0400
|
10212 |
|
|
@@ -0,0 +1,83 @@
|
10213 |
102 |
dgisselq |
+////////////////////////////////////////////////////////////////////////////////
|
10214 |
|
|
+//
|
10215 |
|
|
+// Filename: zip-protos.h
|
10216 |
|
|
+//
|
10217 |
|
|
+// Project: Zip CPU backend for the GNU Compiler Collection
|
10218 |
|
|
+//
|
10219 |
|
|
+// Purpose:
|
10220 |
|
|
+//
|
10221 |
|
|
+// Creator: Dan Gisselquist, Ph.D.
|
10222 |
|
|
+// Gisselquist Technology, LLC
|
10223 |
|
|
+//
|
10224 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
10225 |
|
|
+//
|
10226 |
|
|
+// Copyright (C) 2016, Gisselquist Technology, LLC
|
10227 |
|
|
+//
|
10228 |
|
|
+// This program is free software (firmware): you can redistribute it and/or
|
10229 |
|
|
+// modify it under the terms of the GNU General Public License as published
|
10230 |
|
|
+// by the Free Software Foundation, either version 3 of the License, or (at
|
10231 |
|
|
+// your option) any later version.
|
10232 |
|
|
+//
|
10233 |
|
|
+// This program is distributed in the hope that it will be useful, but WITHOUT
|
10234 |
|
|
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
|
10235 |
|
|
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
10236 |
|
|
+// for more details.
|
10237 |
|
|
+//
|
10238 |
|
|
+// You should have received a copy of the GNU General Public License along
|
10239 |
|
|
+// with this program. (It's in the $(ROOT)/doc directory, run make with no
|
10240 |
|
|
+// target there if the PDF file isn't present.) If not, see
|
10241 |
|
|
+// <http://www.gnu.org/licenses/> for a copy.
|
10242 |
|
|
+//
|
10243 |
|
|
+// License: GPL, v3, as defined and found on www.gnu.org,
|
10244 |
|
|
+// http://www.gnu.org/licenses/gpl.html
|
10245 |
|
|
+//
|
10246 |
|
|
+//
|
10247 |
|
|
+////////////////////////////////////////////////////////////////////////////////
|
10248 |
|
|
+#ifndef ZIP_PROTOS_H
|
10249 |
|
|
+#define ZIP_PROTOS_H
|
10250 |
|
|
+
|
10251 |
127 |
dgisselq |
+extern bool zip_supported_condition(int c);
|
10252 |
102 |
dgisselq |
+extern void zip_expand_prologue(void);
|
10253 |
|
|
+extern void zip_expand_epilogue(void);
|
10254 |
142 |
dgisselq |
+extern bool zip_expand_movsicc(rtx,rtx,rtx,rtx);
|
10255 |
102 |
dgisselq |
+extern int zip_initial_elimination_offset(int, int);
|
10256 |
|
|
+extern void zip_print_operand(FILE *, rtx, int);
|
10257 |
|
|
+extern void zip_print_operand_address(FILE *, rtx);
|
10258 |
|
|
+extern enum reg_class zip_reg_class(int);
|
10259 |
|
|
+extern rtx zip_return_addr_rtx(int, rtx);
|
10260 |
|
|
+extern int zip_num_arg_regs(enum machine_mode, tree);
|
10261 |
|
|
+
|
10262 |
|
|
+extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
|
10263 |
122 |
dgisselq |
+
|
10264 |
|
|
+#ifdef HAVE_cc0
|
10265 |
102 |
dgisselq |
+extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
|
10266 |
122 |
dgisselq |
+#else
|
10267 |
|
|
+extern void zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
|
10268 |
|
|
+#endif
|
10269 |
102 |
dgisselq |
+extern int zip_address_operand(rtx op);
|
10270 |
|
|
+extern int zip_const_address_operand(rtx op);
|
10271 |
|
|
+extern bool zip_gen_move_rtl(rtx, rtx);
|
10272 |
|
|
+extern bool zip_use_return_insn(void);
|
10273 |
|
|
+extern const char *zip_set_zero_or_one(rtx, rtx);
|
10274 |
|
|
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
|
10275 |
|
|
+
|
10276 |
127 |
dgisselq |
+extern int zip_insn_sets_cc(rtx_insn *insn);
|
10277 |
|
|
+extern int zip_is_conditional(rtx_insn *insn);
|
10278 |
102 |
dgisselq |
+extern int zip_ct_address_operand(rtx op);
|
10279 |
111 |
dgisselq |
+extern int zip_pd_opb_operand(rtx op);
|
10280 |
102 |
dgisselq |
+extern int zip_pd_mov_operand(rtx op);
|
10281 |
111 |
dgisselq |
+extern int zip_pd_imm_operand(rtx op);
|
10282 |
|
|
+extern int zip_pd_mvimm_operand(rtx op);
|
10283 |
102 |
dgisselq |
+extern int zip_ct_const_address_operand(rtx op);
|
10284 |
|
|
+extern int zip_pd_const_address_operand(rtx op);
|
10285 |
|
|
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
|
10286 |
|
|
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
|
10287 |
|
|
+
|
10288 |
122 |
dgisselq |
+extern void zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
|
10289 |
|
|
+extern void zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
|
10290 |
|
|
+extern void zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
|
10291 |
|
|
+extern void zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
|
10292 |
142 |
dgisselq |
+extern void zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
|
10293 |
122 |
dgisselq |
+
|
10294 |
102 |
dgisselq |
+#endif
|
10295 |
|
|
+
|
10296 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
|
10297 |
|
|
--- gcc-5.3.0-original/gcc/config.gcc 2015-09-10 10:17:53.000000000 -0400
|
10298 |
|
|
+++ gcc-5.3.0-zip/gcc/config.gcc 2016-02-14 00:53:37.389411987 -0500
|
10299 |
|
|
@@ -479,6 +479,10 @@
|
10300 |
|
|
tilepro*-*-*)
|
10301 |
|
|
cpu_type=tilepro
|
10302 |
|
|
;;
|
10303 |
|
|
+zip*)
|
10304 |
|
|
+ cpu_type=zip
|
10305 |
|
|
+ tmake_file=zip/t-zip
|
10306 |
|
|
+ ;;
|
10307 |
|
|
esac
|
10308 |
|
|
|
10309 |
|
|
tm_file=${cpu_type}/${cpu_type}.h
|
10310 |
|
|
@@ -2972,6 +2976,15 @@
|
10311 |
|
|
c_target_objs="m32c-pragma.o"
|
10312 |
|
|
cxx_target_objs="m32c-pragma.o"
|
10313 |
|
|
;;
|
10314 |
|
|
+zip-*-netbsd*)
|
10315 |
|
|
+ tm_file="${tm_file} elfos.h netbsd.h netbsd-elf.h zip/netbsd.h"
|
10316 |
|
|
+ tmake_file="${tmake_file} zip/t-zip"
|
10317 |
|
|
+ ;;
|
10318 |
|
|
+zip*)
|
10319 |
|
|
+ target_has_targetm_common=yes
|
10320 |
|
|
+ tm_file="elfos.h newlib-stdint.h ${tm_file}"
|
10321 |
|
|
+ tmake_file="${tmake_file} zip/t-zip"
|
10322 |
|
|
+ ;;
|
10323 |
|
|
*)
|
10324 |
|
|
echo "*** Configuration ${target} not supported" 1>&2
|
10325 |
|
|
exit 1
|
10326 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
|
10327 |
|
|
--- gcc-5.3.0-original/gcc/cse.c 2015-02-03 15:41:38.000000000 -0500
|
10328 |
138 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/cse.c 2016-05-04 11:07:38.874831028 -0400
|
10329 |
|
|
@@ -70,6 +70,7 @@
|
10330 |
|
|
#include "dbgcnt.h"
|
10331 |
|
|
#include "rtl-iter.h"
|
10332 |
|
|
|
10333 |
|
|
+
|
10334 |
|
|
/* The basic idea of common subexpression elimination is to go
|
10335 |
|
|
through the code, keeping a record of expressions that would
|
10336 |
|
|
have the same value at the current scan point, and replacing
|
10337 |
|
|
@@ -634,6 +635,16 @@
|
10338 |
102 |
dgisselq |
|
10339 |
|
|
/* Nonzero if X has the form (PLUS frame-pointer integer). */
|
10340 |
|
|
|
10341 |
111 |
dgisselq |
+// #define DO_ZIP_DEBUGS
|
10342 |
102 |
dgisselq |
+#ifdef DO_ZIP_DEBUGS
|
10343 |
|
|
+#include <stdio.h>
|
10344 |
138 |
dgisselq |
+extern void zip_debug_rtx(const_rtx);
|
10345 |
|
|
+extern void zip_debug_rtx_pfx(char *, const_rtx);
|
10346 |
102 |
dgisselq |
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s\n", STR); zip_debug_rtx(RTX); } while(0)
|
10347 |
|
|
+#else
|
10348 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
10349 |
|
|
+#endif
|
10350 |
|
|
+
|
10351 |
|
|
static bool
|
10352 |
|
|
fixed_base_plus_p (rtx x)
|
10353 |
|
|
{
|
10354 |
138 |
dgisselq |
@@ -2898,6 +2909,7 @@
|
10355 |
102 |
dgisselq |
validate_canon_reg (&XVECEXP (x, i, j), insn);
|
10356 |
|
|
}
|
10357 |
|
|
|
10358 |
|
|
+ ZIP_DEBUG_LINE("CANON-REG-RTN", x);
|
10359 |
|
|
return x;
|
10360 |
|
|
}
|
10361 |
|
|
|
10362 |
138 |
dgisselq |
@@ -3125,6 +3137,8 @@
|
10363 |
|
|
rtx new_rtx = 0;
|
10364 |
|
|
int changed = 0;
|
10365 |
|
|
|
10366 |
|
|
+ZIP_DEBUG_LINE("CSE:FOLD-RTX", insn);
|
10367 |
|
|
+
|
10368 |
|
|
/* Operands of X. */
|
10369 |
|
|
/* Workaround -Wmaybe-uninitialized false positive during
|
10370 |
|
|
profiledbootstrap by initializing them. */
|
10371 |
|
|
@@ -3144,14 +3158,16 @@
|
10372 |
102 |
dgisselq |
if (x == 0)
|
10373 |
|
|
return x;
|
10374 |
|
|
|
10375 |
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX", x);
|
10376 |
|
|
/* Try to perform some initial simplifications on X. */
|
10377 |
|
|
code = GET_CODE (x);
|
10378 |
|
|
switch (code)
|
10379 |
|
|
{
|
10380 |
|
|
case MEM:
|
10381 |
|
|
case SUBREG:
|
10382 |
|
|
- if ((new_rtx = equiv_constant (x)) != NULL_RTX)
|
10383 |
|
|
- return new_rtx;
|
10384 |
|
|
+ if ((new_rtx = equiv_constant (x)) != NULL_RTX) {
|
10385 |
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX-NEW", new_rtx);
|
10386 |
|
|
+ return new_rtx; }
|
10387 |
|
|
return x;
|
10388 |
|
|
|
10389 |
|
|
case CONST:
|
10390 |
138 |
dgisselq |
@@ -3208,6 +3224,8 @@
|
10391 |
102 |
dgisselq |
rtx folded_arg = XEXP (x, i), const_arg;
|
10392 |
|
|
machine_mode mode_arg = GET_MODE (folded_arg);
|
10393 |
|
|
|
10394 |
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX-ARG = ", folded_arg);
|
10395 |
|
|
+
|
10396 |
|
|
switch (GET_CODE (folded_arg))
|
10397 |
|
|
{
|
10398 |
|
|
case MEM:
|
10399 |
138 |
dgisselq |
@@ -3317,6 +3335,7 @@
|
10400 |
102 |
dgisselq |
}
|
10401 |
|
|
|
10402 |
|
|
apply_change_group ();
|
10403 |
|
|
+ ZIP_DEBUG_LINE("FOLD-RTX-CANONICALIZED = ", insn);
|
10404 |
|
|
}
|
10405 |
|
|
|
10406 |
|
|
/* If X is an arithmetic operation, see if we can simplify it. */
|
10407 |
138 |
dgisselq |
@@ -4203,6 +4222,7 @@
|
10408 |
102 |
dgisselq |
{
|
10409 |
|
|
rtx dest = SET_DEST (set);
|
10410 |
|
|
rtx src = SET_SRC (set);
|
10411 |
|
|
+ ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG", insn);
|
10412 |
|
|
|
10413 |
|
|
if (REG_P (dest)
|
10414 |
|
|
&& REG_P (src) && ! HARD_REGISTER_P (src)
|
10415 |
138 |
dgisselq |
@@ -4258,6 +4278,7 @@
|
10416 |
102 |
dgisselq |
}
|
10417 |
|
|
}
|
10418 |
|
|
}
|
10419 |
|
|
+ ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG, done", insn);
|
10420 |
|
|
}
|
10421 |
|
|
|
10422 |
|
|
/* Record all the SETs in this instruction into SETS_PTR,
|
10423 |
138 |
dgisselq |
@@ -4351,6 +4372,7 @@
|
10424 |
102 |
dgisselq |
rtx tem;
|
10425 |
|
|
rtx x = PATTERN (insn);
|
10426 |
|
|
int i;
|
10427 |
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN", insn);
|
10428 |
|
|
|
10429 |
|
|
if (CALL_P (insn))
|
10430 |
|
|
{
|
10431 |
138 |
dgisselq |
@@ -4364,6 +4386,7 @@
|
10432 |
102 |
dgisselq |
canon_reg (SET_SRC (x), insn);
|
10433 |
|
|
apply_change_group ();
|
10434 |
|
|
fold_rtx (SET_SRC (x), insn);
|
10435 |
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN, was set:", insn);
|
10436 |
|
|
}
|
10437 |
|
|
else if (GET_CODE (x) == CLOBBER)
|
10438 |
|
|
{
|
10439 |
138 |
dgisselq |
@@ -4400,6 +4423,7 @@
|
10440 |
102 |
dgisselq |
canon_reg (PATTERN (insn), insn);
|
10441 |
|
|
else if (GET_CODE (x) == PARALLEL)
|
10442 |
|
|
{
|
10443 |
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN/parallel", insn);
|
10444 |
|
|
for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
|
10445 |
|
|
{
|
10446 |
|
|
rtx y = XVECEXP (x, 0, i);
|
10447 |
138 |
dgisselq |
@@ -4491,6 +4515,7 @@
|
10448 |
102 |
dgisselq |
|
10449 |
|
|
The result of apply_change_group can be ignored; see canon_reg. */
|
10450 |
|
|
|
10451 |
|
|
+ ZIP_DEBUG_LINE("CANONICALIZE-INSN/done", insn);
|
10452 |
|
|
apply_change_group ();
|
10453 |
|
|
}
|
10454 |
|
|
|
10455 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/defaults.h gcc-5.3.0-zip/gcc/defaults.h
|
10456 |
|
|
--- gcc-5.3.0-original/gcc/defaults.h 2015-03-03 10:04:02.000000000 -0500
|
10457 |
|
|
+++ gcc-5.3.0-zip/gcc/defaults.h 2016-02-06 16:57:53.939410173 -0500
|
10458 |
|
|
@@ -480,6 +480,8 @@
|
10459 |
|
|
#define LOG2_BITS_PER_UNIT 3
|
10460 |
|
|
#elif BITS_PER_UNIT == 16
|
10461 |
|
|
#define LOG2_BITS_PER_UNIT 4
|
10462 |
|
|
+#elif BITS_PER_UNIT == 32
|
10463 |
|
|
+#define LOG2_BITS_PER_UNIT 5
|
10464 |
|
|
#else
|
10465 |
|
|
#error Unknown BITS_PER_UNIT
|
10466 |
|
|
#endif
|
10467 |
127 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/df-scan.c gcc-5.3.0-zip/gcc/df-scan.c
|
10468 |
|
|
--- gcc-5.3.0-original/gcc/df-scan.c 2015-01-09 15:18:42.000000000 -0500
|
10469 |
|
|
+++ gcc-5.3.0-zip/gcc/df-scan.c 2016-04-14 16:12:03.614777002 -0400
|
10470 |
|
|
@@ -61,6 +61,14 @@
|
10471 |
|
|
|
10472 |
|
|
typedef struct df_mw_hardreg *df_mw_hardreg_ptr;
|
10473 |
|
|
|
10474 |
|
|
+// #define DO_ZIP_DEBUGS
|
10475 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
10476 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
10477 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
10478 |
|
|
+#else
|
10479 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
10480 |
|
|
+#endif
|
10481 |
|
|
+
|
10482 |
|
|
|
10483 |
|
|
#ifndef HAVE_epilogue
|
10484 |
|
|
#define HAVE_epilogue 0
|
10485 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log
|
10486 |
|
|
--- gcc-5.3.0-original/gcc/doc/gcc.log 1969-12-31 19:00:00.000000000 -0500
|
10487 |
|
|
+++ gcc-5.3.0-zip/gcc/doc/gcc.log 2016-01-30 15:18:43.262724969 -0500
|
10488 |
|
|
@@ -0,0 +1,214 @@
|
10489 |
|
|
+This is pdfTeX, Version 3.1415926-2.5-1.40.14 (TeX Live 2013/Debian) (format=pdfetex 2014.5.7) 30 JAN 2016 15:17
|
10490 |
|
|
+entering extended mode
|
10491 |
|
|
+ restricted \write18 enabled.
|
10492 |
|
|
+ file:line:error style messages enabled.
|
10493 |
|
|
+ %&-line parsing enabled.
|
10494 |
|
|
+**\catcode126=12 \def\normaltilde{~}\catcode126=13 \let~\normaltilde \input ./
|
10495 |
|
|
+gcc.texi
|
10496 |
|
|
+(./gcc.texi (/usr/share/texmf/tex/texinfo/texinfo.tex
|
10497 |
|
|
+Loading texinfo [version 2013-09-11.11]:
|
10498 |
|
|
+\bindingoffset=\dimen16
|
10499 |
|
|
+\normaloffset=\dimen17
|
10500 |
|
|
+\pagewidth=\dimen18
|
10501 |
|
|
+\pageheight=\dimen19
|
10502 |
|
|
+\outerhsize=\dimen20
|
10503 |
|
|
+\outervsize=\dimen21
|
10504 |
|
|
+\cornerlong=\dimen22
|
10505 |
|
|
+\cornerthick=\dimen23
|
10506 |
|
|
+\topandbottommargin=\dimen24
|
10507 |
|
|
+\headlinebox=\box16
|
10508 |
|
|
+\footlinebox=\box17
|
10509 |
|
|
+\margin=\insert252
|
10510 |
|
|
+\EMsimple=\toks13
|
10511 |
|
|
+\groupbox=\box18
|
10512 |
|
|
+\groupinvalidhelp=\toks14
|
10513 |
|
|
+\mil=\dimen25
|
10514 |
|
|
+\exdentamount=\skip18
|
10515 |
|
|
+\inmarginspacing=\skip19
|
10516 |
|
|
+\centerpenalty=\count27
|
10517 |
|
|
+ pdf,
|
10518 |
|
|
+\tempnum=\count28
|
10519 |
|
|
+\lnkcount=\count29
|
10520 |
|
|
+\filename=\toks15
|
10521 |
|
|
+\filenamelength=\count30
|
10522 |
|
|
+\pgn=\count31
|
10523 |
|
|
+\toksA=\toks16
|
10524 |
|
|
+\toksB=\toks17
|
10525 |
|
|
+\toksC=\toks18
|
10526 |
|
|
+\toksD=\toks19
|
10527 |
|
|
+\boxA=\box19
|
10528 |
|
|
+\countA=\count32
|
10529 |
|
|
+\nopdfimagehelp=\toks20
|
10530 |
|
|
+ fonts,
|
10531 |
|
|
+\sffam=\fam8
|
10532 |
|
|
+\textleading=\dimen26
|
10533 |
|
|
+ markup,
|
10534 |
|
|
+\fontdepth=\count33
|
10535 |
|
|
+ glyphs,
|
10536 |
|
|
+\errorbox=\box20
|
10537 |
|
|
+
|
10538 |
|
|
+page headings,
|
10539 |
|
|
+\titlepagetopglue=\skip20
|
10540 |
|
|
+\titlepagebottomglue=\skip21
|
10541 |
|
|
+\evenheadline=\toks21
|
10542 |
|
|
+\oddheadline=\toks22
|
10543 |
|
|
+\evenfootline=\toks23
|
10544 |
|
|
+\oddfootline=\toks24
|
10545 |
|
|
+ tables,
|
10546 |
|
|
+\tableindent=\dimen27
|
10547 |
|
|
+\itemindent=\dimen28
|
10548 |
|
|
+\itemmargin=\dimen29
|
10549 |
|
|
+\itemmax=\dimen30
|
10550 |
|
|
+\itemno=\count34
|
10551 |
|
|
+\multitableparskip=\skip22
|
10552 |
|
|
+\multitableparindent=\skip23
|
10553 |
|
|
+\multitablecolspace=\dimen31
|
10554 |
|
|
+\multitablelinespace=\skip24
|
10555 |
|
|
+\colcount=\count35
|
10556 |
|
|
+\everytab=\toks25
|
10557 |
|
|
+ conditionals,
|
10558 |
|
|
+\doignorecount=\count36
|
10559 |
|
|
+ indexing,
|
10560 |
|
|
+\whatsitskip=\skip25
|
10561 |
|
|
+\whatsitpenalty=\count37
|
10562 |
|
|
+\secondaryindent=\skip26
|
10563 |
|
|
+\partialpage=\box21
|
10564 |
|
|
+\doublecolumnhsize=\dimen32
|
10565 |
|
|
+ sectioning,
|
10566 |
|
|
+\unnumberedno=\count38
|
10567 |
|
|
+\chapno=\count39
|
10568 |
|
|
+\secno=\count40
|
10569 |
|
|
+\subsecno=\count41
|
10570 |
|
|
+\subsubsecno=\count42
|
10571 |
|
|
+\appendixno=\count43
|
10572 |
|
|
+\absseclevel=\count44
|
10573 |
|
|
+\secbase=\count45
|
10574 |
|
|
+\chapheadingskip=\skip27
|
10575 |
|
|
+\secheadingskip=\skip28
|
10576 |
|
|
+\subsecheadingskip=\skip29
|
10577 |
|
|
+ toc,
|
10578 |
|
|
+\tocfile=\write0
|
10579 |
|
|
+\contentsrightmargin=\skip30
|
10580 |
|
|
+\savepageno=\count46
|
10581 |
|
|
+\lastnegativepageno=\count47
|
10582 |
|
|
+\tocindent=\dimen33
|
10583 |
|
|
+ environments,
|
10584 |
|
|
+\lispnarrowing=\skip31
|
10585 |
|
|
+\envskipamount=\skip32
|
10586 |
|
|
+\circthick=\dimen34
|
10587 |
|
|
+\cartouter=\dimen35
|
10588 |
|
|
+\cartinner=\dimen36
|
10589 |
|
|
+\normbskip=\skip33
|
10590 |
|
|
+\normpskip=\skip34
|
10591 |
|
|
+\normlskip=\skip35
|
10592 |
|
|
+\lskip=\skip36
|
10593 |
|
|
+\rskip=\skip37
|
10594 |
|
|
+\nonfillparindent=\dimen37
|
10595 |
|
|
+\tabw=\dimen38
|
10596 |
|
|
+\verbbox=\box22
|
10597 |
|
|
+
|
10598 |
|
|
+defuns,
|
10599 |
|
|
+\defbodyindent=\skip38
|
10600 |
|
|
+\defargsindent=\skip39
|
10601 |
|
|
+\deflastargmargin=\skip40
|
10602 |
|
|
+\defunpenalty=\count48
|
10603 |
|
|
+\parencount=\count49
|
10604 |
|
|
+\brackcount=\count50
|
10605 |
|
|
+ macros,
|
10606 |
|
|
+\paramno=\count51
|
10607 |
|
|
+\macname=\toks26
|
10608 |
|
|
+ cross references,
|
10609 |
|
|
+\auxfile=\write1
|
10610 |
|
|
+\savesfregister=\count52
|
10611 |
|
|
+\toprefbox=\box23
|
10612 |
|
|
+\printedrefnamebox=\box24
|
10613 |
|
|
+\infofilenamebox=\box25
|
10614 |
|
|
+\printedmanualbox=\box26
|
10615 |
|
|
+ insertions,
|
10616 |
|
|
+\footnoteno=\count53
|
10617 |
|
|
+\SAVEfootins=\box27
|
10618 |
|
|
+\SAVEmargin=\box28
|
10619 |
|
|
+
|
10620 |
|
|
+(/usr/share/texlive/texmf-dist/tex/generic/epsf/epsf.tex
|
10621 |
|
|
+This is `epsf.tex' v2.7.4 <14 February 2011>
|
10622 |
|
|
+\epsffilein=\read1
|
10623 |
|
|
+\epsfframemargin=\dimen39
|
10624 |
|
|
+\epsfframethickness=\dimen40
|
10625 |
|
|
+\epsfrsize=\dimen41
|
10626 |
|
|
+\epsftmp=\dimen42
|
10627 |
|
|
+\epsftsize=\dimen43
|
10628 |
|
|
+\epsfxsize=\dimen44
|
10629 |
|
|
+\epsfysize=\dimen45
|
10630 |
|
|
+\pspoints=\dimen46
|
10631 |
|
|
+)
|
10632 |
|
|
+\noepsfhelp=\toks27
|
10633 |
|
|
+ localization,
|
10634 |
|
|
+\nolanghelp=\toks28
|
10635 |
|
|
+\countUTFx=\count54
|
10636 |
|
|
+\countUTFy=\count55
|
10637 |
|
|
+\countUTFz=\count56
|
10638 |
|
|
+ formatting,
|
10639 |
|
|
+\defaultparindent=\dimen47
|
10640 |
|
|
+ and turning on texinfo input format.)
|
10641 |
|
|
+\openout1 = `gcc.aux'.
|
10642 |
|
|
+
|
10643 |
|
|
+@cpindfile=@write2
|
10644 |
|
|
+@fnindfile=@write3
|
10645 |
|
|
+@vrindfile=@write4
|
10646 |
|
|
+@tpindfile=@write5
|
10647 |
|
|
+@kyindfile=@write6
|
10648 |
|
|
+@pgindfile=@write7
|
10649 |
|
|
+texinfo.tex: doing @include of gcc-common.texi
|
10650 |
|
|
+
|
10651 |
|
|
+
|
10652 |
|
|
+./gcc.texi:25: I can't find file `gcc-common.texi'.
|
10653 |
|
|
+@temp ->@input gcc-common.texi
|
10654 |
|
|
+
|
10655 |
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
10656 |
|
|
+ @popthisfilestack
|
10657 |
|
|
+l.25 @include gcc-common.texi
|
10658 |
|
|
+
|
10659 |
|
|
+(Press Enter to retry, or Control-D to exit)
|
10660 |
|
|
+Please type another input file name: include/gcc-common.texi
|
10661 |
|
|
+(./include/gcc-common.texi
|
10662 |
|
|
+texinfo.tex: doing @include of gcc-vers.texi
|
10663 |
|
|
+
|
10664 |
|
|
+
|
10665 |
|
|
+./include/gcc-common.texi:11: I can't find file `gcc-vers.texi'.
|
10666 |
|
|
+@temp ->@input gcc-vers.texi
|
10667 |
|
|
+
|
10668 |
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
10669 |
|
|
+ @popthisfilestack
|
10670 |
|
|
+l.11 @include gcc-vers.texi
|
10671 |
|
|
+
|
10672 |
|
|
+(Press Enter to retry, or Control-D to exit)
|
10673 |
|
|
+Please type another input file name: include/gcc-vers.texi
|
10674 |
|
|
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
|
10675 |
|
|
+@temp ->@input gcc-vers.texi
|
10676 |
|
|
+
|
10677 |
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
10678 |
|
|
+ @popthisfilestack
|
10679 |
|
|
+l.11 @include gcc-vers.texi
|
10680 |
|
|
+
|
10681 |
|
|
+(Press Enter to retry, or Control-D to exit)
|
10682 |
|
|
+Please type another input file name:
|
10683 |
|
|
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
|
10684 |
|
|
+@temp ->@input gcc-vers.texi
|
10685 |
|
|
+
|
10686 |
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
10687 |
|
|
+ @popthisfilestack
|
10688 |
|
|
+l.11 @include gcc-vers.texi
|
10689 |
|
|
+
|
10690 |
|
|
+(Press Enter to retry, or Control-D to exit)
|
10691 |
|
|
+Please type another input file name:
|
10692 |
|
|
+./include/gcc-common.texi:11: Emergency stop.
|
10693 |
|
|
+@temp ->@input gcc-vers.texi
|
10694 |
|
|
+
|
10695 |
|
|
+@includezzz ...and @input #1 }@expandafter }@temp
|
10696 |
|
|
+ @popthisfilestack
|
10697 |
|
|
+l.11 @include gcc-vers.texi
|
10698 |
|
|
+
|
10699 |
|
|
+End of file on the terminal!
|
10700 |
|
|
+
|
10701 |
|
|
+./include/gcc-common.texi:11: ==> Fatal error occurred, no output PDF file pro
|
10702 |
|
|
+duced!
|
10703 |
117 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c
|
10704 |
|
|
--- gcc-5.3.0-original/gcc/emit-rtl.c 2015-08-05 07:20:59.000000000 -0400
|
10705 |
138 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/emit-rtl.c 2016-05-02 07:48:47.925017436 -0400
|
10706 |
117 |
dgisselq |
@@ -81,6 +81,15 @@
|
10707 |
|
|
#include "builtins.h"
|
10708 |
|
|
#include "rtl-iter.h"
|
10709 |
|
|
|
10710 |
|
|
+// #define DO_ZIP_DEBUGS
|
10711 |
|
|
+#include <stdio.h>
|
10712 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
10713 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
10714 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
10715 |
|
|
+#else
|
10716 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
10717 |
|
|
+#endif
|
10718 |
|
|
+
|
10719 |
|
|
struct target_rtl default_target_rtl;
|
10720 |
|
|
#if SWITCHABLE_TARGET
|
10721 |
|
|
struct target_rtl *this_target_rtl = &default_target_rtl;
|
10722 |
127 |
dgisselq |
@@ -2979,6 +2988,8 @@
|
10723 |
117 |
dgisselq |
break;
|
10724 |
|
|
}
|
10725 |
|
|
|
10726 |
|
|
+ZIP_DEBUG_LINE("Before RTX_FLAG",x);
|
10727 |
|
|
+
|
10728 |
|
|
/* This rtx may not be shared. If it has already been seen,
|
10729 |
|
|
replace it with a copy of itself. */
|
10730 |
|
|
|
10731 |
127 |
dgisselq |
@@ -2989,6 +3000,8 @@
|
10732 |
117 |
dgisselq |
}
|
10733 |
|
|
RTX_FLAG (x, used) = 1;
|
10734 |
|
|
|
10735 |
|
|
+ZIP_DEBUG_LINE("Post RTX_FLAG",x);
|
10736 |
|
|
+
|
10737 |
|
|
/* Now scan the subexpressions recursively.
|
10738 |
|
|
We can store any replaced subexpressions directly into X
|
10739 |
|
|
since we know X is not shared! Any vectors in X
|
10740 |
127 |
dgisselq |
@@ -3665,7 +3678,9 @@
|
10741 |
|
|
split_branch_probability = XINT (note, 0);
|
10742 |
|
|
probability = split_branch_probability;
|
10743 |
|
|
|
10744 |
|
|
+ZIP_DEBUG_LINE("Before split", trial);
|
10745 |
|
|
seq = safe_as_a <rtx_insn *> (split_insns (pat, trial));
|
10746 |
|
|
+ZIP_DEBUG_LINE("After split", seq);
|
10747 |
|
|
|
10748 |
|
|
split_branch_probability = -1;
|
10749 |
|
|
|
10750 |
|
|
@@ -3834,6 +3849,7 @@
|
10751 |
|
|
if (! tem->deleted () && INSN_P (tem))
|
10752 |
|
|
tem = try_split (PATTERN (tem), tem, 1);
|
10753 |
|
|
|
10754 |
|
|
+
|
10755 |
|
|
/* Return either the first or the last insn, depending on which was
|
10756 |
|
|
requested. */
|
10757 |
|
|
return last
|
10758 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c
|
10759 |
|
|
--- gcc-5.3.0-original/gcc/expr.c 2015-04-07 10:34:06.000000000 -0400
|
10760 |
103 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/expr.c 2016-03-08 04:07:01.426335724 -0500
|
10761 |
102 |
dgisselq |
@@ -7999,6 +7999,8 @@
|
10762 |
|
|
the back of the caller.
|
10763 |
|
|
The normal operating mode is to pass FALSE for this parameter. */
|
10764 |
|
|
|
10765 |
|
|
+#include "print-tree.h"
|
10766 |
|
|
+
|
10767 |
|
|
rtx
|
10768 |
|
|
expand_expr_real (tree exp, rtx target, machine_mode tmode,
|
10769 |
|
|
enum expand_modifier modifier, rtx *alt_rtl,
|
10770 |
111 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
|
10771 |
|
|
--- gcc-5.3.0-original/gcc/final.c 2015-01-15 08:28:42.000000000 -0500
|
10772 |
127 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/final.c 2016-04-20 20:52:07.186056061 -0400
|
10773 |
111 |
dgisselq |
@@ -109,6 +109,14 @@
|
10774 |
|
|
#include "wide-int-print.h"
|
10775 |
|
|
#include "rtl-iter.h"
|
10776 |
|
|
|
10777 |
122 |
dgisselq |
+// #define DO_ZIP_DEBUGS
|
10778 |
111 |
dgisselq |
+#ifdef DO_ZIP_DEBUGS
|
10779 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
10780 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
10781 |
|
|
+#else
|
10782 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
10783 |
|
|
+#endif
|
10784 |
|
|
+
|
10785 |
|
|
#ifdef XCOFF_DEBUGGING_INFO
|
10786 |
|
|
#include "xcoffout.h" /* Needed for external data
|
10787 |
|
|
declarations for e.g. AIX 4.x. */
|
10788 |
|
|
@@ -2071,6 +2079,8 @@
|
10789 |
|
|
/* Output the insns. */
|
10790 |
|
|
for (insn = first; insn;)
|
10791 |
|
|
{
|
10792 |
|
|
+ ZIP_DEBUG_LINE("final()\n", insn);
|
10793 |
|
|
+
|
10794 |
|
|
if (HAVE_ATTR_length)
|
10795 |
|
|
{
|
10796 |
|
|
if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
|
10797 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
|
10798 |
|
|
--- gcc-5.3.0-original/gcc/genmodes.c 2015-01-05 07:33:28.000000000 -0500
|
10799 |
|
|
+++ gcc-5.3.0-zip/gcc/genmodes.c 2016-03-04 21:27:49.669147699 -0500
|
10800 |
|
|
@@ -330,7 +330,8 @@
|
10801 |
|
|
the size of a CC mode is four units. */
|
10802 |
|
|
validate_mode (m, UNSET, UNSET, UNSET, UNSET, UNSET);
|
10803 |
|
|
|
10804 |
|
|
- m->bytesize = 4;
|
10805 |
|
|
+ /* For the ZipCPU, however, it is only one unit */
|
10806 |
|
|
+ m->bytesize = 1;
|
10807 |
|
|
m->ncomponents = 1;
|
10808 |
|
|
m->component = 0;
|
10809 |
|
|
break;
|
10810 |
|
|
@@ -766,11 +767,12 @@
|
10811 |
|
|
|
10812 |
|
|
/* So put the default value unless the target needs a non standard
|
10813 |
|
|
value. */
|
10814 |
|
|
-#ifdef BITS_PER_UNIT
|
10815 |
|
|
- bits_per_unit = BITS_PER_UNIT;
|
10816 |
|
|
-#else
|
10817 |
|
|
- bits_per_unit = 8;
|
10818 |
|
|
-#endif
|
10819 |
|
|
+// #ifdef BITS_PER_UNIT
|
10820 |
|
|
+ // bits_per_unit = BITS_PER_UNIT;
|
10821 |
|
|
+// #else
|
10822 |
|
|
+ bits_per_unit = 32;
|
10823 |
|
|
+#warning "Is there a more automated way to set bits per unit?"
|
10824 |
|
|
+// #endif
|
10825 |
|
|
|
10826 |
|
|
#ifdef MAX_BITSIZE_MODE_ANY_INT
|
10827 |
|
|
max_bitsize_mode_any_int = MAX_BITSIZE_MODE_ANY_INT;
|
10828 |
|
|
@@ -1083,7 +1085,7 @@
|
10829 |
|
|
first = modes[c];
|
10830 |
|
|
last = 0;
|
10831 |
|
|
for (m = first; m; last = m, m = m->next)
|
10832 |
|
|
- ;
|
10833 |
|
|
+ if ((m->next)&&(m->next->bytesize == m->bytesize)) first = m;
|
10834 |
|
|
|
10835 |
|
|
/* Don't use BImode for MIN_MODE_INT, since otherwise the middle
|
10836 |
|
|
end will try to use it for bitfields in structures and the
|
10837 |
|
|
@@ -1268,7 +1270,7 @@
|
10838 |
|
|
continue;
|
10839 |
|
|
if (m->precision != (unsigned int) -1)
|
10840 |
|
|
{
|
10841 |
|
|
- if (m2->precision != 2 * m->precision)
|
10842 |
|
|
+ if (m2->precision < 2 * m->precision)
|
10843 |
|
|
continue;
|
10844 |
|
|
}
|
10845 |
|
|
else
|
10846 |
|
|
@@ -1323,7 +1325,6 @@
|
10847 |
|
|
tagged_printf ("MODE_MASK (%u)", m->precision, m->name);
|
10848 |
|
|
else
|
10849 |
|
|
tagged_printf ("MODE_MASK (%u*BITS_PER_UNIT)", m->bytesize, m->name);
|
10850 |
|
|
-
|
10851 |
|
|
puts ("#undef MODE_MASK");
|
10852 |
|
|
print_closer ();
|
10853 |
|
|
}
|
10854 |
|
|
@@ -1351,12 +1352,23 @@
|
10855 |
|
|
int c;
|
10856 |
|
|
struct mode_data *m;
|
10857 |
|
|
|
10858 |
|
|
+ puts(
|
10859 |
|
|
+"\n\n/* This is a rather strange conundrum. Alignment is used by the host in\n"
|
10860 |
|
|
+" * the assembly file, whereas the size is used by the target. Thus, for\n"
|
10861 |
|
|
+" * now, to align to a single target word means to align to 4 8-bit bytes in\n"
|
10862 |
|
|
+" * assembly. If you get it wrong, the assembler will try to help. Thus,\n"
|
10863 |
|
|
+" * aligning to anything less than 4 (1 target word) will cause an alignment\n"
|
10864 |
|
|
+" * of the target word in size. However, this tries to do a little something\n"
|
10865 |
|
|
+" * teach our compiler what we are doing.\n"
|
10866 |
|
|
+" */\n");
|
10867 |
|
|
print_maybe_const_decl ("%sunsigned char",
|
10868 |
|
|
"mode_base_align", "NUM_MACHINE_MODES",
|
10869 |
|
|
alignment);
|
10870 |
|
|
|
10871 |
|
|
for_all_modes (c, m)
|
10872 |
|
|
- tagged_printf ("%u", m->alignment, m->name);
|
10873 |
|
|
+ tagged_printf ("%u", 4*m->bytesize,
|
10874 |
|
|
+ // m->alignment,
|
10875 |
|
|
+ m->name);
|
10876 |
|
|
|
10877 |
|
|
print_closer ();
|
10878 |
|
|
}
|
10879 |
117 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c
|
10880 |
|
|
--- gcc-5.3.0-original/gcc/jump.c 2015-01-27 04:19:30.000000000 -0500
|
10881 |
122 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/jump.c 2016-04-06 14:06:50.207563805 -0400
|
10882 |
117 |
dgisselq |
@@ -80,6 +80,14 @@
|
10883 |
|
|
#include "target.h"
|
10884 |
|
|
#include "rtl-iter.h"
|
10885 |
|
|
|
10886 |
|
|
+// #define DO_ZIP_DEBUGS
|
10887 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
10888 |
|
|
+#include <stdio.h>
|
10889 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
|
10890 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
10891 |
|
|
+#else
|
10892 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
10893 |
|
|
+#endif
|
10894 |
|
|
/* Optimize jump y; x: ... y: jumpif... x?
|
10895 |
|
|
Don't know if it is worth bothering with. */
|
10896 |
|
|
/* Optimize two cases of conditional jump to conditional jump?
|
10897 |
|
|
@@ -1136,6 +1144,7 @@
|
10898 |
|
|
int i;
|
10899 |
|
|
const char *fmt;
|
10900 |
|
|
|
10901 |
|
|
+ZIP_DEBUG_LINE("Mark jump label",insn);
|
10902 |
|
|
switch (code)
|
10903 |
|
|
{
|
10904 |
|
|
case PC:
|
10905 |
|
|
@@ -1248,6 +1257,8 @@
|
10906 |
|
|
break;
|
10907 |
|
|
}
|
10908 |
|
|
|
10909 |
|
|
+ZIP_DEBUG_LINE("Post case",insn);
|
10910 |
|
|
+
|
10911 |
|
|
fmt = GET_RTX_FORMAT (code);
|
10912 |
|
|
|
10913 |
|
|
/* The primary target of a tablejump is the label of the ADDR_VEC,
|
10914 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
|
10915 |
|
|
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
|
10916 |
111 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/machmode.def 2016-03-08 11:56:45.375491523 -0500
|
10917 |
102 |
dgisselq |
@@ -184,11 +184,11 @@
|
10918 |
|
|
larger types, then corresponding modes must be added here. The
|
10919 |
|
|
name OI is reserved for a 256-bit type (needed by some back ends).
|
10920 |
|
|
*/
|
10921 |
|
|
-INT_MODE (QI, 1);
|
10922 |
|
|
-INT_MODE (HI, 2);
|
10923 |
|
|
-INT_MODE (SI, 4);
|
10924 |
|
|
-INT_MODE (DI, 8);
|
10925 |
|
|
-INT_MODE (TI, 16);
|
10926 |
|
|
+// INT_MODE (QI, 1);
|
10927 |
|
|
+// INT_MODE (HI, 1);
|
10928 |
|
|
+INT_MODE (SI, 1);
|
10929 |
|
|
+INT_MODE (DI, 2);
|
10930 |
|
|
+INT_MODE (TI, 4);
|
10931 |
|
|
|
10932 |
|
|
/* No partial integer modes are defined by default. */
|
10933 |
|
|
|
10934 |
111 |
dgisselq |
@@ -206,35 +206,35 @@
|
10935 |
102 |
dgisselq |
These are the IEEE mappings. They can be overridden with
|
10936 |
|
|
RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE). */
|
10937 |
|
|
|
10938 |
|
|
-FLOAT_MODE (SF, 4, ieee_single_format);
|
10939 |
|
|
-FLOAT_MODE (DF, 8, ieee_double_format);
|
10940 |
|
|
+FLOAT_MODE (SF, 1, ieee_single_format);
|
10941 |
|
|
+FLOAT_MODE (DF, 2, ieee_double_format);
|
10942 |
|
|
|
10943 |
|
|
/* Basic CC modes.
|
10944 |
|
|
FIXME define this only for targets that need it. */
|
10945 |
111 |
dgisselq |
CC_MODE (CC);
|
10946 |
102 |
dgisselq |
|
10947 |
|
|
/* Fixed-point modes. */
|
10948 |
111 |
dgisselq |
-FRACT_MODE (QQ, 1, 7); /* s.7 */
|
10949 |
102 |
dgisselq |
-FRACT_MODE (HQ, 2, 15); /* s.15 */
|
10950 |
|
|
-FRACT_MODE (SQ, 4, 31); /* s.31 */
|
10951 |
|
|
-FRACT_MODE (DQ, 8, 63); /* s.63 */
|
10952 |
|
|
-FRACT_MODE (TQ, 16, 127); /* s.127 */
|
10953 |
111 |
dgisselq |
-
|
10954 |
|
|
-UFRACT_MODE (UQQ, 1, 8); /* .8 */
|
10955 |
102 |
dgisselq |
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
|
10956 |
|
|
-UFRACT_MODE (USQ, 4, 32); /* .32 */
|
10957 |
|
|
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
|
10958 |
|
|
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
|
10959 |
111 |
dgisselq |
-
|
10960 |
|
|
-ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
|
10961 |
|
|
-ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
|
10962 |
|
|
-ACCUM_MODE (DA, 8, 32, 31); /* s32.31 */
|
10963 |
|
|
-ACCUM_MODE (TA, 16, 64, 63); /* s64.63 */
|
10964 |
|
|
-
|
10965 |
|
|
-UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
|
10966 |
|
|
-UACCUM_MODE (USA, 4, 16, 16); /* 16.16 */
|
10967 |
|
|
-UACCUM_MODE (UDA, 8, 32, 32); /* 32.32 */
|
10968 |
|
|
-UACCUM_MODE (UTA, 16, 64, 64); /* 64.64 */
|
10969 |
|
|
+/* FRACT_MODE (QQ, 1, 7); /* s.7 */
|
10970 |
|
|
+/* FRACT_MODE (HQ, 1, 15); /* s.15 */
|
10971 |
|
|
+FRACT_MODE (SQ, 1, 31); /* s.31 */
|
10972 |
|
|
+FRACT_MODE (DQ, 2, 63); /* s.63 */
|
10973 |
|
|
+FRACT_MODE (TQ, 4, 127); /* s.127 */
|
10974 |
|
|
+
|
10975 |
|
|
+/* UFRACT_MODE (UQQ, 1, 8); /* .8 */
|
10976 |
|
|
+/* UFRACT_MODE (UHQ, 1, 16); /* .16 */
|
10977 |
102 |
dgisselq |
+UFRACT_MODE (USQ, 1, 32); /* .32 */
|
10978 |
|
|
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
|
10979 |
|
|
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
|
10980 |
111 |
dgisselq |
+
|
10981 |
|
|
+/* ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
|
10982 |
|
|
+ACCUM_MODE (SA, 1, 16, 15); /* s16.15 */
|
10983 |
|
|
+ACCUM_MODE (DA, 2, 32, 31); /* s32.31 */
|
10984 |
|
|
+ACCUM_MODE (TA, 4, 64, 63); /* s64.63 */
|
10985 |
|
|
+
|
10986 |
|
|
+/* UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
|
10987 |
|
|
+UACCUM_MODE (USA, 1, 16, 16); /* 16.16 */
|
10988 |
|
|
+UACCUM_MODE (UDA, 2, 32, 32); /* 32.32 */
|
10989 |
|
|
+UACCUM_MODE (UTA, 4, 64, 64); /* 64.64 */
|
10990 |
102 |
dgisselq |
|
10991 |
111 |
dgisselq |
/* Allow the target to specify additional modes of various kinds. */
|
10992 |
|
|
#if HAVE_EXTRA_MODES
|
10993 |
102 |
dgisselq |
@@ -246,9 +246,9 @@
|
10994 |
|
|
COMPLEX_MODES (FLOAT);
|
10995 |
|
|
|
10996 |
|
|
/* Decimal floating point modes. */
|
10997 |
|
|
-DECIMAL_FLOAT_MODE (SD, 4, decimal_single_format);
|
10998 |
|
|
-DECIMAL_FLOAT_MODE (DD, 8, decimal_double_format);
|
10999 |
|
|
-DECIMAL_FLOAT_MODE (TD, 16, decimal_quad_format);
|
11000 |
|
|
+DECIMAL_FLOAT_MODE (SD, 1, decimal_single_format);
|
11001 |
|
|
+DECIMAL_FLOAT_MODE (DD, 2, decimal_double_format);
|
11002 |
|
|
+DECIMAL_FLOAT_MODE (TD, 4, decimal_quad_format);
|
11003 |
|
|
|
11004 |
|
|
/* The symbol Pmode stands for one of the above machine modes (usually SImode).
|
11005 |
|
|
The tm.h file specifies which one. It is not a distinct mode. */
|
11006 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.h gcc-5.3.0-zip/gcc/machmode.h
|
11007 |
|
|
--- gcc-5.3.0-original/gcc/machmode.h 2015-01-05 07:33:28.000000000 -0500
|
11008 |
|
|
+++ gcc-5.3.0-zip/gcc/machmode.h 2016-02-06 17:21:49.592924065 -0500
|
11009 |
|
|
@@ -180,13 +180,7 @@
|
11010 |
|
|
/* Get the size in bytes and bits of an object of mode MODE. */
|
11011 |
|
|
|
11012 |
|
|
extern CONST_MODE_SIZE unsigned char mode_size[NUM_MACHINE_MODES];
|
11013 |
|
|
-#if GCC_VERSION >= 4001
|
11014 |
|
|
-#define GET_MODE_SIZE(MODE) \
|
11015 |
|
|
- ((unsigned short) (__builtin_constant_p (MODE) \
|
11016 |
|
|
- ? mode_size_inline (MODE) : mode_size[MODE]))
|
11017 |
|
|
-#else
|
11018 |
|
|
#define GET_MODE_SIZE(MODE) ((unsigned short) mode_size[MODE])
|
11019 |
|
|
-#endif
|
11020 |
|
|
#define GET_MODE_BITSIZE(MODE) \
|
11021 |
|
|
((unsigned short) (GET_MODE_SIZE (MODE) * BITS_PER_UNIT))
|
11022 |
|
|
|
11023 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/objc/objc-encoding.c gcc-5.3.0-zip/gcc/objc/objc-encoding.c
|
11024 |
|
|
--- gcc-5.3.0-original/gcc/objc/objc-encoding.c 2015-01-09 15:18:42.000000000 -0500
|
11025 |
|
|
+++ gcc-5.3.0-zip/gcc/objc/objc-encoding.c 2016-03-04 22:53:40.431902505 -0500
|
11026 |
|
|
@@ -765,10 +765,14 @@
|
11027 |
|
|
{
|
11028 |
|
|
switch (TYPE_MODE (type))
|
11029 |
|
|
{
|
11030 |
|
|
+#ifdef HAVE_QImode
|
11031 |
|
|
case QImode:
|
11032 |
|
|
charType = 'C'; break;
|
11033 |
|
|
+#endif
|
11034 |
|
|
+#ifdef HAVE_HImode
|
11035 |
|
|
case HImode:
|
11036 |
|
|
charType = 'S'; break;
|
11037 |
|
|
+#endif
|
11038 |
|
|
case SImode:
|
11039 |
|
|
{
|
11040 |
|
|
if (type == long_unsigned_type_node)
|
11041 |
|
|
@@ -788,10 +792,14 @@
|
11042 |
|
|
{
|
11043 |
|
|
switch (TYPE_MODE (type))
|
11044 |
|
|
{
|
11045 |
|
|
+#ifdef HAVE_QImode
|
11046 |
|
|
case QImode:
|
11047 |
|
|
charType = 'c'; break;
|
11048 |
|
|
+#endif
|
11049 |
|
|
+#ifdef HAVE_HImode
|
11050 |
|
|
case HImode:
|
11051 |
|
|
charType = 's'; break;
|
11052 |
|
|
+#endif
|
11053 |
|
|
case SImode:
|
11054 |
|
|
{
|
11055 |
|
|
if (type == long_integer_type_node)
|
11056 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
|
11057 |
|
|
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
|
11058 |
111 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/postreload.c 2016-03-24 21:30:23.402590035 -0400
|
11059 |
|
|
@@ -71,6 +71,14 @@
|
11060 |
102 |
dgisselq |
#include "df.h"
|
11061 |
|
|
#include "dbgcnt.h"
|
11062 |
|
|
|
11063 |
111 |
dgisselq |
+// #define DO_ZIP_DEBUGS
|
11064 |
102 |
dgisselq |
+#ifdef DO_ZIP_DEBUGS
|
11065 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
11066 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
11067 |
|
|
+#else
|
11068 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
11069 |
|
|
+#endif
|
11070 |
|
|
+
|
11071 |
|
|
static int reload_cse_noop_set_p (rtx);
|
11072 |
|
|
static bool reload_cse_simplify (rtx_insn *, rtx);
|
11073 |
|
|
static void reload_cse_regs_1 (void);
|
11074 |
111 |
dgisselq |
@@ -120,6 +128,8 @@
|
11075 |
102 |
dgisselq |
basic_block insn_bb = BLOCK_FOR_INSN (insn);
|
11076 |
|
|
unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
|
11077 |
|
|
|
11078 |
|
|
+ ZIP_DEBUG_LINE("RELOAD-CSE-SIMPLIFY:",insn);
|
11079 |
|
|
+
|
11080 |
|
|
if (GET_CODE (body) == SET)
|
11081 |
|
|
{
|
11082 |
|
|
int count = 0;
|
11083 |
111 |
dgisselq |
@@ -147,6 +157,7 @@
|
11084 |
102 |
dgisselq |
apply_change_group ();
|
11085 |
|
|
else
|
11086 |
|
|
reload_cse_simplify_operands (insn, testreg);
|
11087 |
|
|
+ ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
|
11088 |
|
|
}
|
11089 |
|
|
else if (GET_CODE (body) == PARALLEL)
|
11090 |
|
|
{
|
11091 |
111 |
dgisselq |
@@ -205,6 +216,7 @@
|
11092 |
102 |
dgisselq |
apply_change_group ();
|
11093 |
|
|
else
|
11094 |
|
|
reload_cse_simplify_operands (insn, testreg);
|
11095 |
|
|
+ ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
|
11096 |
|
|
}
|
11097 |
|
|
|
11098 |
|
|
done:
|
11099 |
111 |
dgisselq |
@@ -246,6 +258,7 @@
|
11100 |
102 |
dgisselq |
cfg_changed |= reload_cse_simplify (insn, testreg);
|
11101 |
|
|
|
11102 |
|
|
cselib_process_insn (insn);
|
11103 |
|
|
+ ZIP_DEBUG_LINE("End-CSE-REGS-1:",insn);
|
11104 |
|
|
}
|
11105 |
|
|
|
11106 |
|
|
/* Clean up. */
|
11107 |
111 |
dgisselq |
@@ -276,6 +289,8 @@
|
11108 |
102 |
dgisselq |
#endif
|
11109 |
|
|
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
|
11110 |
|
|
|
11111 |
|
|
+
|
11112 |
|
|
+ ZIP_DEBUG_LINE("RELOAD:Attempting to simplify set",set);
|
11113 |
|
|
dreg = true_regnum (SET_DEST (set));
|
11114 |
|
|
if (dreg < 0)
|
11115 |
|
|
return 0;
|
11116 |
111 |
dgisselq |
@@ -427,6 +442,7 @@
|
11117 |
102 |
dgisselq |
/* Array of alternatives, sorted in order of decreasing desirability. */
|
11118 |
|
|
int *alternative_order;
|
11119 |
|
|
|
11120 |
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands", insn);
|
11121 |
|
|
extract_constrain_insn (insn);
|
11122 |
|
|
|
11123 |
|
|
if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
|
11124 |
111 |
dgisselq |
@@ -519,6 +535,7 @@
|
11125 |
102 |
dgisselq |
SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
|
11126 |
|
|
}
|
11127 |
|
|
|
11128 |
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - A", insn);
|
11129 |
|
|
alternative_mask preferred = get_preferred_alternatives (insn);
|
11130 |
|
|
for (i = 0; i < recog_data.n_operands; i++)
|
11131 |
|
|
{
|
11132 |
111 |
dgisselq |
@@ -617,6 +634,7 @@
|
11133 |
102 |
dgisselq |
}
|
11134 |
|
|
}
|
11135 |
|
|
}
|
11136 |
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - B", insn);
|
11137 |
|
|
|
11138 |
|
|
/* Record all alternatives which are better or equal to the currently
|
11139 |
|
|
matching one in the alternative_order array. */
|
11140 |
111 |
dgisselq |
@@ -666,6 +684,7 @@
|
11141 |
102 |
dgisselq |
validate_change (insn, recog_data.operand_loc[i],
|
11142 |
|
|
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
|
11143 |
|
|
}
|
11144 |
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
|
11145 |
|
|
|
11146 |
|
|
for (i = recog_data.n_dups - 1; i >= 0; i--)
|
11147 |
|
|
{
|
11148 |
111 |
dgisselq |
@@ -679,6 +698,7 @@
|
11149 |
102 |
dgisselq |
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
|
11150 |
|
|
}
|
11151 |
|
|
|
11152 |
|
|
+ ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
|
11153 |
|
|
return apply_change_group ();
|
11154 |
|
|
}
|
11155 |
|
|
|
11156 |
117 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
|
11157 |
|
|
--- gcc-5.3.0-original/gcc/recog.c 2015-03-20 02:07:30.000000000 -0400
|
11158 |
127 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/recog.c 2016-04-14 23:19:07.630839483 -0400
|
11159 |
117 |
dgisselq |
@@ -68,6 +68,15 @@
|
11160 |
|
|
#include "df.h"
|
11161 |
|
|
#include "insn-codes.h"
|
11162 |
|
|
|
11163 |
|
|
+// #define DO_ZIP_DEBUGS
|
11164 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
11165 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
11166 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
11167 |
|
|
+#else
|
11168 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
11169 |
|
|
+#endif
|
11170 |
|
|
+
|
11171 |
|
|
+
|
11172 |
|
|
#ifndef STACK_PUSH_CODE
|
11173 |
|
|
#ifdef STACK_GROWS_DOWNWARD
|
11174 |
|
|
#define STACK_PUSH_CODE PRE_DEC
|
11175 |
122 |
dgisselq |
@@ -2283,6 +2292,7 @@
|
11176 |
|
|
recog_data.n_dups = 0;
|
11177 |
|
|
recog_data.is_asm = false;
|
11178 |
|
|
|
11179 |
|
|
+ZIP_DEBUG_LINE("Extract-insn", insn);
|
11180 |
|
|
switch (GET_CODE (body))
|
11181 |
|
|
{
|
11182 |
|
|
case USE:
|
11183 |
|
|
@@ -3671,7 +3681,6 @@
|
11184 |
117 |
dgisselq |
break;
|
11185 |
|
|
|
11186 |
|
|
/* The buffer filled to the current maximum, so try to match. */
|
11187 |
|
|
-
|
11188 |
|
|
pos = peep2_buf_position (peep2_current + peep2_current_count);
|
11189 |
|
|
peep2_insn_data[pos].insn = PEEP2_EOB;
|
11190 |
|
|
COPY_REG_SET (peep2_insn_data[pos].live_before, live);
|
11191 |
122 |
dgisselq |
@@ -3704,6 +3713,7 @@
|
11192 |
117 |
dgisselq |
rebuild_jump_labels (get_insns ());
|
11193 |
|
|
if (peep2_do_cleanup_cfg)
|
11194 |
|
|
cleanup_cfg (CLEANUP_CFG_CHANGED);
|
11195 |
|
|
+
|
11196 |
|
|
}
|
11197 |
|
|
#endif /* HAVE_peephole2 */
|
11198 |
|
|
|
11199 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
|
11200 |
|
|
--- gcc-5.3.0-original/gcc/reload1.c 2015-01-15 08:28:42.000000000 -0500
|
11201 |
127 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-04-20 20:51:38.590252867 -0400
|
11202 |
117 |
dgisselq |
@@ -72,6 +72,14 @@
|
11203 |
|
|
#include "dumpfile.h"
|
11204 |
|
|
#include "rtl-iter.h"
|
11205 |
|
|
|
11206 |
|
|
+// #define DO_ZIP_DEBUGS
|
11207 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
11208 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
11209 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
11210 |
|
|
+#else
|
11211 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
11212 |
|
|
+#endif
|
11213 |
|
|
+
|
11214 |
|
|
/* This file contains the reload pass of the compiler, which is
|
11215 |
|
|
run after register allocation has been done. It checks that
|
11216 |
|
|
each insn is valid (operands required to be in registers really
|
11217 |
127 |
dgisselq |
@@ -794,6 +802,20 @@
|
11218 |
117 |
dgisselq |
basic_block bb;
|
11219 |
|
|
bool inserted;
|
11220 |
|
|
|
11221 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
11222 |
|
|
+ {
|
11223 |
127 |
dgisselq |
+ fprintf(stderr, "BEFORE-RELOAD\n");
|
11224 |
117 |
dgisselq |
+ int total_count = 0, current_count = 0;
|
11225 |
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
11226 |
|
|
+ total_count++;
|
11227 |
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
11228 |
|
|
+ fprintf(stderr, "B %3d/%3d", current_count++, total_count);
|
11229 |
|
|
+ zip_debug_rtx(insn);
|
11230 |
|
|
+ }
|
11231 |
127 |
dgisselq |
+ fprintf(stderr, "BEFORE-RELOAD -- END OF INSTRUCTION LIST\n");
|
11232 |
117 |
dgisselq |
+ }
|
11233 |
|
|
+#endif
|
11234 |
|
|
+
|
11235 |
|
|
/* Make sure even insns with volatile mem refs are recognizable. */
|
11236 |
|
|
init_recog ();
|
11237 |
|
|
|
11238 |
127 |
dgisselq |
@@ -1366,6 +1388,20 @@
|
11239 |
117 |
dgisselq |
|
11240 |
|
|
reload_completed = !failure;
|
11241 |
|
|
|
11242 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
11243 |
|
|
+ {
|
11244 |
127 |
dgisselq |
+ fprintf(stderr, "AFTER-RELOAD\n");
|
11245 |
117 |
dgisselq |
+ int total_count = 0, current_count = 0;
|
11246 |
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn))
|
11247 |
|
|
+ total_count++;
|
11248 |
|
|
+ for (insn = first; insn; insn = NEXT_INSN (insn)) {
|
11249 |
|
|
+ fprintf(stderr, "A %3d/%3d", current_count++, total_count);
|
11250 |
|
|
+ zip_debug_rtx(insn);
|
11251 |
|
|
+ }
|
11252 |
127 |
dgisselq |
+ fprintf(stderr, "AFTER-RELOAD -- END OF INSTRUCTION LIST\n");
|
11253 |
117 |
dgisselq |
+ }
|
11254 |
|
|
+#endif
|
11255 |
|
|
+
|
11256 |
|
|
return need_dce;
|
11257 |
|
|
}
|
11258 |
|
|
|
11259 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
|
11260 |
|
|
--- gcc-5.3.0-original/gcc/reload.c 2015-01-15 08:28:42.000000000 -0500
|
11261 |
122 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/reload.c 2016-04-06 17:49:33.418613170 -0400
|
11262 |
|
|
@@ -136,6 +136,15 @@
|
11263 |
|
|
#include "target.h"
|
11264 |
|
|
#include "ira.h"
|
11265 |
|
|
|
11266 |
|
|
+// #define DO_ZIP_DEBUGS
|
11267 |
|
|
+#ifdef DO_ZIP_DEBUGS
|
11268 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
11269 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
|
11270 |
|
|
+#else
|
11271 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
11272 |
|
|
+#endif
|
11273 |
|
|
+
|
11274 |
|
|
+
|
11275 |
|
|
/* True if X is a constant that can be forced into the constant pool.
|
11276 |
|
|
MODE is the mode of the operand, or VOIDmode if not known. */
|
11277 |
|
|
#define CONST_POOL_OK_P(MODE, X) \
|
11278 |
|
|
@@ -2700,6 +2709,8 @@
|
11279 |
|
|
hard_regs_live_known = live_known;
|
11280 |
|
|
static_reload_reg_p = reload_reg_p;
|
11281 |
|
|
|
11282 |
|
|
+ZIP_DEBUG_LINE("Find reloads\n", insn);
|
11283 |
|
|
+
|
11284 |
|
|
/* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
|
11285 |
|
|
neither are insns that SET cc0. Insns that use CC0 are not allowed
|
11286 |
|
|
to have any input reloads. */
|
11287 |
|
|
@@ -2707,8 +2718,17 @@
|
11288 |
102 |
dgisselq |
no_output_reloads = 1;
|
11289 |
|
|
|
11290 |
|
|
#ifdef HAVE_cc0
|
11291 |
|
|
+ // If the instruction depends upon cc0, such as a branch, if_then_else, or
|
11292 |
|
|
+ // cond_exec instruction, we cannot change the input so that the instruction
|
11293 |
|
|
+ // relies on another register--cc0 is specific. This requries that the
|
11294 |
|
|
+ // references be only cc0 and (const_int 0), rather than allowing other
|
11295 |
|
|
+ // registers here as well.
|
11296 |
|
|
if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
|
11297 |
|
|
no_input_reloads = 1;
|
11298 |
|
|
+ // If the result of an instruction is the cc0 register, that cannot
|
11299 |
|
|
+ // be changed, therefore no output reloading is allowed. This only
|
11300 |
|
|
+ // works if instructions *only* set the cc0 register, and not multiple
|
11301 |
|
|
+ // registers.
|
11302 |
|
|
if (reg_set_p (cc0_rtx, PATTERN (insn)))
|
11303 |
|
|
no_output_reloads = 1;
|
11304 |
|
|
#endif
|
11305 |
146 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/target-def.h gcc-5.3.0-zip/gcc/target-def.h
|
11306 |
|
|
--- gcc-5.3.0-original/gcc/target-def.h 2015-01-05 07:33:28.000000000 -0500
|
11307 |
|
|
+++ gcc-5.3.0-zip/gcc/target-def.h 2016-05-12 15:20:06.896745740 -0400
|
11308 |
|
|
@@ -29,24 +29,44 @@
|
11309 |
|
|
rather than the .c file, then we need to wrap the default
|
11310 |
|
|
definition in a #ifndef, since files include tm.h before this one. */
|
11311 |
|
|
|
11312 |
|
|
+#ifndef TARGET_ASM_ALIGNED_HI_OP
|
11313 |
|
|
#define TARGET_ASM_ALIGNED_HI_OP "\t.short\t"
|
11314 |
|
|
+#endif
|
11315 |
|
|
+#ifndef TARGET_ASM_ALIGNED_SI_OP
|
11316 |
|
|
#define TARGET_ASM_ALIGNED_SI_OP "\t.long\t"
|
11317 |
|
|
+#endif
|
11318 |
|
|
#define TARGET_ASM_ALIGNED_DI_OP NULL
|
11319 |
|
|
#define TARGET_ASM_ALIGNED_TI_OP NULL
|
11320 |
|
|
|
11321 |
|
|
/* GAS and SYSV4 assemblers accept these. */
|
11322 |
|
|
#if defined (OBJECT_FORMAT_ELF)
|
11323 |
|
|
-#define TARGET_ASM_UNALIGNED_HI_OP "\t.2byte\t"
|
11324 |
|
|
-#define TARGET_ASM_UNALIGNED_SI_OP "\t.4byte\t"
|
11325 |
|
|
-#define TARGET_ASM_UNALIGNED_DI_OP "\t.8byte\t"
|
11326 |
|
|
-#define TARGET_ASM_UNALIGNED_TI_OP NULL
|
11327 |
|
|
+# ifndef TARGET_ASM_UNALIGNED_HI_OP
|
11328 |
|
|
+# define TARGET_ASM_UNALIGNED_HI_OP "\t.2byte\t"
|
11329 |
|
|
+# endif
|
11330 |
|
|
+# ifndef TARGET_ASM_UNALIGNED_SI_OP
|
11331 |
|
|
+# define TARGET_ASM_UNALIGNED_SI_OP "\t.4b0te\t"
|
11332 |
|
|
+# endif
|
11333 |
|
|
+# ifndef TARGET_ASM_UNALIGNED_DI_OP
|
11334 |
|
|
+# define TARGET_ASM_UNALIGNED_DI_OP "\t.8byte\t"
|
11335 |
|
|
+# endif
|
11336 |
|
|
+# define TARGET_ASM_UNALIGNED_TI_OP NULL
|
11337 |
|
|
#else
|
11338 |
|
|
-#define TARGET_ASM_UNALIGNED_HI_OP NULL
|
11339 |
|
|
-#define TARGET_ASM_UNALIGNED_SI_OP NULL
|
11340 |
|
|
-#define TARGET_ASM_UNALIGNED_DI_OP NULL
|
11341 |
|
|
-#define TARGET_ASM_UNALIGNED_TI_OP NULL
|
11342 |
|
|
+# ifndef TARGET_ASM_UNALIGNED_HI_OP
|
11343 |
|
|
+# define TARGET_ASM_UNALIGNED_HI_OP NULL
|
11344 |
|
|
+# endif
|
11345 |
|
|
+# ifndef TARGET_ASM_UNALIGNED_SI_OP
|
11346 |
|
|
+# define TARGET_ASM_UNALIGNED_SI_OP NULL
|
11347 |
|
|
+# endif
|
11348 |
|
|
+# ifndef TARGET_ASM_UNALIGNED_DI_OP
|
11349 |
|
|
+# define TARGET_ASM_UNALIGNED_DI_OP NULL
|
11350 |
|
|
+# endif
|
11351 |
|
|
+# define TARGET_ASM_UNALIGNED_TI_OP NULL
|
11352 |
|
|
#endif /* OBJECT_FORMAT_ELF */
|
11353 |
|
|
|
11354 |
|
|
+#ifndef TARGET_ASM_UNALIGNED_TI_OP
|
11355 |
|
|
+#define TARGET_ASM_UNALIGNED_TI_OP NULL
|
11356 |
|
|
+#endif
|
11357 |
|
|
+
|
11358 |
|
|
#if !defined(TARGET_ASM_CONSTRUCTOR) && !defined(USE_COLLECT2)
|
11359 |
|
|
# ifdef CTORS_SECTION_ASM_OP
|
11360 |
|
|
# define TARGET_ASM_CONSTRUCTOR default_ctor_section_asm_out_constructor
|
11361 |
102 |
dgisselq |
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp
|
11362 |
|
|
--- gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp 2015-11-26 05:10:58.000000000 -0500
|
11363 |
|
|
+++ gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp 2016-01-30 15:14:21.620586694 -0500
|
11364 |
|
|
@@ -503,6 +503,11 @@
|
11365 |
|
|
return 0
|
11366 |
|
|
}
|
11367 |
|
|
|
11368 |
|
|
+ # Zip CPU doesn't support profiling (yet)
|
11369 |
|
|
+ if { [istarget zip*] }
|
11370 |
|
|
+ return 0
|
11371 |
|
|
+ }
|
11372 |
|
|
+
|
11373 |
|
|
# MinGW does not support -p.
|
11374 |
|
|
if { [istarget *-*-mingw*] && $test_what == "-p" } {
|
11375 |
|
|
return 0
|
11376 |
|
|
@@ -986,6 +991,12 @@
|
11377 |
|
|
}]
|
11378 |
|
|
}
|
11379 |
|
|
|
11380 |
|
|
+ # No real hardware FPU support for ZipCPU yet--even though the instruction
|
11381 |
|
|
+ # set supports it, the CPU just isn't ready yet.
|
11382 |
|
|
+ if { [istarget zip*-*-*] } {
|
11383 |
|
|
+ return 0
|
11384 |
|
|
+ }
|
11385 |
|
|
+
|
11386 |
|
|
# This proc is actually checking the availabilty of FPU
|
11387 |
|
|
# support for doubles, so on the RX we must fail if the
|
11388 |
|
|
# 64-bit double multilib has been selected.
|
11389 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/tree-ssa-math-opts.c gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c
|
11390 |
|
|
--- gcc-5.3.0-original/gcc/tree-ssa-math-opts.c 2015-08-11 03:58:07.000000000 -0400
|
11391 |
|
|
+++ gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c 2016-02-12 11:21:11.309149239 -0500
|
11392 |
|
|
@@ -972,7 +972,7 @@
|
11393 |
|
|
{
|
11394 |
|
|
if (val & 1)
|
11395 |
|
|
{
|
11396 |
|
|
- digit = val & ((1 << POWI_WINDOW_SIZE) - 1);
|
11397 |
|
|
+ digit = val & ((1l << POWI_WINDOW_SIZE) - 1);
|
11398 |
|
|
result += powi_lookup_cost (digit, cache)
|
11399 |
|
|
+ POWI_WINDOW_SIZE + 1;
|
11400 |
|
|
val >>= POWI_WINDOW_SIZE;
|
11401 |
|
|
@@ -1012,7 +1012,7 @@
|
11402 |
|
|
}
|
11403 |
|
|
else if (n & 1)
|
11404 |
|
|
{
|
11405 |
|
|
- digit = n & ((1 << POWI_WINDOW_SIZE) - 1);
|
11406 |
|
|
+ digit = n & ((1l << POWI_WINDOW_SIZE) - 1);
|
11407 |
|
|
op0 = powi_as_mults_1 (gsi, loc, type, n - digit, cache);
|
11408 |
|
|
op1 = powi_as_mults_1 (gsi, loc, type, digit, cache);
|
11409 |
|
|
}
|
11410 |
|
|
@@ -1651,7 +1651,7 @@
|
11411 |
|
|
};
|
11412 |
|
|
|
11413 |
|
|
#define BITS_PER_MARKER 8
|
11414 |
|
|
-#define MARKER_MASK ((1 << BITS_PER_MARKER) - 1)
|
11415 |
|
|
+#define MARKER_MASK ((1l << BITS_PER_MARKER) - 1)
|
11416 |
|
|
#define MARKER_BYTE_UNKNOWN MARKER_MASK
|
11417 |
|
|
#define HEAD_MARKER(n, size) \
|
11418 |
|
|
((n) & ((uint64_t) MARKER_MASK << (((size) - 1) * BITS_PER_MARKER)))
|
11419 |
|
|
@@ -1687,7 +1687,7 @@
|
11420 |
|
|
/* Zero out the extra bits of N in order to avoid them being shifted
|
11421 |
|
|
into the significant bits. */
|
11422 |
|
|
if (size < 64 / BITS_PER_MARKER)
|
11423 |
|
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
11424 |
|
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
11425 |
|
|
|
11426 |
|
|
switch (code)
|
11427 |
|
|
{
|
11428 |
|
|
@@ -1714,7 +1714,7 @@
|
11429 |
|
|
}
|
11430 |
|
|
/* Zero unused bits for size. */
|
11431 |
|
|
if (size < 64 / BITS_PER_MARKER)
|
11432 |
|
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
11433 |
|
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
11434 |
|
|
return true;
|
11435 |
|
|
}
|
11436 |
|
|
|
11437 |
|
|
@@ -1761,7 +1761,7 @@
|
11438 |
|
|
n->n = CMPNOP;
|
11439 |
|
|
|
11440 |
|
|
if (size < 64 / BITS_PER_MARKER)
|
11441 |
|
|
- n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
|
11442 |
|
|
+ n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
|
11443 |
|
|
|
11444 |
|
|
return true;
|
11445 |
|
|
}
|
11446 |
|
|
@@ -2020,7 +2020,7 @@
|
11447 |
|
|
{
|
11448 |
|
|
int i, size = TYPE_PRECISION (n->type) / BITS_PER_UNIT;
|
11449 |
|
|
uint64_t val = int_cst_value (rhs2), mask = 0;
|
11450 |
|
|
- uint64_t tmp = (1 << BITS_PER_UNIT) - 1;
|
11451 |
|
|
+ uint64_t tmp = (1l << BITS_PER_UNIT) - 1;
|
11452 |
|
|
|
11453 |
|
|
/* Only constants masking full bytes are allowed. */
|
11454 |
|
|
for (i = 0; i < size; i++, tmp <<= BITS_PER_UNIT)
|
11455 |
|
|
@@ -2064,7 +2064,7 @@
|
11456 |
|
|
{
|
11457 |
|
|
/* If STMT casts to a smaller type mask out the bits not
|
11458 |
|
|
belonging to the target type. */
|
11459 |
|
|
- n->n &= ((uint64_t) 1 << (type_size * BITS_PER_MARKER)) - 1;
|
11460 |
|
|
+ n->n &= ((uint64_t) 1l << (type_size * BITS_PER_MARKER)) - 1;
|
11461 |
|
|
}
|
11462 |
|
|
n->type = type;
|
11463 |
|
|
if (!n->base_addr)
|
11464 |
|
|
@@ -2177,7 +2177,7 @@
|
11465 |
|
|
{
|
11466 |
|
|
uint64_t mask;
|
11467 |
|
|
|
11468 |
|
|
- mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;
|
11469 |
|
|
+ mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;
|
11470 |
|
|
cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
|
11471 |
|
|
cmpnop &= mask;
|
11472 |
|
|
}
|
11473 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
|
11474 |
|
|
--- gcc-5.3.0-original/gcc/var-tracking.c 2015-03-26 09:19:00.000000000 -0400
|
11475 |
117 |
dgisselq |
+++ gcc-5.3.0-zip/gcc/var-tracking.c 2016-03-31 18:55:03.584197958 -0400
|
11476 |
102 |
dgisselq |
@@ -143,6 +143,13 @@
|
11477 |
|
|
#include "rtl-iter.h"
|
11478 |
|
|
#include "fibonacci_heap.h"
|
11479 |
|
|
|
11480 |
117 |
dgisselq |
+#ifdef DO_ZIP_DEBUGS
|
11481 |
102 |
dgisselq |
+#include <stdio.h>
|
11482 |
|
|
+extern void zip_debug_rtx(const_rtx);
|
11483 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX) do {fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
|
11484 |
|
|
+#else
|
11485 |
|
|
+#define ZIP_DEBUG_LINE(STR,RTX)
|
11486 |
|
|
+#endif
|
11487 |
|
|
typedef fibonacci_heap <long, basic_block_def> bb_heap_t;
|
11488 |
|
|
typedef fibonacci_node <long, basic_block_def> bb_heap_node_t;
|
11489 |
|
|
|
11490 |
|
|
@@ -6356,6 +6363,7 @@
|
11491 |
|
|
machine_mode indmode
|
11492 |
|
|
= TYPE_MODE (TREE_TYPE (argtype));
|
11493 |
|
|
rtx mem = gen_rtx_MEM (indmode, x);
|
11494 |
|
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref", mem);
|
11495 |
|
|
cselib_val *val = cselib_lookup (mem, indmode, 0, VOIDmode);
|
11496 |
|
|
if (val && cselib_preserved_value_p (val))
|
11497 |
|
|
{
|
11498 |
|
|
@@ -6462,12 +6470,14 @@
|
11499 |
|
|
machine_mode mode
|
11500 |
|
|
= TYPE_MODE (TREE_TYPE (OBJ_TYPE_REF_EXPR (obj_type_ref)));
|
11501 |
|
|
rtx clobbered = gen_rtx_MEM (mode, this_arg);
|
11502 |
|
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered", clobbered);
|
11503 |
|
|
HOST_WIDE_INT token
|
11504 |
|
|
= tree_to_shwi (OBJ_TYPE_REF_TOKEN (obj_type_ref));
|
11505 |
|
|
if (token)
|
11506 |
|
|
clobbered = plus_constant (mode, clobbered,
|
11507 |
|
|
token * GET_MODE_SIZE (mode));
|
11508 |
|
|
clobbered = gen_rtx_MEM (mode, clobbered);
|
11509 |
|
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered-2", clobbered);
|
11510 |
|
|
x = gen_rtx_CONCAT (mode, gen_rtx_CLOBBER (VOIDmode, pc_rtx), clobbered);
|
11511 |
|
|
call_arguments
|
11512 |
|
|
= gen_rtx_EXPR_LIST (VOIDmode, x, call_arguments);
|
11513 |
|
|
@@ -9790,6 +9800,7 @@
|
11514 |
|
|
machine_mode indmode
|
11515 |
|
|
= TYPE_MODE (TREE_TYPE (TREE_TYPE (parm)));
|
11516 |
|
|
rtx mem = gen_rtx_MEM (indmode, incoming);
|
11517 |
|
|
+ ZIP_DEBUG_LINE("Var-tracking mem-ref/incoming", incoming);
|
11518 |
|
|
cselib_val *val = cselib_lookup_from_insn (mem, indmode, true,
|
11519 |
|
|
VOIDmode,
|
11520 |
|
|
get_insns ());
|
11521 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/config.host gcc-5.3.0-zip/libgcc/config.host
|
11522 |
|
|
--- gcc-5.3.0-original/libgcc/config.host 2015-10-01 08:01:18.000000000 -0400
|
11523 |
|
|
+++ gcc-5.3.0-zip/libgcc/config.host 2016-01-30 15:16:00.459883558 -0500
|
11524 |
|
|
@@ -195,6 +195,9 @@
|
11525 |
|
|
tic6x-*-*)
|
11526 |
|
|
cpu_type=c6x
|
11527 |
|
|
;;
|
11528 |
|
|
+zip*)
|
11529 |
|
|
+ cpu_type=zip
|
11530 |
|
|
+ ;;
|
11531 |
|
|
esac
|
11532 |
|
|
|
11533 |
|
|
# Common parts for widely ported systems.
|
11534 |
|
|
@@ -1300,6 +1303,9 @@
|
11535 |
|
|
echo "*** Configuration ${host} not supported" 1>&2
|
11536 |
|
|
exit 1
|
11537 |
|
|
;;
|
11538 |
|
|
+zip*)
|
11539 |
|
|
+ tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
|
11540 |
|
|
+ ;;
|
11541 |
|
|
esac
|
11542 |
|
|
|
11543 |
|
|
case ${host} in
|
11544 |
|
|
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgomp/configure.tgt gcc-5.3.0-zip/libgomp/configure.tgt
|
11545 |
|
|
--- gcc-5.3.0-original/libgomp/configure.tgt 2015-03-13 06:57:07.000000000 -0400
|
11546 |
|
|
+++ gcc-5.3.0-zip/libgomp/configure.tgt 2016-01-30 15:16:51.323521641 -0500
|
11547 |
|
|
@@ -150,6 +150,9 @@
|
11548 |
|
|
# Need to link with -lpthread so libgomp.so is self-contained.
|
11549 |
|
|
XLDFLAGS="${XLDFLAGS} -lpthread"
|
11550 |
|
|
;;
|
11551 |
|
|
+ zip*)
|
11552 |
|
|
+ config_path="bsd posix"
|
11553 |
|
|
+ ;;
|
11554 |
|
|
|
11555 |
|
|
*)
|
11556 |
|
|
;;
|