OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [lib/] [divu.S] - Blame information for rev 170

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 59 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2 45 dgisselq
;
3 59 dgisselq
; Filename:     divu.S
4 45 dgisselq
;
5 59 dgisselq
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
6 45 dgisselq
;
7 59 dgisselq
; Purpose:      Zip assembly file for running doing an unsigned divide.
8
;               This routine is also called by the signed divide.
9 45 dgisselq
;
10 59 dgisselq
; Creator:      Dan Gisselquist, Ph.D.
11 69 dgisselq
;               Gisselquist Technology, LLC
12 59 dgisselq
;
13
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14
;
15
; Copyright (C) 2015, Gisselquist Technology, LLC
16
;
17
; This program is free software (firmware): you can redistribute it and/or
18
; modify it under the terms of  the GNU General Public License as published
19
; by the Free Software Foundation, either version 3 of the License, or (at
20
; your option) any later version.
21
;
22
; This program is distributed in the hope that it will be useful, but WITHOUT
23
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
24
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
25
; for more details.
26
;
27
; License:      GPL, v3, as defined and found on www.gnu.org,
28
;               http://www.gnu.org/licenses/gpl.html
29
;
30
;
31
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
32
;
33
;
34
;
35 69 dgisselq
lib_divu:       ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
36 45 dgisselq
        TST     -1,R1
37
        ; BNZ   divu_valid_divide
38
        CLR.Z   R0              ; Should be a divide by zero error / trap
39 69 dgisselq
        JMP.Z   R2
40 45 dgisselq
divu_valid_divide:
41 69 dgisselq
        SUB     2,SP
42
        STO     R2,(SP)
43 45 dgisselq
        STO     R3,1(SP)
44
        ;
45
        LDI     1,R2    ; Here's where we record the bit we are working on
46
        CLR     R3      ; Here's where we build our result
47
; Our original loop rejoin point, before a touch of unrolling
48
        CMP     R1,R0
49
        BRC     divu_prep_next_bit
50
        TST     -1,R1
51
        BLT     divu_top_bit_set
52
divu_rotate_up_r1:
53
        LSL     1,R2
54
        LSL     1,R1
55
/*
56
        CMP     R1,R0
57
        BRC     divu_prep_next_bit
58
        TST     -1,R1
59
        BGT     divu_rotate_up_r1
60
*/
61
        BLT     divu_top_bit_set
62
        CMP     R1,R0
63
        BRC     divu_prep_next_bit
64
        ;
65
        LSL     1,R2
66
        LSL     1,R1
67
        BLT     divu_top_bit_set
68
        CMP     R1,R0
69
        BRC     divu_prep_next_bit
70
        ;
71
        LSL     1,R2
72
        LSL     1,R1
73
        BLT     divu_top_bit_set
74
        CMP     R1,R0
75
        BRC     divu_prep_next_bit
76
        ;
77
        LSL     1,R2
78
        LSL     1,R1
79
        BLT     divu_top_bit_set
80
        CMP     R1,R0
81
        BRC     divu_prep_next_bit
82
        BRA     divu_rotate_up_r1
83
 
84
divu_top_bit_set:
85
        CMP     R1,R0
86
        BRC     divu_prep_next_bit
87
        SUB     R1,R0
88
        OR      R2,R3
89
divu_prep_next_bit:
90
        LSR     1,R1
91
        LSR     1,R2
92
        BZ      divu_record_result
93
        ;
94
divu_next_loop:
95
        CMP     R1,R0           ;
96
        SUB.GE  R1,R0           ; We also switch to signed arithmetic, since
97
        OR.GE   R2,R3           ; after the first bit, we are signed
98
        LSR     1,R1
99
        LSR     1,R2
100
        BZ      divu_record_result
101
        ;
102
        CMP     R1,R0
103
        SUB.GE  R1,R0
104
        OR.GE   R2,R3
105
        LSR     1,R1
106
        LSR     1,R2
107
        BZ      divu_record_result
108
        ;
109
        CMP     R1,R0
110
        SUB.GE  R1,R0
111
        OR.GE   R2,R3
112
        LSR     1,R1
113
        LSR     1,R2
114
        BZ      divu_record_result
115
        ;
116
        CMP     R1,R0
117
        SUB.GE  R1,R0
118
        OR.GE   R2,R3
119
        LSR     1,R1
120
        LSR     1,R2
121
        BNZ     divu_next_loop
122
 
123
divu_record_result:
124
        MOV     R0,R1
125
        MOV     R3,R0
126 69 dgisselq
        LOD     (SP),R2
127 45 dgisselq
        LOD     1(SP),R3
128 69 dgisselq
        ADD     2,SP
129 59 dgisselq
        JMP     R2
130 45 dgisselq
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.