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[/] [zipcpu/] [trunk/] [sw/] [lib/] [divu.S] - Blame information for rev 56

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;
;
;
;
divu:   ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
        TST     -1,R1
        ; BNZ   divu_valid_divide
        CLR.Z   R0              ; Should be a divide by zero error / trap
        RETN.Z
divu_valid_divide:
        SUB     1,SP
        STO     R3,1(SP)
        ;
        LDI     1,R2    ; Here's where we record the bit we are working on
        CLR     R3      ; Here's where we build our result
; Our original loop rejoin point, before a touch of unrolling
        CMP     R1,R0
        BRC     divu_prep_next_bit
        TST     -1,R1
        BLT     divu_top_bit_set
divu_rotate_up_r1:
        LSL     1,R2
        LSL     1,R1
/*
        CMP     R1,R0
        BRC     divu_prep_next_bit
        TST     -1,R1
        BGT     divu_rotate_up_r1
*/
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        ;
        LSL     1,R2
        LSL     1,R1
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        ;
        LSL     1,R2
        LSL     1,R1
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        ;
        LSL     1,R2
        LSL     1,R1
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        BRA     divu_rotate_up_r1
 
divu_top_bit_set:
        CMP     R1,R0
        BRC     divu_prep_next_bit
        SUB     R1,R0
        OR      R2,R3
divu_prep_next_bit:
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
divu_next_loop:
        CMP     R1,R0           ;
        SUB.GE  R1,R0           ; We also switch to signed arithmetic, since
        OR.GE   R2,R3           ; after the first bit, we are signed
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
        CMP     R1,R0
        SUB.GE  R1,R0
        OR.GE   R2,R3
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
        CMP     R1,R0
        SUB.GE  R1,R0
        OR.GE   R2,R3
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
        CMP     R1,R0
        SUB.GE  R1,R0
        OR.GE   R2,R3
        LSR     1,R1
        LSR     1,R2
        BNZ     divu_next_loop
 
divu_record_result:
        MOV     R0,R1
        MOV     R3,R0
        LOD     1(SP),R3
        ADD     1,SP
        RETN
 

Line No.	Rev	Author	Line
1	45	dgisselq	`;`
2			`;`
3			`;`
4			`;`
5			`divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1`
6			`TST -1,R1`
7			`; BNZ divu_valid_divide`
8			`CLR.Z R0 ; Should be a divide by zero error / trap`
9			`RETN.Z`
10			`divu_valid_divide:`
11			`SUB 1,SP`
12			`STO R3,1(SP)`
13			`;`
14			`LDI 1,R2 ; Here's where we record the bit we are working on`
15			`CLR R3 ; Here's where we build our result`
16			`; Our original loop rejoin point, before a touch of unrolling`
17			`CMP R1,R0`
18			`BRC divu_prep_next_bit`
19			`TST -1,R1`
20			`BLT divu_top_bit_set`
21			`divu_rotate_up_r1:`
22			`LSL 1,R2`
23			`LSL 1,R1`
24			`/*`
25			`CMP R1,R0`
26			`BRC divu_prep_next_bit`
27			`TST -1,R1`
28			`BGT divu_rotate_up_r1`
29			`*/`
30			`BLT divu_top_bit_set`
31			`CMP R1,R0`
32			`BRC divu_prep_next_bit`
33			`;`
34			`LSL 1,R2`
35			`LSL 1,R1`
36			`BLT divu_top_bit_set`
37			`CMP R1,R0`
38			`BRC divu_prep_next_bit`
39			`;`
40			`LSL 1,R2`
41			`LSL 1,R1`
42			`BLT divu_top_bit_set`
43			`CMP R1,R0`
44			`BRC divu_prep_next_bit`
45			`;`
46			`LSL 1,R2`
47			`LSL 1,R1`
48			`BLT divu_top_bit_set`
49			`CMP R1,R0`
50			`BRC divu_prep_next_bit`
51			`BRA divu_rotate_up_r1`
52
53			`divu_top_bit_set:`
54			`CMP R1,R0`
55			`BRC divu_prep_next_bit`
56			`SUB R1,R0`
57			`OR R2,R3`
58			`divu_prep_next_bit:`
59			`LSR 1,R1`
60			`LSR 1,R2`
61			`BZ divu_record_result`
62			`;`
63			`divu_next_loop:`
64			`CMP R1,R0 ;`
65			`SUB.GE R1,R0 ; We also switch to signed arithmetic, since`
66			`OR.GE R2,R3 ; after the first bit, we are signed`
67			`LSR 1,R1`
68			`LSR 1,R2`
69			`BZ divu_record_result`
70			`;`
71			`CMP R1,R0`
72			`SUB.GE R1,R0`
73			`OR.GE R2,R3`
74			`LSR 1,R1`
75			`LSR 1,R2`
76			`BZ divu_record_result`
77			`;`
78			`CMP R1,R0`
79			`SUB.GE R1,R0`
80			`OR.GE R2,R3`
81			`LSR 1,R1`
82			`LSR 1,R2`
83			`BZ divu_record_result`
84			`;`
85			`CMP R1,R0`
86			`SUB.GE R1,R0`
87			`OR.GE R2,R3`
88			`LSR 1,R1`
89			`LSR 1,R2`
90			`BNZ divu_next_loop`
91
92			`divu_record_result:`
93			`MOV R0,R1`
94			`MOV R3,R0`
95			`LOD 1(SP),R3`
96			`ADD 1,SP`
97			`RETN`
98

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[/] [zipcpu/] [trunk/] [sw/] [lib/] [divu.S] - Blame information for rev 56