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[/] [zipcpu/] [trunk/] [sw/] [lib/] [divu.S] - Blame information for rev 63

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     divu.S
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      Zip assembly file for running doing an unsigned divide.
;               This routine is also called by the signed divide.
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
;
;
divu:   ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1
        TST     -1,R1
        ; BNZ   divu_valid_divide
        CLR.Z   R0              ; Should be a divide by zero error / trap
        RETN.Z
divu_valid_divide:
        SUB     1,SP
        STO     R3,1(SP)
        ;
        LDI     1,R2    ; Here's where we record the bit we are working on
        CLR     R3      ; Here's where we build our result
; Our original loop rejoin point, before a touch of unrolling
        CMP     R1,R0
        BRC     divu_prep_next_bit
        TST     -1,R1
        BLT     divu_top_bit_set
divu_rotate_up_r1:
        LSL     1,R2
        LSL     1,R1
/*
        CMP     R1,R0
        BRC     divu_prep_next_bit
        TST     -1,R1
        BGT     divu_rotate_up_r1
*/
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        ;
        LSL     1,R2
        LSL     1,R1
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        ;
        LSL     1,R2
        LSL     1,R1
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        ;
        LSL     1,R2
        LSL     1,R1
        BLT     divu_top_bit_set
        CMP     R1,R0
        BRC     divu_prep_next_bit
        BRA     divu_rotate_up_r1
 
divu_top_bit_set:
        CMP     R1,R0
        BRC     divu_prep_next_bit
        SUB     R1,R0
        OR      R2,R3
divu_prep_next_bit:
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
divu_next_loop:
        CMP     R1,R0           ;
        SUB.GE  R1,R0           ; We also switch to signed arithmetic, since
        OR.GE   R2,R3           ; after the first bit, we are signed
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
        CMP     R1,R0
        SUB.GE  R1,R0
        OR.GE   R2,R3
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
        CMP     R1,R0
        SUB.GE  R1,R0
        OR.GE   R2,R3
        LSR     1,R1
        LSR     1,R2
        BZ      divu_record_result
        ;
        CMP     R1,R0
        SUB.GE  R1,R0
        OR.GE   R2,R3
        LSR     1,R1
        LSR     1,R2
        BNZ     divu_next_loop
 
divu_record_result:
        MOV     R0,R1
        MOV     R3,R0
        LOD     1(SP),R3
        LOD     2(SP),R2
        ADD     1,SP
        JMP     R2
 

Line No.	Rev	Author	Line
1	59	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2	45	dgisselq	`;`
3	59	dgisselq	`; Filename: divu.S`
4	45	dgisselq	`;`
5	59	dgisselq	`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6	45	dgisselq	`;`
7	59	dgisselq	`; Purpose: Zip assembly file for running doing an unsigned divide.`
8			`; This routine is also called by the signed divide.`
9	45	dgisselq	`;`
10	59	dgisselq	`; Creator: Dan Gisselquist, Ph.D.`
11			`; Gisselquist Tecnology, LLC`
12			`;`
13			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
14			`;`
15			`; Copyright (C) 2015, Gisselquist Technology, LLC`
16			`;`
17			`; This program is free software (firmware): you can redistribute it and/or`
18			`; modify it under the terms of the GNU General Public License as published`
19			`; by the Free Software Foundation, either version 3 of the License, or (at`
20			`; your option) any later version.`
21			`;`
22			`; This program is distributed in the hope that it will be useful, but WITHOUT`
23			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
24			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
25			`; for more details.`
26			`;`
27			`; License: GPL, v3, as defined and found on www.gnu.org,`
28			`; http://www.gnu.org/licenses/gpl.html`
29			`;`
30			`;`
31			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
32			`;`
33			`;`
34			`;`
35	45	dgisselq	`divu: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1`
36			`TST -1,R1`
37			`; BNZ divu_valid_divide`
38			`CLR.Z R0 ; Should be a divide by zero error / trap`
39			`RETN.Z`
40			`divu_valid_divide:`
41			`SUB 1,SP`
42			`STO R3,1(SP)`
43			`;`
44			`LDI 1,R2 ; Here's where we record the bit we are working on`
45			`CLR R3 ; Here's where we build our result`
46			`; Our original loop rejoin point, before a touch of unrolling`
47			`CMP R1,R0`
48			`BRC divu_prep_next_bit`
49			`TST -1,R1`
50			`BLT divu_top_bit_set`
51			`divu_rotate_up_r1:`
52			`LSL 1,R2`
53			`LSL 1,R1`
54			`/*`
55			`CMP R1,R0`
56			`BRC divu_prep_next_bit`
57			`TST -1,R1`
58			`BGT divu_rotate_up_r1`
59			`*/`
60			`BLT divu_top_bit_set`
61			`CMP R1,R0`
62			`BRC divu_prep_next_bit`
63			`;`
64			`LSL 1,R2`
65			`LSL 1,R1`
66			`BLT divu_top_bit_set`
67			`CMP R1,R0`
68			`BRC divu_prep_next_bit`
69			`;`
70			`LSL 1,R2`
71			`LSL 1,R1`
72			`BLT divu_top_bit_set`
73			`CMP R1,R0`
74			`BRC divu_prep_next_bit`
75			`;`
76			`LSL 1,R2`
77			`LSL 1,R1`
78			`BLT divu_top_bit_set`
79			`CMP R1,R0`
80			`BRC divu_prep_next_bit`
81			`BRA divu_rotate_up_r1`
82
83			`divu_top_bit_set:`
84			`CMP R1,R0`
85			`BRC divu_prep_next_bit`
86			`SUB R1,R0`
87			`OR R2,R3`
88			`divu_prep_next_bit:`
89			`LSR 1,R1`
90			`LSR 1,R2`
91			`BZ divu_record_result`
92			`;`
93			`divu_next_loop:`
94			`CMP R1,R0 ;`
95			`SUB.GE R1,R0 ; We also switch to signed arithmetic, since`
96			`OR.GE R2,R3 ; after the first bit, we are signed`
97			`LSR 1,R1`
98			`LSR 1,R2`
99			`BZ divu_record_result`
100			`;`
101			`CMP R1,R0`
102			`SUB.GE R1,R0`
103			`OR.GE R2,R3`
104			`LSR 1,R1`
105			`LSR 1,R2`
106			`BZ divu_record_result`
107			`;`
108			`CMP R1,R0`
109			`SUB.GE R1,R0`
110			`OR.GE R2,R3`
111			`LSR 1,R1`
112			`LSR 1,R2`
113			`BZ divu_record_result`
114			`;`
115			`CMP R1,R0`
116			`SUB.GE R1,R0`
117			`OR.GE R2,R3`
118			`LSR 1,R1`
119			`LSR 1,R2`
120			`BNZ divu_next_loop`
121
122			`divu_record_result:`
123			`MOV R0,R1`
124			`MOV R3,R0`
125			`LOD 1(SP),R3`
126	59	dgisselq	`LOD 2(SP),R2`
127	45	dgisselq	`ADD 1,SP`
128	59	dgisselq	`JMP R2`
129	45	dgisselq

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[/] [zipcpu/] [trunk/] [sw/] [lib/] [divu.S] - Blame information for rev 63