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[/] [zipcpu/] [trunk/] [sw/] [lib/] [mpy32u.S] - Blame information for rev 53
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Author |
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| 1 |
45 |
dgisselq |
mpy32u: ; unsigned R0 * unsigned R1 -> unsigned R0:R1
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PUSH R2
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| 3 |
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PUSH R3
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PUSH R4
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MOV R0,R2
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MULU R1,R2 ; R2 = Low order bits, low(R0) * low(R1)
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| 7 |
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MOV R0,R3
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| 8 |
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LSR 16,R3 ; Put high order bits in lower half of R3
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| 9 |
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MULU R1,R3 ; R3 = Mid order bits, high(R0) * low(R1)
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| 10 |
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LSR 16,R1 ; R1 = High order bits of R1, being done w/ low order
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| 11 |
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MOV R1,R4 ;
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| 12 |
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MUL R0,R4 ; R4 = Mid order bits, low(R0) * high(R1)
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| 13 |
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LSR 16,R0
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| 14 |
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MULU R1,R0 ; R0 = High order bits, high(R0) * high(R1)
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| 15 |
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ADD R3,R4 ; R4 = sum of mid order bits
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| 16 |
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ADD.C 0x010000,R0 ; Add in the carry (if it happened)
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| 17 |
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MOV R4,R3
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LSR 16,R3
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| 19 |
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ADD R3,R0 ; R0 = high order bits plus high order mid-bits
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| 20 |
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LSL 16,R4
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| 21 |
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ADD R4,R2 ; R2 = low order bits plus low order mid-bits
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| 22 |
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ADD.C 1,R0 ; Add in the carry to R0 (if it happened)
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| 23 |
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MOV R2,R1 ; Place low order bits into R1
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| 24 |
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POP R4
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| 25 |
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POP R3
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POP R2
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RET
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