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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [sys.i] - Blame information for rev 125

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     sys.i
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      This is the beginnings of a system wide header file for the
;               Zip System.   It describes and declares the peripherals
;               that will the be used and referenced by the assembly files.
;
; Status:       As of August, 2015, I have no confidence that the preprocessor
;               can properly include this file.  It certainly cannot handle
;               macros (yet).
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Technology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
        sys.bus         equ     0xc0000000
        sys.breaken     equ     0x080
        sys.step        equ     0x040
        sys.gie         equ     0x020
        sys.sleep       equ     0x010
        sys.ccv         equ     0x008
        sys.ccn         equ     0x004
        sys.ccc         equ     0x002
        sys.ccz         equ     0x001
        sys.bus.pic     equ     0x000
        sys.bus.wdt     equ     0x001
        sys.bus.cache   equ     0x002
        sys.bus.ctrpic  equ     0x003
        sys.bus.tma     equ     0x004
        sys.bus.tmb     equ     0x005
        sys.bus.tmc     equ     0x006
 
 
 
; Define the location(s) of our peripherals,
#define sys.base        0xc0000000
#define sys.cache.base  0xc0100000
#struct sys
        pic
        wdt
        cache
        ctrpic
        tma
        tmb
        tmc
        jiffies
        mtask
        mstl
        mpstl
        mastl
        utask
        ustl
        upstl
        uastl
#endstruct
; and their associated interrupt vectors ...
#define CACHEINT        0x01
#define JIFFYINT        0x02    ;
#define TMCINT          0x04    ;
#define TMBINT          0x08    ;
#define TMAINT          0x10    ;
#define CTRPICINT       0x20    ; The aux interrupt controller
; Masks to send to enable those same vectors
#define CACHEINTEN      0x80010000
#define JIFFYINTEN      0x80020000
#define TMCINTEN        0x80040000
#define TMBINTEN        0x80080000
#define TMAINTEN        0x80100000
#define CTRPICEN        0x80200000
; And similar masks to disable them
#define CACHEINTDIS     0x00010000
#define JIFFYINTDIS     0x00020000
#define TMCINTDIS       0x00040000
#define TMBINTDIS       0x00080000
#define TMAINTDIS       0x00100000
#define CTRPICDIS       0x00200000
 
; Define our condition code bits
#define CCZ     0x001
#define CCC     0x002
#define CCN     0x004
#define CCV     0x008
#define CCSLEEP 0x010
#define CCGIE   0x020
#define CCSTEP  0x040
#define CCUBRK  0x080
 
; Now, some macros
#define PUSH(RG,SP)     SUB 1,SP                \
                        STO RG,1(SP)
#define POP(RG,SP)      LOD 1(SP),RG            \
                        ADD 1,SP
#define FJSR(LBL,RG)    MOV __here__+2(PC),RG   \
                        BRA LBL
#define FRET(RG)        MOV RG,PC
#define JSR(LBL,RG)     SUB 1,SP                \
                        MOV __here__+3(PC),RG   \
                        STO RG,1(SP)            \
                        BRA LBL                 \
                        ADD 1,SP
 
#define RET             LOD 1(SP),PC
#define SAVE_USER_CONTEXT(DA,DB,DC,DD,AR)       \
                        MOV -15(uSP),AR         \
                        MOV     uR0,DA          \
                        MOV     uR1,DB          \
                        MOV     uR2,DC          \
                        MOV     uR3,DD          \
                        STO     DA,(AR)         \
                        STO     DB,1(AR)        \
                        STO     DC,2(AR)        \
                        STO     DD,3(AR)        \
                        MOV     uR4,DA          \
                        MOV     uR5,DB          \
                        MOV     uR6,DC          \
                        MOV     uR7,DD          \
                        STO     DA,4(AR)        \
                        STO     DB,5(AR)        \
                        STO     DC,6(AR)        \
                        STO     DD,7(AR)        \
                        MOV     uR8,DA          \
                        MOV     uR9,DB          \
                        MOV     uR10,DC         \
                        MOV     uR11,DD         \
                        STO     DA,8(AR)        \
                        STO     DB,9(AR)        \
                        STO     DC,10(AR)       \
                        STO     DD,11(AR)       \
                        MOV     uR12,DA         \
                        MOV     uCC,DC          \
                        MOV     uPC,DD          \
                        STO     DA,12(AR)       \
                        STO     DC,13(AR)       \
                        STO     DD,14(AR)
#define RESTORE_USER_CONTEXT(DA,DB,DC,DD,AR)    \
                        LOD     (AR),DA         \
                        LOD     1(AR),DB        \
                        LOD     2(AR),DC        \
                        LOD     3(AR),DD        \
                        MOV     DA,uR0          \
                        MOV     DB,uR1          \
                        MOV     DC,uR2          \
                        MOV     DD,uR3          \
                        LOD     4(AR),DA        \
                        LOD     5(AR),DB        \
                        LOD     6(AR),DC        \
                        LOD     7(AR),DD        \
                        MOV     DA,uR4          \
                        MOV     DB,uR5          \
                        MOV     DC,uR6          \
                        MOV     DD,uR7          \
                        LOD     8(AR),DA        \
                        LOD     9(AR),DB        \
                        LOD     10(AR),DC       \
                        LOD     11(AR),DD       \
                        MOV     DA,uR8          \
                        MOV     DB,uR9          \
                        MOV     DC,uR10         \
                        MOV     DD,uR11         \
                        LOD     12(AR),DA       \
                        LOD     13(AR),DB       \
                        LOD     14(AR),DC       \
                        MOV     DA,uR12         \
                        MOV     DB,uCC          \
                        MOV     DC,uPC          \
                        MOV     15(AR),uSP
#define READ_USER_TRAP(RG)                      \
                        MOV     uCC,RG          \
                        AND     -256,RG

Line No.	Rev	Author	Line
1	13	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2			`;`
3			`; Filename: sys.i`
4			`;`
5			`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`;`
7			`; Purpose: This is the beginnings of a system wide header file for the`
8			`; Zip System. It describes and declares the peripherals`
9			`; that will the be used and referenced by the assembly files.`
10			`;`
11			`; Status: As of August, 2015, I have no confidence that the preprocessor`
12			`; can properly include this file. It certainly cannot handle`
13			`; macros (yet).`
14			`;`
15			`; Creator: Dan Gisselquist, Ph.D.`
16	69	dgisselq	`; Gisselquist Technology, LLC`
17	13	dgisselq	`;`
18			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
19			`;`
20			`; Copyright (C) 2015, Gisselquist Technology, LLC`
21			`;`
22			`; This program is free software (firmware): you can redistribute it and/or`
23			`; modify it under the terms of the GNU General Public License as published`
24			`; by the Free Software Foundation, either version 3 of the License, or (at`
25			`; your option) any later version.`
26			`;`
27			`; This program is distributed in the hope that it will be useful, but WITHOUT`
28			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
29			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
30			`; for more details.`
31			`;`
32			`; License: GPL, v3, as defined and found on www.gnu.org,`
33			`; http://www.gnu.org/licenses/gpl.html`
34			`;`
35			`;`
36			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
37			`;`
38			`sys.bus equ 0xc0000000`
39			`sys.breaken equ 0x080`
40			`sys.step equ 0x040`
41			`sys.gie equ 0x020`
42			`sys.sleep equ 0x010`
43			`sys.ccv equ 0x008`
44			`sys.ccn equ 0x004`
45			`sys.ccc equ 0x002`
46			`sys.ccz equ 0x001`
47	36	dgisselq	`sys.bus.pic equ 0x000`
48	13	dgisselq	`sys.bus.wdt equ 0x001`
49			`sys.bus.cache equ 0x002`
50			`sys.bus.ctrpic equ 0x003`
51			`sys.bus.tma equ 0x004`
52	46	dgisselq	`sys.bus.tmb equ 0x005`
53			`sys.bus.tmc equ 0x006`
54	13	dgisselq
55
56
57			`; Define the location(s) of our peripherals,`
58			`#define sys.base 0xc0000000`
59			`#define sys.cache.base 0xc0100000`
60			`#struct sys`
61			`pic`
62			`wdt`
63			`cache`
64			`ctrpic`
65			`tma`
66			`tmb`
67			`tmc`
68			`jiffies`
69			`mtask`
70			`mstl`
71			`mpstl`
72			`mastl`
73			`utask`
74			`ustl`
75			`upstl`
76			`uastl`
77			`#endstruct`
78			`; and their associated interrupt vectors ...`
79			`#define CACHEINT 0x01`
80			`#define JIFFYINT 0x02 ;`
81			`#define TMCINT 0x04 ;`
82			`#define TMBINT 0x08 ;`
83			`#define TMAINT 0x10 ;`
84			`#define CTRPICINT 0x20 ; The aux interrupt controller`
85			`; Masks to send to enable those same vectors`
86			`#define CACHEINTEN 0x80010000`
87			`#define JIFFYINTEN 0x80020000`
88			`#define TMCINTEN 0x80040000`
89			`#define TMBINTEN 0x80080000`
90			`#define TMAINTEN 0x80100000`
91			`#define CTRPICEN 0x80200000`
92			`; And similar masks to disable them`
93			`#define CACHEINTDIS 0x00010000`
94			`#define JIFFYINTDIS 0x00020000`
95			`#define TMCINTDIS 0x00040000`
96			`#define TMBINTDIS 0x00080000`
97			`#define TMAINTDIS 0x00100000`
98			`#define CTRPICDIS 0x00200000`
99
100			`; Define our condition code bits`
101			`#define CCZ 0x001`
102			`#define CCC 0x002`
103			`#define CCN 0x004`
104			`#define CCV 0x008`
105			`#define CCSLEEP 0x010`
106			`#define CCGIE 0x020`
107			`#define CCSTEP 0x040`
108			`#define CCUBRK 0x080`
109
110			`; Now, some macros`
111			`#define PUSH(RG,SP) SUB 1,SP \`
112	34	dgisselq	`STO RG,1(SP)`
113			`#define POP(RG,SP) LOD 1(SP),RG \`
114	13	dgisselq	`ADD 1,SP`
115			`#define FJSR(LBL,RG) MOV __here__+2(PC),RG \`
116	60	dgisselq	`BRA LBL`
117	13	dgisselq	`#define FRET(RG) MOV RG,PC`
118			`#define JSR(LBL,RG) SUB 1,SP \`
119			`MOV __here__+3(PC),RG \`
120	34	dgisselq	`STO RG,1(SP) \`
121	60	dgisselq	`BRA LBL \`
122	13	dgisselq	`ADD 1,SP`
123	69	dgisselq
124	34	dgisselq	`#define RET LOD 1(SP),PC`
125	69	dgisselq	`#define SAVE_USER_CONTEXT(DA,DB,DC,DD,AR) \`
126	36	dgisselq	`MOV -15(uSP),AR \`
127	69	dgisselq	`MOV uR0,DA \`
128			`MOV uR1,DB \`
129			`MOV uR2,DC \`
130			`MOV uR3,DD \`
131			`STO DA,(AR) \`
132			`STO DB,1(AR) \`
133			`STO DC,2(AR) \`
134			`STO DD,3(AR) \`
135			`MOV uR4,DA \`
136			`MOV uR5,DB \`
137			`MOV uR6,DC \`
138			`MOV uR7,DD \`
139			`STO DA,4(AR) \`
140			`STO DB,5(AR) \`
141			`STO DC,6(AR) \`
142			`STO DD,7(AR) \`
143			`MOV uR8,DA \`
144			`MOV uR9,DB \`
145			`MOV uR10,DC \`
146			`MOV uR11,DD \`
147			`STO DA,8(AR) \`
148			`STO DB,9(AR) \`
149			`STO DC,10(AR) \`
150			`STO DD,11(AR) \`
151			`MOV uR12,DA \`
152			`MOV uCC,DC \`
153			`MOV uPC,DD \`
154			`STO DA,12(AR) \`
155			`STO DC,13(AR) \`
156			`STO DD,14(AR)`
157			`#define RESTORE_USER_CONTEXT(DA,DB,DC,DD,AR) \`
158			`LOD (AR),DA \`
159			`LOD 1(AR),DB \`
160			`LOD 2(AR),DC \`
161			`LOD 3(AR),DD \`
162			`MOV DA,uR0 \`
163			`MOV DB,uR1 \`
164			`MOV DC,uR2 \`
165			`MOV DD,uR3 \`
166			`LOD 4(AR),DA \`
167			`LOD 5(AR),DB \`
168			`LOD 6(AR),DC \`
169			`LOD 7(AR),DD \`
170			`MOV DA,uR4 \`
171			`MOV DB,uR5 \`
172			`MOV DC,uR6 \`
173			`MOV DD,uR7 \`
174			`LOD 8(AR),DA \`
175			`LOD 9(AR),DB \`
176			`LOD 10(AR),DC \`
177			`LOD 11(AR),DD \`
178			`MOV DA,uR8 \`
179			`MOV DB,uR9 \`
180			`MOV DC,uR10 \`
181			`MOV DD,uR11 \`
182			`LOD 12(AR),DA \`
183			`LOD 13(AR),DB \`
184			`LOD 14(AR),DC \`
185			`MOV DA,uR12 \`
186			`MOV DB,uCC \`
187			`MOV DC,uPC \`
188			`MOV 15(AR),uSP`
189	13	dgisselq	`#define READ_USER_TRAP(RG) \`
190			`MOV uCC,RG \`
191			`AND -256,RG`

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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [sys.i] - Blame information for rev 125