URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [sys.i] - Blame information for rev 44

Go to most recent revision | Details | Compare with Previous | View Log


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     sys.i
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      This is the beginnings of a system wide header file for the
;               Zip System.   It describes and declares the peripherals
;               that will the be used and referenced by the assembly files.
;
; Status:       As of August, 2015, I have no confidence that the preprocessor
;               can properly include this file.  It certainly cannot handle
;               macros (yet).
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
        sys.bus         equ     0xc0000000
        sys.breaken     equ     0x080
        sys.step        equ     0x040
        sys.gie         equ     0x020
        sys.sleep       equ     0x010
        sys.ccv         equ     0x008
        sys.ccn         equ     0x004
        sys.ccc         equ     0x002
        sys.ccz         equ     0x001
        sys.bus.pic     equ     0x000
        sys.bus.wdt     equ     0x001
        sys.bus.cache   equ     0x002
        sys.bus.ctrpic  equ     0x003
        sys.bus.tma     equ     0x004
 
 
 
; Define the location(s) of our peripherals,
#define sys.base        0xc0000000
#define sys.cache.base  0xc0100000
#struct sys
        pic
        wdt
        cache
        ctrpic
        tma
        tmb
        tmc
        jiffies
        mtask
        mstl
        mpstl
        mastl
        utask
        ustl
        upstl
        uastl
#endstruct
; and their associated interrupt vectors ...
#define CACHEINT        0x01
#define JIFFYINT        0x02    ;
#define TMCINT          0x04    ;
#define TMBINT          0x08    ;
#define TMAINT          0x10    ;
#define CTRPICINT       0x20    ; The aux interrupt controller
; Masks to send to enable those same vectors
#define CACHEINTEN      0x80010000
#define JIFFYINTEN      0x80020000
#define TMCINTEN        0x80040000
#define TMBINTEN        0x80080000
#define TMAINTEN        0x80100000
#define CTRPICEN        0x80200000
; And similar masks to disable them
#define CACHEINTDIS     0x00010000
#define JIFFYINTDIS     0x00020000
#define TMCINTDIS       0x00040000
#define TMBINTDIS       0x00080000
#define TMAINTDIS       0x00100000
#define CTRPICDIS       0x00200000
 
; Define our condition code bits
#define CCZ     0x001
#define CCC     0x002
#define CCN     0x004
#define CCV     0x008
#define CCSLEEP 0x010
#define CCGIE   0x020
#define CCSTEP  0x040
#define CCUBRK  0x080
 
; Now, some macros
#define PUSH(RG,SP)     SUB 1,SP                \
                        STO RG,1(SP)
#define POP(RG,SP)      LOD 1(SP),RG            \
                        ADD 1,SP
#define FJSR(LBL,RG)    MOV __here__+2(PC),RG   \
                        JMP LBL
#define FRET(RG)        MOV RG,PC
#define JSR(LBL,RG)     SUB 1,SP                \
                        MOV __here__+3(PC),RG   \
                        STO RG,1(SP)            \
                        JMP LBL                 \
                        ADD 1,SP
#define RET             LOD 1(SP),PC
#define SAVE_USER_CONTEXT(DR,AR)                \
                        MOV -15(uSP),AR         \
                        MOV     uPC,DR          \
                        STO     DR,15(AR)       \
                        MOV     uCC,DR          \
                        STO     DR,14(AR)       \
                        MOV     uR12,DR         \
                        STO     DR,13(AR)       \
                        MOV     uR11,DR         \
                        STO     DR,12(AR)       \
                        MOV     uR10,DR         \
                        STO     DR,11(AR)       \
                        MOV     uR9,DR          \
                        STO     DR,10(AR)       \
                        MOV     uR8,DR          \
                        STO     DR,9(AR)        \
                        MOV     uR7,DR          \
                        STO     DR,8(AR)        \
                        MOV     uR6,DR          \
                        STO     DR,7(AR)        \
                        MOV     uR5,DR          \
                        STO     DR,6(AR)        \
                        MOV     uR4,DR          \
                        STO     DR,5(AR)        \
                        MOV     uR3,DR          \
                        STO     DR,4(AR)        \
                        MOV     uR2,DR          \
                        STO     DR,3(AR)        \
                        MOV     uR1,DR          \
                        STO     DR,2(AR)        \
                        MOV     uR0,DR          \
                        STO     DR,1(AR)
#define RESTORE_USER_CONTEXT(DR,AR)             \
                        LOD     1(AR),DR        \
                        MOV     DR,uR0          \
                        LOD     2(AR),DR        \
                        MOV     DR,uR1          \
                        LOD     3(AR),DR        \
                        MOV     DR,uR2          \
                        LOD     4(AR),DR        \
                        MOV     DR,uR3          \
                        LOD     5(AR),DR        \
                        MOV     DR,uR4          \
                        LOD     6(AR),DR        \
                        MOV     DR,uR5          \
                        LOD     7(AR),DR        \
                        MOV     DR,uR6          \
                        LOD     8(AR),DR        \
                        MOV     DR,uR7          \
                        LOD     9(AR),DR        \
                        MOV     DR,uR8          \
                        LOD     10(AR),DR       \
                        MOV     DR,uR9          \
                        LOD     11(AR),DR       \
                        MOV     DR,uR10         \
                        LOD     12(AR),DR       \
                        MOV     DR,uR11         \
                        LOD     13(AR),DR       \
                        MOV     DR,uR12         \
                        LOD     14(AR),DR       \
                        MOV     DR,uCC          \
                        LOD     15(AR),DR       \
                        MOV     DR,uPC
#define READ_USER_TRAP(RG)                      \
                        MOV     uCC,RG          \
                        AND     -256,RG
 

Line No.	Rev	Author	Line
1	13	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2			`;`
3			`; Filename: sys.i`
4			`;`
5			`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`;`
7			`; Purpose: This is the beginnings of a system wide header file for the`
8			`; Zip System. It describes and declares the peripherals`
9			`; that will the be used and referenced by the assembly files.`
10			`;`
11			`; Status: As of August, 2015, I have no confidence that the preprocessor`
12			`; can properly include this file. It certainly cannot handle`
13			`; macros (yet).`
14			`;`
15			`; Creator: Dan Gisselquist, Ph.D.`
16			`; Gisselquist Tecnology, LLC`
17			`;`
18			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
19			`;`
20			`; Copyright (C) 2015, Gisselquist Technology, LLC`
21			`;`
22			`; This program is free software (firmware): you can redistribute it and/or`
23			`; modify it under the terms of the GNU General Public License as published`
24			`; by the Free Software Foundation, either version 3 of the License, or (at`
25			`; your option) any later version.`
26			`;`
27			`; This program is distributed in the hope that it will be useful, but WITHOUT`
28			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
29			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
30			`; for more details.`
31			`;`
32			`; License: GPL, v3, as defined and found on www.gnu.org,`
33			`; http://www.gnu.org/licenses/gpl.html`
34			`;`
35			`;`
36			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
37			`;`
38			`sys.bus equ 0xc0000000`
39			`sys.breaken equ 0x080`
40			`sys.step equ 0x040`
41			`sys.gie equ 0x020`
42			`sys.sleep equ 0x010`
43			`sys.ccv equ 0x008`
44			`sys.ccn equ 0x004`
45			`sys.ccc equ 0x002`
46			`sys.ccz equ 0x001`
47	36	dgisselq	`sys.bus.pic equ 0x000`
48	13	dgisselq	`sys.bus.wdt equ 0x001`
49			`sys.bus.cache equ 0x002`
50			`sys.bus.ctrpic equ 0x003`
51			`sys.bus.tma equ 0x004`
52
53
54
55			`; Define the location(s) of our peripherals,`
56			`#define sys.base 0xc0000000`
57			`#define sys.cache.base 0xc0100000`
58			`#struct sys`
59			`pic`
60			`wdt`
61			`cache`
62			`ctrpic`
63			`tma`
64			`tmb`
65			`tmc`
66			`jiffies`
67			`mtask`
68			`mstl`
69			`mpstl`
70			`mastl`
71			`utask`
72			`ustl`
73			`upstl`
74			`uastl`
75			`#endstruct`
76			`; and their associated interrupt vectors ...`
77			`#define CACHEINT 0x01`
78			`#define JIFFYINT 0x02 ;`
79			`#define TMCINT 0x04 ;`
80			`#define TMBINT 0x08 ;`
81			`#define TMAINT 0x10 ;`
82			`#define CTRPICINT 0x20 ; The aux interrupt controller`
83			`; Masks to send to enable those same vectors`
84			`#define CACHEINTEN 0x80010000`
85			`#define JIFFYINTEN 0x80020000`
86			`#define TMCINTEN 0x80040000`
87			`#define TMBINTEN 0x80080000`
88			`#define TMAINTEN 0x80100000`
89			`#define CTRPICEN 0x80200000`
90			`; And similar masks to disable them`
91			`#define CACHEINTDIS 0x00010000`
92			`#define JIFFYINTDIS 0x00020000`
93			`#define TMCINTDIS 0x00040000`
94			`#define TMBINTDIS 0x00080000`
95			`#define TMAINTDIS 0x00100000`
96			`#define CTRPICDIS 0x00200000`
97
98			`; Define our condition code bits`
99			`#define CCZ 0x001`
100			`#define CCC 0x002`
101			`#define CCN 0x004`
102			`#define CCV 0x008`
103			`#define CCSLEEP 0x010`
104			`#define CCGIE 0x020`
105			`#define CCSTEP 0x040`
106			`#define CCUBRK 0x080`
107
108			`; Now, some macros`
109			`#define PUSH(RG,SP) SUB 1,SP \`
110	34	dgisselq	`STO RG,1(SP)`
111			`#define POP(RG,SP) LOD 1(SP),RG \`
112	13	dgisselq	`ADD 1,SP`
113			`#define FJSR(LBL,RG) MOV __here__+2(PC),RG \`
114			`JMP LBL`
115			`#define FRET(RG) MOV RG,PC`
116			`#define JSR(LBL,RG) SUB 1,SP \`
117			`MOV __here__+3(PC),RG \`
118	34	dgisselq	`STO RG,1(SP) \`
119	13	dgisselq	`JMP LBL \`
120			`ADD 1,SP`
121	34	dgisselq	`#define RET LOD 1(SP),PC`
122	13	dgisselq	`#define SAVE_USER_CONTEXT(DR,AR) \`
123	36	dgisselq	`MOV -15(uSP),AR \`
124	13	dgisselq	`MOV uPC,DR \`
125	36	dgisselq	`STO DR,15(AR) \`
126	13	dgisselq	`MOV uCC,DR \`
127	34	dgisselq	`STO DR,14(AR) \`
128	13	dgisselq	`MOV uR12,DR \`
129	34	dgisselq	`STO DR,13(AR) \`
130	13	dgisselq	`MOV uR11,DR \`
131	34	dgisselq	`STO DR,12(AR) \`
132	13	dgisselq	`MOV uR10,DR \`
133	34	dgisselq	`STO DR,11(AR) \`
134	13	dgisselq	`MOV uR9,DR \`
135	34	dgisselq	`STO DR,10(AR) \`
136	13	dgisselq	`MOV uR8,DR \`
137	34	dgisselq	`STO DR,9(AR) \`
138	13	dgisselq	`MOV uR7,DR \`
139	34	dgisselq	`STO DR,8(AR) \`
140	13	dgisselq	`MOV uR6,DR \`
141	34	dgisselq	`STO DR,7(AR) \`
142	13	dgisselq	`MOV uR5,DR \`
143	34	dgisselq	`STO DR,6(AR) \`
144	13	dgisselq	`MOV uR4,DR \`
145	34	dgisselq	`STO DR,5(AR) \`
146	13	dgisselq	`MOV uR3,DR \`
147	34	dgisselq	`STO DR,4(AR) \`
148	13	dgisselq	`MOV uR2,DR \`
149	34	dgisselq	`STO DR,3(AR) \`
150	13	dgisselq	`MOV uR1,DR \`
151	34	dgisselq	`STO DR,2(AR) \`
152	13	dgisselq	`MOV uR0,DR \`
153	34	dgisselq	`STO DR,1(AR)`
154	13	dgisselq	`#define RESTORE_USER_CONTEXT(DR,AR) \`
155	34	dgisselq	`LOD 1(AR),DR \`
156	13	dgisselq	`MOV DR,uR0 \`
157	34	dgisselq	`LOD 2(AR),DR \`
158	13	dgisselq	`MOV DR,uR1 \`
159	34	dgisselq	`LOD 3(AR),DR \`
160	13	dgisselq	`MOV DR,uR2 \`
161	34	dgisselq	`LOD 4(AR),DR \`
162	13	dgisselq	`MOV DR,uR3 \`
163	34	dgisselq	`LOD 5(AR),DR \`
164	13	dgisselq	`MOV DR,uR4 \`
165	34	dgisselq	`LOD 6(AR),DR \`
166	13	dgisselq	`MOV DR,uR5 \`
167	34	dgisselq	`LOD 7(AR),DR \`
168	13	dgisselq	`MOV DR,uR6 \`
169	34	dgisselq	`LOD 8(AR),DR \`
170	13	dgisselq	`MOV DR,uR7 \`
171	34	dgisselq	`LOD 9(AR),DR \`
172	13	dgisselq	`MOV DR,uR8 \`
173	34	dgisselq	`LOD 10(AR),DR \`
174	13	dgisselq	`MOV DR,uR9 \`
175	34	dgisselq	`LOD 11(AR),DR \`
176	13	dgisselq	`MOV DR,uR10 \`
177	34	dgisselq	`LOD 12(AR),DR \`
178	13	dgisselq	`MOV DR,uR11 \`
179	34	dgisselq	`LOD 13(AR),DR \`
180	13	dgisselq	`MOV DR,uR12 \`
181	34	dgisselq	`LOD 14(AR),DR \`
182	36	dgisselq	`MOV DR,uCC \`
183	34	dgisselq	`LOD 15(AR),DR \`
184	13	dgisselq	`MOV DR,uPC`
185			`#define READ_USER_TRAP(RG) \`
186			`MOV uCC,RG \`
187			`AND -256,RG`
188

Browse

Tools

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [sys.i] - Blame information for rev 44