URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Filename:     test.S
;
; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
;
; Purpose:      A disorganized test, just showing some initial operation of
;               the CPU.  As a disorganized test, it doesn't prove anything
;               beyond the generic operation of the CPU.
;
; Status:       As of July, 2015, the assembler isn't sophisticated enough
;               to handle the address resolution needed to assemble this file.
;
; Creator:      Dan Gisselquist, Ph.D.
;               Gisselquist Tecnology, LLC
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; Copyright (C) 2015, Gisselquist Technology, LLC
;
; This program is free software (firmware): you can redistribute it and/or
; modify it under the terms of  the GNU General Public License as published
; by the Free Software Foundation, either version 3 of the License, or (at
; your option) any later version.
;
; This program is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
; for more details.
;
; License:      GPL, v3, as defined and found on www.gnu.org,
;               http://www.gnu.org/licenses/gpl.html
;
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
test:
        clr     r0
        mov     r0,r1
        mov     $1+r0,r2
        mov     $2+r0,r3
        mov     $22h+r0,r4
        mov     $377h+r0,ur5
        noop
        nop
        add     r2,r0
        add     $32,r0
        add     $-33,r0
        not.z   r0
        clrf    r0
        ldi     $5,r1
        cmp     $0+r0,r1
        not.lt  r0
        not.ge  r1
        lod     $-7+pc,r2
        ldihi   $deadh,r3
        ldihi   $beefh,r3
 
testbench:
        // Let's build a software test bench.
        clr     r12     ; R12 will point to our peripherals
        ldihi   $c000h,r12
        mov     r12,ur12
        mov     test_start,upc
        ldihi   $8001,r0
        ldilo   $-1,r0
        sto     r0,$1+r12
        rtu
        lod     r12,r0
        cmp     $0,r0
        bnz     $1
        halt
        busy
 
; Now for a series of tests.  If the test fails, call the trap
; interrupt with the test number that failed.  Upon completion,
; call the trap with #0.
 
; Now for a series of tests.  If the test fails, call the trap
; interrupt with the test number that failed.  Upon completion,
; call the trap with #0.
 
; Test LDI to PC
; Some data registers
        .dat    __here__+5
test_start:
        ldi     $2,r11
        lod     $-3+pc,pc
        clr     r11
        noop
        cmp     $0,r11
        sto.z   r11,(r12)
        add     $1,r0
        add     $1,r0
 
// Let's test whether overflow works
        ldi     $3,r11
        ldi     $-1,r0
        lsr     $1,r0
        add     $1,r0
        bv      $1
        sto     r11,(r12)
// Overflow set from subtraction
        ldi     $4,r11
        ldi     $1,r0
        .dat    0x5000001f              ; rol $31,r0
        sub     $1,r0
        bv      $1
        sto     r11,(r12)
// Overflow set from LSR
        ldi     $5,r11
        ldi     $1,r0
        .dat    0x5000001f              ; rol $31,r0
        lsr     $1,r0
        bv      $1
        sto     r11,(r12)
// Overflow set from LSL
        ldi     $6,r11
        ldi     $1,r0
        .dat    0x5000001e
        lsl     $1,r0
        bv      $1
        sto     r11,(r12)
 
// Overflow set from LSL, negative to positive
        ldi     $7,r11
        ldi     $1,r0
        .dat    0x5000001f; //  E: ROL $30,R0
        lsl     $1,r0
        bv      $1
        sto     r11,(r12)
 
// Test carry
        ldi     $0x010,r11
        ldi     $-1,r0
        add     $1,r0
        tst     $2,cc
        sto.z   r11,(r12)
// and carry from subtraction
        ldi     $17,r11
        sub     $1,r0
        tst     $2,cc
        sto.z   r11,(r12)
 
// Let's try a loop: for i=0; i<5; i++)
//      We'll use R0=i, Immediates for 5
for_loop:
        ldi     $18,r11
        clr     r0
        noop
        add     $1,r0
        cmp     $5,r0
        blt     for_loop
//
// Let's try a reverse loop.  Such loops are usually cheaper to
// implement, and this one is no different: 2 loop instructions
// (minus setup instructions) vs 3 from before.
// R0 = 5; (from before)
// do {
// } while (R0 > 0);
bgt_loop:
        ldi     $19,r11
        noop
        sub     $1,r0
        bgt     bgt_loop
 
// How about the same thing with a >= comparison?
// R1 = 5; // Need to do this explicitly
// do {
// } while(R1 >= 0);
        ldi     $20,r00
        ldi     $5,r1
bge_loop:
        noop
        sub     $1,r1
        bge     bge_loop
 
// Let's try the reverse loop again, only this time we'll store our
// loop variable in memory.
// R0 = 5; (from before)
// do {
// } while (R0 > 0);
        ldi     $21,r11
        bra     $1
loop_var:
        .dat    0
mem_loop:
        mov     $-2+pc,r1
        clr     r2
        ldi     $5,r0
        sto     r1,(r0)
        add     $1,r2
        add     $14,r0
        lod     (r1),r0
        sub     $1,r0
        bgt     $-6
        cmp     $5,r2
        sto.ne  r11,(r12)
 
// Return success / Test the trap interrupt
        clr     r11
        sto     r11,(r12)
        noop
        noop
 
// Go into an infinite loop if the trap fails
// Permanent loop instruction -- a busy halt if you will
        busy
 
// And, in case we miss a halt ...
        halt

Browse

Tools

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	dgisselq	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
2			`;`
3			`; Filename: test.S`
4			`;`
5			`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`;`
7			`; Purpose: A disorganized test, just showing some initial operation of`
8			`; the CPU. As a disorganized test, it doesn't prove anything`
9			`; beyond the generic operation of the CPU.`
10			`;`
11			`; Status: As of July, 2015, the assembler isn't sophisticated enough`
12			`; to handle the address resolution needed to assemble this file.`
13			`;`
14			`; Creator: Dan Gisselquist, Ph.D.`
15			`; Gisselquist Tecnology, LLC`
16			`;`
17			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
18			`;`
19			`; Copyright (C) 2015, Gisselquist Technology, LLC`
20			`;`
21			`; This program is free software (firmware): you can redistribute it and/or`
22			`; modify it under the terms of the GNU General Public License as published`
23			`; by the Free Software Foundation, either version 3 of the License, or (at`
24			`; your option) any later version.`
25			`;`
26			`; This program is distributed in the hope that it will be useful, but WITHOUT`
27			`; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
28			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
29			`; for more details.`
30			`;`
31			`; License: GPL, v3, as defined and found on www.gnu.org,`
32			`; http://www.gnu.org/licenses/gpl.html`
33			`;`
34			`;`
35			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
36			`;`
37			`test:`
38			`clr r0`
39			`mov r0,r1`
40			`mov $1+r0,r2`
41			`mov $2+r0,r3`
42			`mov $22h+r0,r4`
43			`mov $377h+r0,ur5`
44			`noop`
45			`nop`
46			`add r2,r0`
47			`add $32,r0`
48			`add $-33,r0`
49			`not.z r0`
50			`clrf r0`
51			`ldi $5,r1`
52			`cmp $0+r0,r1`
53			`not.lt r0`
54			`not.ge r1`
55			`lod $-7+pc,r2`
56			`ldihi $deadh,r3`
57			`ldihi $beefh,r3`
58
59			`testbench:`
60			`// Let's build a software test bench.`
61			`clr r12 ; R12 will point to our peripherals`
62			`ldihi $c000h,r12`
63			`mov r12,ur12`
64			`mov test_start,upc`
65			`ldihi $8001,r0`
66			`ldilo $-1,r0`
67			`sto r0,$1+r12`
68			`rtu`
69			`lod r12,r0`
70			`cmp $0,r0`
71			`bnz $1`
72			`halt`
73			`busy`
74
75			`; Now for a series of tests. If the test fails, call the trap`
76			`; interrupt with the test number that failed. Upon completion,`
77			`; call the trap with #0.`
78
79			`; Now for a series of tests. If the test fails, call the trap`
80			`; interrupt with the test number that failed. Upon completion,`
81			`; call the trap with #0.`
82
83			`; Test LDI to PC`
84			`; Some data registers`
85			`.dat __here__+5`
86			`test_start:`
87			`ldi $2,r11`
88			`lod $-3+pc,pc`
89			`clr r11`
90			`noop`
91			`cmp $0,r11`
92			`sto.z r11,(r12)`
93			`add $1,r0`
94			`add $1,r0`
95
96			`// Let's test whether overflow works`
97			`ldi $3,r11`
98			`ldi $-1,r0`
99			`lsr $1,r0`
100			`add $1,r0`
101			`bv $1`
102			`sto r11,(r12)`
103			`// Overflow set from subtraction`
104			`ldi $4,r11`
105			`ldi $1,r0`
106			`.dat 0x5000001f ; rol $31,r0`
107			`sub $1,r0`
108			`bv $1`
109			`sto r11,(r12)`
110			`// Overflow set from LSR`
111			`ldi $5,r11`
112			`ldi $1,r0`
113			`.dat 0x5000001f ; rol $31,r0`
114			`lsr $1,r0`
115			`bv $1`
116			`sto r11,(r12)`
117			`// Overflow set from LSL`
118			`ldi $6,r11`
119			`ldi $1,r0`
120			`.dat 0x5000001e`
121			`lsl $1,r0`
122			`bv $1`
123			`sto r11,(r12)`
124
125			`// Overflow set from LSL, negative to positive`
126			`ldi $7,r11`
127			`ldi $1,r0`
128			`.dat 0x5000001f; // E: ROL $30,R0`
129			`lsl $1,r0`
130			`bv $1`
131			`sto r11,(r12)`
132
133			`// Test carry`
134			`ldi $0x010,r11`
135			`ldi $-1,r0`
136			`add $1,r0`
137			`tst $2,cc`
138			`sto.z r11,(r12)`
139			`// and carry from subtraction`
140			`ldi $17,r11`
141			`sub $1,r0`
142			`tst $2,cc`
143			`sto.z r11,(r12)`
144
145			`// Let's try a loop: for i=0; i<5; i++)`
146			`// We'll use R0=i, Immediates for 5`
147			`for_loop:`
148			`ldi $18,r11`
149			`clr r0`
150			`noop`
151			`add $1,r0`
152			`cmp $5,r0`
153			`blt for_loop`
154			`//`
155			`// Let's try a reverse loop. Such loops are usually cheaper to`
156			`// implement, and this one is no different: 2 loop instructions`
157			`// (minus setup instructions) vs 3 from before.`
158			`// R0 = 5; (from before)`
159			`// do {`
160			`// } while (R0 > 0);`
161			`bgt_loop:`
162			`ldi $19,r11`
163			`noop`
164			`sub $1,r0`
165			`bgt bgt_loop`
166
167			`// How about the same thing with a >= comparison?`
168			`// R1 = 5; // Need to do this explicitly`
169			`// do {`
170			`// } while(R1 >= 0);`
171			`ldi $20,r00`
172			`ldi $5,r1`
173			`bge_loop:`
174			`noop`
175			`sub $1,r1`
176			`bge bge_loop`
177
178			`// Let's try the reverse loop again, only this time we'll store our`
179			`// loop variable in memory.`
180			`// R0 = 5; (from before)`
181			`// do {`
182			`// } while (R0 > 0);`
183			`ldi $21,r11`
184			`bra $1`
185			`loop_var:`
186			`.dat 0`
187			`mem_loop:`
188			`mov $-2+pc,r1`
189			`clr r2`
190			`ldi $5,r0`
191			`sto r1,(r0)`
192			`add $1,r2`
193			`add $14,r0`
194			`lod (r1),r0`
195			`sub $1,r0`
196			`bgt $-6`
197			`cmp $5,r2`
198			`sto.ne r11,(r12)`
199
200			`// Return success / Test the trap interrupt`
201			`clr r11`
202			`sto r11,(r12)`
203			`noop`
204			`noop`
205
206			`// Go into an infinite loop if the trap fails`
207			`// Permanent loop instruction -- a busy halt if you will`
208			`busy`
209
210			`// And, in case we miss a halt ...`
211			`halt`