URL
https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [sw/] [zipdbg/] [README] - Blame information for rev 46
Go to most recent revision |
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
26 |
dgisselq |
|
2 |
|
|
This directory contains the Zip System Debugger. If you wish to use it,
|
3 |
|
|
you'll need to define something that implements the DEVBUS interface,
|
4 |
|
|
as found in devbus.h. Basically, the debugger expects to interact with the
|
5 |
|
|
Zip System across a 32-bit bus. Since this interaction is hardware system
|
6 |
|
|
specific, the implementation for your system isn't provided here.
|
7 |
|
|
|
8 |
31 |
dgisselq |
If you are wondering what the Zip System Debugger looks like, you'll find
|
9 |
|
|
that it works in a fashion very similar to the bench test program zippy_tb
|
10 |
|
|
found in the bench/cpp directory. The big difference is and will be that
|
11 |
|
|
zippy_tb allows clock for clock testing, whereas the debugger allows
|
12 |
|
|
instruction to instruction testing. There isn't supposed to be any difference
|
13 |
|
|
between the two, but there may be. This is why I run the zippy_tb program:
|
14 |
|
|
to find errors in the CPU, whereas a normal debugger is supposed to find
|
15 |
|
|
errors in the user program.
|
16 |
|
|
|
17 |
|
|
Now that I have break point functionality in the CPU, I hope to add
|
18 |
|
|
breakpoints to the debugger.
|
19 |
|
|
|
20 |
26 |
dgisselq |
Contact me if you need help building such a capability for your system.
|
21 |
|
|
My current implementation transforms a UART signal into 32-bit wishbone
|
22 |
|
|
bus interactions which then support this CPU.
|
23 |
|
|
|
24 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.