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[/] [zpu/] [trunk/] [zpu/] [example/] [sim_small_fpga_top_noint.vhd] - Blame information for rev 95

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1 93 oharboe
-- ZPU
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--
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-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
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-- 
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-- The FreeBSD license
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-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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--    copyright notice, this list of conditions and the following
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--    disclaimer in the documentation and/or other materials
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--    provided with the distribution.
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-- 
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use ieee.numeric_std.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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library work;
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use work.zpu_config.all;
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use work.zpupkg.all;
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entity fpga_top is
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end fpga_top;
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architecture behave of fpga_top is
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signal clk : std_logic;
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signal  areset                  : std_logic := '1';
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component  zpu_io is
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  generic (
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           log_file:       string  := "log.txt"
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          );
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  port(
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        clk         : in std_logic;
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        areset        : in std_logic;
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                busy : out std_logic;
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                writeEnable : in std_logic;
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                readEnable : in std_logic;
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                write   : in std_logic_vector(wordSize-1 downto 0);
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                read    : out std_logic_vector(wordSize-1 downto 0);
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                addr : in std_logic_vector(maxAddrBit downto minAddrBit)
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                );
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end component;
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signal                    mem_busy : std_logic;
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signal                    mem_read : std_logic_vector(wordSize-1 downto 0);
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signal                    mem_write : std_logic_vector(wordSize-1 downto 0);
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signal                    mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
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signal                    mem_writeEnable : std_logic;
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signal                    mem_readEnable : std_logic;
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signal                    mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
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signal                    enable : std_logic;
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signal                    dram_mem_busy : std_logic;
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signal                    dram_mem_read : std_logic_vector(wordSize-1 downto 0);
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signal                    dram_mem_write : std_logic_vector(wordSize-1 downto 0);
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signal                    dram_mem_writeEnable : std_logic;
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signal                    dram_mem_readEnable : std_logic;
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signal                    dram_mem_writeMask: std_logic_vector(wordBytes-1 downto 0);
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signal                    io_busy : std_logic;
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signal                    io_mem_read : std_logic_vector(wordSize-1 downto 0);
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signal                    io_mem_writeEnable : std_logic;
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signal                    io_mem_readEnable : std_logic;
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signal                    dram_ready : std_logic;
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signal                    io_ready : std_logic;
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signal                    io_reading : std_logic;
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signal break : std_logic;
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begin
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        zpu: zpu_core port map (
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                clk => clk ,
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                areset => areset,
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                enable => enable,
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                in_mem_busy => mem_busy,
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                mem_read => mem_read,
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                mem_write => mem_write,
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                out_mem_addr => mem_addr,
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                out_mem_writeEnable => mem_writeEnable,
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                out_mem_readEnable => mem_readEnable,
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                mem_writeMask => mem_writeMask,
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                interrupt => '0',
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                break  => break);
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        ioMap: zpu_io port map (
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        clk => clk,
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                areset => areset,
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                busy => io_busy,
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                writeEnable => io_mem_writeEnable,
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                readEnable => io_mem_readEnable,
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                write   => mem_write,
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                read    => io_mem_read,
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                addr => mem_addr(maxAddrBit downto minAddrBit)
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        );
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        dram_mem_writeEnable <= mem_writeEnable and not mem_addr(ioBit);
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        dram_mem_readEnable <= mem_readEnable and not mem_addr(ioBit);
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        io_mem_writeEnable <= mem_writeEnable and mem_addr(ioBit);
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        io_mem_readEnable <= mem_readEnable and mem_addr(ioBit);
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        mem_busy <= io_busy;
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        -- Memory reads either come from IO or DRAM. We need to pick the right one.
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        memorycontrol:
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        process(dram_mem_read, dram_ready, io_ready, io_mem_read)
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        begin
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                mem_read <= (others => 'U');
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                if dram_ready='1' then
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                        mem_read <= dram_mem_read;
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                end if;
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                if io_ready='1' then
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                        mem_read <= (others => '0');
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                        mem_read <= io_mem_read;
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                end if;
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        end process;
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        io_ready <= (io_reading or io_mem_readEnable) and not io_busy;
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        memoryControlSync:
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        process(clk, areset)
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        begin
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                if areset = '1' then
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                        enable <= '0';
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                        io_reading <= '0';
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                        dram_ready <= '0';
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                elsif (clk'event and clk = '1') then
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                        enable <= '1';
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                        io_reading <= io_busy or io_mem_readEnable;
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                        dram_ready<=dram_mem_readEnable;
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                end if;
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        end process;
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        -- wiggle the clock @ 100MHz
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        clock : PROCESS
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           begin
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                        clk <= '0';
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                   wait for 5 ns;
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                        clk <= '1';
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                   wait for 5 ns;
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                   areset <= '0';
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        end PROCESS clock;
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end behave;

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