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[/] [zpu/] [trunk/] [zpu/] [zpu4/] [core/] [zpupkg.vhd] - Blame information for rev 96

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1 93 oharboe
-- ZPU
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--
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-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
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-- 
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-- The FreeBSD license
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-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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--    copyright notice, this list of conditions and the following
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--    disclaimer in the documentation and/or other materials
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--    provided with the distribution.
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-- 
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.zpu_config.all;
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package zpupkg is
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        -- This bit is set for read/writes to IO
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        -- FIX!!! eventually this should be set to wordSize-1 so as to
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        -- to make the address of IO independent of amount of memory
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        -- reserved for CPU. Requires trivial tweaks in toolchain/runtime
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        -- libraries.
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        constant byteBits                       : integer := wordPower-3; -- # of bits in a word that addresses bytes
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        constant maxAddrBit                     : integer := maxAddrBitIncIO-1;
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        constant ioBit                          : integer := maxAddrBit+1;
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        constant wordSize                       : integer := 2**wordPower;
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        constant wordBytes                      : integer := wordSize/8;
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        constant minAddrBit                     : integer := byteBits;
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        -- configurable internal stack size. Probably going to be 16 after toolchain is done
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        constant        stack_bits              : integer := 5;
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        constant        stack_size              : integer := 2**stack_bits;
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        component dualport_ram is
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        port (clk : in std_logic;
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                memAWriteEnable : in std_logic;
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                memAAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
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                memAWrite : in std_logic_vector(wordSize-1 downto 0);
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                memARead : out std_logic_vector(wordSize-1 downto 0);
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                memBWriteEnable : in std_logic;
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                memBAddr : in std_logic_vector(maxAddrBitBRAM downto minAddrBit);
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                memBWrite : in std_logic_vector(wordSize-1 downto 0);
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                memBRead : out std_logic_vector(wordSize-1 downto 0));
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        end component;
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        component dram is
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                port (clk : in std_logic;
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                        areset : in std_logic;
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                        mem_writeEnable : in std_logic;
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                        mem_readEnable : in std_logic;
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                        mem_addr : in std_logic_vector(maxAddrBit downto 0);
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                        mem_write : in std_logic_vector(wordSize-1 downto 0);
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                        mem_read : out std_logic_vector(wordSize-1 downto 0);
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                        mem_busy : out std_logic;
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                        mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
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        end component;
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        component trace is
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          port(
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                clk         : in std_logic;
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                begin_inst  : in std_logic;
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                pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
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                        opcode          : in std_logic_vector(7 downto 0);
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                        sp                      : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
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                        memA            : in std_logic_vector(wordSize-1 downto 0);
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                        memB            : in std_logic_vector(wordSize-1 downto 0);
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                        busy         : in std_logic;
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                        intSp           : in std_logic_vector(stack_bits-1 downto 0)
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                        );
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        end component;
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        component zpu_core is
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    port ( clk : in std_logic;
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                          areset : in std_logic;
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                          enable : in std_logic;
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                          in_mem_busy : in std_logic;
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                          mem_read : in std_logic_vector(wordSize-1 downto 0);
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                          mem_write : out std_logic_vector(wordSize-1 downto 0);
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                          out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
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                          out_mem_writeEnable : out std_logic;
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                          out_mem_readEnable : out std_logic;
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                          mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
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                          interrupt : in std_logic;
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                          break : out std_logic);
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        end component;
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        component timer is
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          port(
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               clk              : in std_logic;
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                         areset                         : in std_logic;
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                         we                                     : in std_logic;
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                         din                                    : in std_logic_vector(7 downto 0);
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                         adr                                    : in std_logic_vector(2 downto 0);
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                         dout                                   : out std_logic_vector(7 downto 0));
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        end component;
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        component  zpuio is
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                port (  areset                  : in std_logic;
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                                cpu_clk                 : in std_logic;
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                                clk_status              : in std_logic_vector(2 downto 0);
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                                cpu_din                 : in std_logic_vector(15 downto 0);
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                                cpu_a                   : in std_logic_vector(20 downto 0);
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                                cpu_we                  : in std_logic_vector(1 downto 0);
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                                cpu_re                  : in std_logic;
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                                cpu_dout                : inout std_logic_vector(15 downto 0));
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        end component;
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        -- opcode decode constants
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        constant        OpCode_Im               : std_logic_vector(7 downto 7) := "1";
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        constant        OpCode_StoreSP  : std_logic_vector(7 downto 5) := "010";
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        constant        OpCode_LoadSP   : std_logic_vector(7 downto 5) := "011";
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        constant        OpCode_Emulate  : std_logic_vector(7 downto 5) := "001";
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        constant        OpCode_AddSP    : std_logic_vector(7 downto 4) := "0001";
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        constant        OpCode_Short    : std_logic_vector(7 downto 4) := "0000";
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        constant        OpCode_Break    : std_logic_vector(3 downto 0) := "0000";
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        constant        OpCode_NA4      : std_logic_vector(3 downto 0) := "0001";
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        constant        OpCode_PushSP   : std_logic_vector(3 downto 0) := "0010";
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        constant        OpCode_NA3              : std_logic_vector(3 downto 0) := "0011";
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        constant        OpCode_PopPC    : std_logic_vector(3 downto 0) := "0100";
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        constant        OpCode_Add              : std_logic_vector(3 downto 0) := "0101";
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        constant        OpCode_And              : std_logic_vector(3 downto 0) := "0110";
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        constant        OpCode_Or               : std_logic_vector(3 downto 0) := "0111";
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        constant        OpCode_Load             : std_logic_vector(3 downto 0) := "1000";
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        constant        OpCode_Not              : std_logic_vector(3 downto 0) := "1001";
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        constant        OpCode_Flip             : std_logic_vector(3 downto 0) := "1010";
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        constant        OpCode_Nop              : std_logic_vector(3 downto 0) := "1011";
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        constant        OpCode_Store    : std_logic_vector(3 downto 0) := "1100";
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        constant        OpCode_PopSP    : std_logic_vector(3 downto 0) := "1101";
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        constant        OpCode_NA2              : std_logic_vector(3 downto 0) := "1110";
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        constant        OpCode_NA               : std_logic_vector(3 downto 0) := "1111";
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        constant        OpCode_Lessthan                         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
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        constant        OpCode_Lessthanorequal          : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
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        constant        OpCode_Ulessthan                        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
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        constant        OpCode_Ulessthanorequal         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
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        constant        OpCode_Swap                                     : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
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        constant        OpCode_Mult                                     : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
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        constant        OpCode_Lshiftright                      : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
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        constant        OpCode_Ashiftleft                       : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
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        constant        OpCode_Ashiftright                      : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
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        constant        OpCode_Call                                     : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
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        constant        OpCode_Eq                                       : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
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        constant        OpCode_Neq                                      : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
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        constant        OpCode_Sub                                      : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
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        constant        OpCode_Loadb                            : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
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        constant        OpCode_Storeb                           : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
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        constant        OpCode_Eqbranch                         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
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        constant        OpCode_Neqbranch                        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
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        constant        OpCode_Poppcrel                         : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
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        constant        OpCode_Pushspadd                        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
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        constant        OpCode_Mult16x16                        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
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        constant        OpCode_Callpcrel                        : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
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        constant OpCode_Size            : integer := 8;
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end zpupkg;

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