URL https://opencores.org/ocsvn/zx_ula/zx_ula/trunk

Subversion Repositories zx_ula

[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [signalview.wcfg] - Blame information for rev 5

Details | Compare with Previous | View Log




   
   
   
      
         
            
            
         
      
   
   
   
      clk7
      clk7
   
   
      Counters
      label
      128 128 255
      230 230 230
   
   
      hc[8:0]
      hc[8:0]
      UNSIGNEDDECRADIX
   
   
      vc[8:0]
      vc[8:0]
      UNSIGNEDDECRADIX
   
   
      Syncs
      label
      128 128 255
      230 230 230
   
   
      HBlank_n
      HBlank_n
   
   
      HSync_n
      HSync_n
   
   
      VSync_n
      VSync_n
   
   
      msk_int_n
      msk_int_n
   
   
      Control clocks
      label
      128 128 255
      230 230 230
   
   
      Border_n
      Border_n
   
   
      VidEN_n
      VidEN_n
   
   
      DataLatch_n
      DataLatch_n
   
   
      AttrLatch_n
      AttrLatch_n
   
   
      SLoad
      SLoad
   
   
      AOLatch_n
      AOLatch_n
   
   
      Data
      label
      128 128 255
      230 230 230
   
   
      va[13:0]
      va[13:0]
      HEXRADIX
   
   
      BitmapReg[7:0]
      BitmapReg[7:0]
      HEXRADIX
   
   
      SRegister[7:0]
      SRegister[7:0]
      HEXRADIX
   
   
      AttrReg[7:0]
      AttrReg[7:0]
      HEXRADIX
   
   
      AttrOut[7:0]
      AttrOut[7:0]
      HEXRADIX
   
   
      TV Output
      label
      128 128 255
      230 230 230
   
   
      RGB
      label
      UNSIGNEDDECRADIX
      
         g
         g
      
      
         r
         r
      
      
         b
         b
      
   
   
      i
      i
   
   
      csync
      csync
   
   
      Contention handler
      label
      128 128 255
      230 230 230
   
   
      CLKContention
      CLKContention
   
   
      Nor1
      Nor1
   
   
      Nor2
      Nor2
   
   
      CPU
      label
      128 128 255
      230 230 230
   
   
      clk7
      clk7
   
   
      clk
      clk
   
   
      a[15:0]
      a[15:0]
      HEXRADIX
   
   
      mreq_n
      mreq_n
   
   
      iorq_n
      iorq_n
   
   
      wr_n
      wr_n
   
   
      d[7:0]
      d[7:0]
      UNSIGNEDDECRADIX
   


Browse

Tools

Subversion Repositories zx_ula

[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [signalview.wcfg] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	mcleod_ide
2
3
4
5
6
7
8
9
10
11
12
13
14
15			`clk7`
16			`clk7`
17
18
19			`Counters`
20			`label`
21			`128 128 255`
22			`230 230 230`
23
24
25			`hc[8:0]`
26			`hc[8:0]`
27			`UNSIGNEDDECRADIX`
28
29
30			`vc[8:0]`
31			`vc[8:0]`
32			`UNSIGNEDDECRADIX`
33
34
35			`Syncs`
36			`label`
37			`128 128 255`
38			`230 230 230`
39
40
41			`HBlank_n`
42			`HBlank_n`
43
44
45			`HSync_n`
46			`HSync_n`
47
48
49			`VSync_n`
50			`VSync_n`
51
52
53			`msk_int_n`
54			`msk_int_n`
55
56
57			`Control clocks`
58			`label`
59			`128 128 255`
60			`230 230 230`
61
62
63			`Border_n`
64			`Border_n`
65
66
67			`VidEN_n`
68			`VidEN_n`
69
70
71			`DataLatch_n`
72			`DataLatch_n`
73
74
75			`AttrLatch_n`
76			`AttrLatch_n`
77
78
79			`SLoad`
80			`SLoad`
81
82
83			`AOLatch_n`
84			`AOLatch_n`
85
86
87			`Data`
88			`label`
89			`128 128 255`
90			`230 230 230`
91
92
93			`va[13:0]`
94			`va[13:0]`
95			`HEXRADIX`
96
97
98			`BitmapReg[7:0]`
99			`BitmapReg[7:0]`
100			`HEXRADIX`
101
102
103			`SRegister[7:0]`
104			`SRegister[7:0]`
105			`HEXRADIX`
106
107
108			`AttrReg[7:0]`
109			`AttrReg[7:0]`
110			`HEXRADIX`
111
112
113			`AttrOut[7:0]`
114			`AttrOut[7:0]`
115			`HEXRADIX`
116
117
118			`TV Output`
119			`label`
120			`128 128 255`
121			`230 230 230`
122
123
124			`RGB`
125			`label`
126			`UNSIGNEDDECRADIX`
127
128			`g`
129			`g`
130
131
132			`r`
133			`r`
134
135
136			`b`
137			`b`
138
139
140
141			`i`
142			`i`
143
144
145			`csync`
146			`csync`
147
148
149			`Contention handler`
150			`label`
151			`128 128 255`
152			`230 230 230`
153
154
155			`CLKContention`
156			`CLKContention`
157
158
159			`Nor1`
160			`Nor1`
161
162
163			`Nor2`
164			`Nor2`
165
166
167			`CPU`
168			`label`
169			`128 128 255`
170			`230 230 230`
171
172
173			`clk7`
174			`clk7`
175
176
177			`clk`
178			`clk`
179
180
181			`a[15:0]`
182			`a[15:0]`
183			`HEXRADIX`
184
185
186			`mreq_n`
187			`mreq_n`
188
189
190			`iorq_n`
191			`iorq_n`
192
193
194			`wr_n`
195			`wr_n`
196
197
198			`d[7:0]`
199			`d[7:0]`
200			`UNSIGNEDDECRADIX`
201
202