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[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [test_ula.v] - Blame information for rev 5

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`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   20:16:22 04/08/2012
// Design Name:   ula
// Module Name:   C:/proyectos_xilinx/ulaplus/test_reference_ula.v
// Project Name:  ulaplus
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ula
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
 
module test_reference_ula;
 
        // Inputs
        reg clk14;
        wire [15:0] a;
        wire [7:0] din;
        wire mreq_n;
        wire iorq_n;
        wire wr_n;
        wire rfsh_n;
        reg [7:0] vramdout;
        reg ear;
        reg [4:0] kbcolumns;
 
        // Outputs
        wire [7:0] dout;
        wire clkcpu;
        wire msk_int_n;
        wire [13:0] va;
        wire [7:0] vramdin;
        wire vramoe;
        wire vramcs;
        wire vramwe;
        wire mic;
        wire spk;
        wire [7:0] kbrows;
        wire r;
        wire g;
        wire b;
        wire i;
        wire csync;
 
        // Instantiate the Unit Under Test (UUT)
        ula uut (
                .clk14(clk14),
                .a(a),
                .din(din),
                .dout(dout),
                .mreq_n(mreq_n),
                .iorq_n(iorq_n),
                .rd_n(1'b1),
                .wr_n(wr_n),
                .rfsh_n(rfsh_n),
                .clkcpu(clkcpu),
                .msk_int_n(msk_int_n),
                .va(va),
                .vramdout(vramdout),
                .vramdin(vramdin),
                .vramoe(vramoe),
                .vramcs(vramcs),
                .vramwe(vramwe),
                .ear(ear),
                .mic(mic),
                .spk(spk),
                .kbrows(kbrows),
                .kbcolumns(kbcolumns),
                .r(r),
                .g(g),
                .b(b),
                .i(i),
                .csync(csync)
        );
 
        z80memio cpu (
                .clk(clkcpu),
           .a(a),
                .d(din),
                .mreq_n(mreq_n),
                .iorq_n(iorq_n),
                .wr_n(wr_n),
                .rfsh_n(rfsh_n)
        );
 
        initial begin
                // Initialize Inputs
                clk14 = 0;
                vramdout = 8'b01010101;
                ear = 0;
                kbcolumns = 0;
        end
 
        always begin
                clk14 = #35.714286 ~clk14;
        end
endmodule
 
module z80memr (
        input clk,
        output [15:0] a,
        output [7:0] d,
        output mreq,
        output rd
        );
 
        reg rmreq = 1;
        reg rrd = 1;
        assign mreq = rmreq;
        assign rd = rrd;
        reg [1:0] estado = 2;
        assign d = 8'bzzzzzzzz;
 
        reg [15:0] ra = 16'h7FFF;
        assign a = ra;
 
        always @(posedge clk) begin
                if (estado==2) begin
                        estado <= 0;
                        ra <= ~ra;
                end
                else
                        estado <= estado + 1;
        end
 
        always @(*) begin
                if (estado==0 && clk)
                        {rmreq,rrd} = 2'b11;
                else if (estado==0 && !clk)
                        {rmreq,rrd} = 2'b00;
                else if (estado==1)
                        {rmreq,rrd} = 2'b00;
                else if (estado==2 && clk)
                        {rmreq,rrd} = 2'b00;
                else
                        {rmreq,rrd} = 2'b11;
        end
endmodule
 
 
module z80memio (
        input clk,
        output [15:0] a,
        output [7:0] d,
        output mreq_n,
        output iorq_n,
        output wr_n,
        output rfsh_n
        );
 
        reg rmreq = 1;
        reg riorq = 1;
        reg rwr = 1;
        reg rrfsh = 1;
        assign mreq_n = rmreq;
        assign iorq_n = riorq;
        assign wr_n = rwr;
        assign rfsh_n = rrfsh;
 
        reg [1:0] estado = 0;
 
        reg [5:0] memioseq = 6'b011001;
        reg [5:0] io2seq =   5'b011000;
        reg [4:0] hiloseq =  5'b01010;
        wire memio = memioseq[0];  // 0 = mem, 1 = io
        wire hilo = hiloseq[0];   // 0 = access to lower RAM/Port FEh
        wire iohi = io2seq[0];    // 0 = port 00FF/00FE, 1 = port 40FE,40FF
 
 
        reg [15:0] ra;
        assign a = ra;
 
        reg [7:0] rd;
        assign d = rd;
 
        reg [7:0] iodata = 0;
        reg [7:0] memdata = 0;
        reg [15:0] memaddr = 16384;
 
        always @(posedge clk) begin
                if (estado==2 && !memio) begin
                        estado <= 0;
                        memioseq <= { memioseq[0], memioseq[5:1] };
                        hiloseq <= { hiloseq[0], hiloseq[4:1] };
                        io2seq <= { io2seq[0], io2seq[5:1] };
                        memdata <= memdata + 1;
                        if (memaddr == 23295)
                                memaddr <= 16384;
                        else
                                memaddr <= memaddr + 1;
                end
                else if (estado==3 && memio) begin
                        estado <= 0;
                        memioseq <= { memioseq[0], memioseq[5:1] };
                        hiloseq <= { hiloseq[0], hiloseq[4:1] };
                        io2seq <= { io2seq[0], io2seq[5:1] };
                        iodata <= iodata + 1;
                end
                else
                        estado <= estado + 1;
        end
 
        always @(*) begin
                if (memio) begin // if this is an I/O bus cycle...
                        case ({estado,clk})
                                3'b001 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = 8'bzzzzzzzz;
                                                        end
                                3'b000 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = iodata;
                                                        end
                                3'b011,3'b010,3'b101,3'b100,3'b111 :
                                         begin
                                                                {rmreq,riorq,rwr} = 3'b100;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = iodata;
                                                        end
                                3'b110 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {1'b0, iohi, 13'b0000001111111, hilo};
                                                                rd = iodata;
                                                        end
                        endcase
                end
                else begin      // this is a MEM bus cycle
                        case ({estado,clk})
                                3'b001 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = 8'bzzzzzzzz;
                                                        end
                                3'b000,3'b011 :
                                         begin
                                                                {rmreq,riorq,rwr} = 3'b011;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = memdata;
                                                        end
                                3'b010,3'b101 :
                                         begin
                                                                {rmreq,riorq,rwr} = 3'b010;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = memdata;
                                                        end
                                3'b100 : begin
                                                                {rmreq,riorq,rwr} = 3'b111;
                                                                ra = {hilo,memaddr[14:0]};
                                                                rd = memdata;
                                                        end
                        endcase
                end
        end
endmodule

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[/] [zx_ula/] [trunk/] [fpga_version/] [ula_test_for_ise_and_isim/] [test_ula.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	mcleod_ide	`timescale 1ns / 1ps
2
3			`////////////////////////////////////////////////////////////////////////////////`
4			`// Company:`
5			`// Engineer:`
6			`//`
7			`// Create Date: 20:16:22 04/08/2012`
8			`// Design Name: ula`
9			`// Module Name: C:/proyectos_xilinx/ulaplus/test_reference_ula.v`
10			`// Project Name: ulaplus`
11			`// Target Device:`
12			`// Tool versions:`
13			`// Description:`
14			`//`
15			`// Verilog Test Fixture created by ISE for module: ula`
16			`//`
17			`// Dependencies:`
18			`//`
19			`// Revision:`
20			`// Revision 0.01 - File Created`
21			`// Additional Comments:`
22			`//`
23			`////////////////////////////////////////////////////////////////////////////////`
24
25			`module test_reference_ula;`
26
27			`// Inputs`
28			`reg clk14;`
29			`wire [15:0] a;`
30			`wire [7:0] din;`
31			`wire mreq_n;`
32			`wire iorq_n;`
33			`wire wr_n;`
34			`wire rfsh_n;`
35			`reg [7:0] vramdout;`
36			`reg ear;`
37			`reg [4:0] kbcolumns;`
38
39			`// Outputs`
40			`wire [7:0] dout;`
41			`wire clkcpu;`
42			`wire msk_int_n;`
43			`wire [13:0] va;`
44			`wire [7:0] vramdin;`
45			`wire vramoe;`
46			`wire vramcs;`
47			`wire vramwe;`
48			`wire mic;`
49			`wire spk;`
50			`wire [7:0] kbrows;`
51			`wire r;`
52			`wire g;`
53			`wire b;`
54			`wire i;`
55			`wire csync;`
56
57			`// Instantiate the Unit Under Test (UUT)`
58			`ula uut (`
59			`.clk14(clk14),`
60			`.a(a),`
61			`.din(din),`
62			`.dout(dout),`
63			`.mreq_n(mreq_n),`
64			`.iorq_n(iorq_n),`
65			`.rd_n(1'b1),`
66			`.wr_n(wr_n),`
67			`.rfsh_n(rfsh_n),`
68			`.clkcpu(clkcpu),`
69			`.msk_int_n(msk_int_n),`
70			`.va(va),`
71			`.vramdout(vramdout),`
72			`.vramdin(vramdin),`
73			`.vramoe(vramoe),`
74			`.vramcs(vramcs),`
75			`.vramwe(vramwe),`
76			`.ear(ear),`
77			`.mic(mic),`
78			`.spk(spk),`
79			`.kbrows(kbrows),`
80			`.kbcolumns(kbcolumns),`
81			`.r(r),`
82			`.g(g),`
83			`.b(b),`
84			`.i(i),`
85			`.csync(csync)`
86			`);`
87
88			`z80memio cpu (`
89			`.clk(clkcpu),`
90			`.a(a),`
91			`.d(din),`
92			`.mreq_n(mreq_n),`
93			`.iorq_n(iorq_n),`
94			`.wr_n(wr_n),`
95			`.rfsh_n(rfsh_n)`
96			`);`
97
98			`initial begin`
99			`// Initialize Inputs`
100			`clk14 = 0;`
101			`vramdout = 8'b01010101;`
102			`ear = 0;`
103			`kbcolumns = 0;`
104			`end`
105
106			`always begin`
107			`clk14 = #35.714286 ~clk14;`
108			`end`
109			`endmodule`
110
111			`module z80memr (`
112			`input clk,`
113			`output [15:0] a,`
114			`output [7:0] d,`
115			`output mreq,`
116			`output rd`
117			`);`
118
119			`reg rmreq = 1;`
120			`reg rrd = 1;`
121			`assign mreq = rmreq;`
122			`assign rd = rrd;`
123			`reg [1:0] estado = 2;`
124			`assign d = 8'bzzzzzzzz;`
125
126			`reg [15:0] ra = 16'h7FFF;`
127			`assign a = ra;`
128
129			`always @(posedge clk) begin`
130			`if (estado==2) begin`
131			`estado <= 0;`
132			`ra <= ~ra;`
133			`end`
134			`else`
135			`estado <= estado + 1;`
136			`end`
137
138			`always @(*) begin`
139			`if (estado==0 && clk)`
140			`{rmreq,rrd} = 2'b11;`
141			`else if (estado==0 && !clk)`
142			`{rmreq,rrd} = 2'b00;`
143			`else if (estado==1)`
144			`{rmreq,rrd} = 2'b00;`
145			`else if (estado==2 && clk)`
146			`{rmreq,rrd} = 2'b00;`
147			`else`
148			`{rmreq,rrd} = 2'b11;`
149			`end`
150			`endmodule`
151
152
153			`module z80memio (`
154			`input clk,`
155			`output [15:0] a,`
156			`output [7:0] d,`
157			`output mreq_n,`
158			`output iorq_n,`
159			`output wr_n,`
160			`output rfsh_n`
161			`);`
162
163			`reg rmreq = 1;`
164			`reg riorq = 1;`
165			`reg rwr = 1;`
166			`reg rrfsh = 1;`
167			`assign mreq_n = rmreq;`
168			`assign iorq_n = riorq;`
169			`assign wr_n = rwr;`
170			`assign rfsh_n = rrfsh;`
171
172			`reg [1:0] estado = 0;`
173
174			`reg [5:0] memioseq = 6'b011001;`
175			`reg [5:0] io2seq = 5'b011000;`
176			`reg [4:0] hiloseq = 5'b01010;`
177			`wire memio = memioseq[0]; // 0 = mem, 1 = io`
178			`wire hilo = hiloseq[0]; // 0 = access to lower RAM/Port FEh`
179			`wire iohi = io2seq[0]; // 0 = port 00FF/00FE, 1 = port 40FE,40FF`
180
181
182			`reg [15:0] ra;`
183			`assign a = ra;`
184
185			`reg [7:0] rd;`
186			`assign d = rd;`
187
188			`reg [7:0] iodata = 0;`
189			`reg [7:0] memdata = 0;`
190			`reg [15:0] memaddr = 16384;`
191
192			`always @(posedge clk) begin`
193			`if (estado==2 && !memio) begin`
194			`estado <= 0;`
195			`memioseq <= { memioseq[0], memioseq[5:1] };`
196			`hiloseq <= { hiloseq[0], hiloseq[4:1] };`
197			`io2seq <= { io2seq[0], io2seq[5:1] };`
198			`memdata <= memdata + 1;`
199			`if (memaddr == 23295)`
200			`memaddr <= 16384;`
201			`else`
202			`memaddr <= memaddr + 1;`
203			`end`
204			`else if (estado==3 && memio) begin`
205			`estado <= 0;`
206			`memioseq <= { memioseq[0], memioseq[5:1] };`
207			`hiloseq <= { hiloseq[0], hiloseq[4:1] };`
208			`io2seq <= { io2seq[0], io2seq[5:1] };`
209			`iodata <= iodata + 1;`
210			`end`
211			`else`
212			`estado <= estado + 1;`
213			`end`
214
215			`always @(*) begin`
216			`if (memio) begin // if this is an I/O bus cycle...`
217			`case ({estado,clk})`
218			`3'b001 : begin`
219			`{rmreq,riorq,rwr} = 3'b111;`
220			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
221			`rd = 8'bzzzzzzzz;`
222			`end`
223			`3'b000 : begin`
224			`{rmreq,riorq,rwr} = 3'b111;`
225			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
226			`rd = iodata;`
227			`end`
228			`3'b011,3'b010,3'b101,3'b100,3'b111 :`
229			`begin`
230			`{rmreq,riorq,rwr} = 3'b100;`
231			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
232			`rd = iodata;`
233			`end`
234			`3'b110 : begin`
235			`{rmreq,riorq,rwr} = 3'b111;`
236			`ra = {1'b0, iohi, 13'b0000001111111, hilo};`
237			`rd = iodata;`
238			`end`
239			`endcase`
240			`end`
241			`else begin // this is a MEM bus cycle`
242			`case ({estado,clk})`
243			`3'b001 : begin`
244			`{rmreq,riorq,rwr} = 3'b111;`
245			`ra = {hilo,memaddr[14:0]};`
246			`rd = 8'bzzzzzzzz;`
247			`end`
248			`3'b000,3'b011 :`
249			`begin`
250			`{rmreq,riorq,rwr} = 3'b011;`
251			`ra = {hilo,memaddr[14:0]};`
252			`rd = memdata;`
253			`end`
254			`3'b010,3'b101 :`
255			`begin`
256			`{rmreq,riorq,rwr} = 3'b010;`
257			`ra = {hilo,memaddr[14:0]};`
258			`rd = memdata;`
259			`end`
260			`3'b100 : begin`
261			`{rmreq,riorq,rwr} = 3'b111;`
262			`ra = {hilo,memaddr[14:0]};`
263			`rd = memdata;`
264			`end`
265			`endcase`
266			`end`
267			`end`
268			`endmodule`