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antiquity |
//author :gurenliang
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//Email: gurenliang@gmail.com
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//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me.
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//version 0.3 correct some minor errors
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//version 0.3 add the option of frameID mode, by include common.v and judge the macro-varible frameIDfromRx
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//The top layer module provided full functions
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`include "common.v"
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module EthernetModule(reset, clk_10K,
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ff_clk, ff_en_source, ff_en_sink, ff_data_source, ff_data_sink, //ff_clk should be a 270.33KHz clock
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phy_rxd, phy_rxen, phy_rxclk, phy_rxer,
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phy_txd, phy_txen, phy_txclk, phy_txer,
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phy_reset, phy_col, phy_linksts, phy_crs,
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test1, test2, test3, test4
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);
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input reset, clk_10K, ff_clk;
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output phy_reset, test1, test2, test3, test4;
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input ff_en_sink, ff_data_sink; //sink is used to receive data from the demodulate module
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output ff_en_source, ff_data_source;//source is used to provide the modulation module with data get from ethernet
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input[3:0] phy_rxd; //MII interface for the phy chip
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input phy_rxclk, phy_rxer;
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output[3:0] phy_txd;
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output phy_txer, phy_txen;
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//declare them as inout port because when powerup reset, they act as output pins to config DM9161
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//after reset, phy_txclk and phy_rxen must be input ports
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inout phy_txclk, phy_col, phy_rxen, phy_linksts, phy_crs;
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wire out_en;
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wire rxen_in, txclk_in;
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`ifdef frameIDfromRx
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wire[23:0] frameid; //share the frameid between TxModule and RxModule
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`endif
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wire empty, start;
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InitModule initModule_inst(.init_clk(clk_10K), .reset(reset), .phy_reset(phy_reset), .out_en(out_en));
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tri_state tri_state_inst1(.d_in(txclk_in ), .d_out(1'b0), .out_en(out_en), .ioport(phy_txclk));
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tri_state tri_state_inst2(.d_in( ), .d_out(1'b0), .out_en(out_en), .ioport(phy_col));
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tri_state tri_state_inst3(.d_in(rxen_in ), .d_out(1'b0), .out_en(out_en), .ioport(phy_rxen));
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tri_state tri_state_inst4(.d_in( ), .d_out(1'b0), .out_en(out_en), .ioport(phy_linksts));
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tri_state tri_state_inst5(.d_in( ), .d_out(1'b1), .out_en(out_en), .ioport(phy_crs));
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TxModule TxModule_inst(.reset(out_en),
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.phy_txd(phy_txd), .phy_txen(phy_txen), .phy_txclk(txclk_in), .phy_txer(phy_txer),
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.ff_clk(ff_clk), .ff_en(ff_en_sink), .ff_data(ff_data_sink),
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`ifdef frameIDfromRx
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.frameid(frameid),
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`endif
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.start(start),
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.test1(), .test2(), .test3(), .test4());
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//.test1(test1), .test2(test2), .test3(test3), .test4(test4));
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RxModule RxModule_inst(.phy_rxd(phy_rxd), .phy_rxen(rxen_in), .phy_rxclk(phy_rxclk), .phy_rxer(phy_rxer),
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.ff_clk(ff_clk), .ff_data(ff_data_source), .ff_en(ff_en_source),
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`ifdef frameIDfromRx
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.frameid(frameid),
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`endif
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.start(start),
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//.test1(), .test2(), .test3(), .test4());
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.test1(test1), .test2(test2), .test3(test3), .test4(test4));
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endmodule
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