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[/] [10_100m_ethernet-fifo_convertor/] [verilog/] [Readme_important!!!!!.txt] - Blame information for rev 13

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1 10 antiquity
 
2 13 antiquity
Hi, folks,
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I am sorry for the incomplete document and absence of the test files for
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this project.  Here I provide the test cpp program, concise.cpp, by
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connecting the fifo_source and fifo_sink.  In the environment of Linux, run
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    g++ -o main concise.cpp
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and then
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    ./main
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11 13 antiquity
When the program is running, then you must be able to know how to operate
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the IP core.
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Although the pdf document downloaded is out of date, it can tell out some
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clue on how to design ethernet-fifo convertor. Now both the RxModule and
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TxModule are designed with RAM, so that it consumes lesser resource.
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This project has been tested on the hardware designed by myself. I have
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provided the circuit in the appendix of the document. These materials can
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be used directly. If you find something wrong with the codes or have any
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problem, please feel free to contact me.
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23 10 antiquity
Sincerely yours,
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Renliang Gu
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gurenliang@gmail.com
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13 Dec. 2009

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