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Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [layout/] [tcl/] [vsetup.tcl] - Blame information for rev 7

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Line No. Rev Author Line
1 7 kuzmi4
 
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create_project project_n1 ./ -part xc7k325tffg900-2
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set obj [get_projects project_n1]
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set_property "board_part" "xilinx.com:kc705:part0:1.2" $obj
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set_property "default_lib" "mblite" $obj
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set_property "sim.ip.auto_export_scripts" "1" $obj
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set_property "simulator_language" "Mixed" $obj
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set_property "target_language" "Verilog" $obj
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set_property "target_simulator" "ModelSim" $obj
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add_files -norecurse ../xdc/project_n1_b.sdc
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add_files -norecurse ../xdc/project_n1_p.sdc
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add_files -norecurse ../xdc/project_n1_t.sdc
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add_files -norecurse ../../src/rtl/mblite_top.sv
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add_files -norecurse ../../src/rtl/mblite_soc.sv
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add_files -norecurse ../../src/rtl/misc/clk_module.sv
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add_files -norecurse ../../src/rtl/misc/por_module.sv
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add_files -norecurse ../../src/rtl/misc/rst_sync.sv
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add_files -norecurse ../../src/rtl/wb_pio/hdl/wb_pio_top.sv
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add_files -norecurse ../../src/rtl/wb_uart/hdl/async.v
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add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_mscfifo.v
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add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_sdpram.v
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add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_slv.sv
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add_files -norecurse ../../src/rtl/wb_uart/hdl/wb_uart_top.sv
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add_files -norecurse ../../src/rtl/mblite/config_Pkg.vhd
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add_files -norecurse ../../src/rtl/mblite/std/std_Pkg.vhd
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add_files -norecurse ../../src/rtl/mblite/std/dsram.vhd
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add_files -norecurse ../../src/rtl/mblite/std/sram.vhd
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add_files -norecurse ../../src/rtl/mblite/std/sram_4en.vhd
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add_files -norecurse ../../src/rtl/mblite/core/core_Pkg.vhd
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add_files -norecurse ../../src/rtl/mblite/core/core.vhd
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add_files -norecurse ../../src/rtl/mblite/core/core_address_decoder.vhd
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add_files -norecurse ../../src/rtl/mblite/core/core_wb_adapter.vhd
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add_files -norecurse ../../src/rtl/mblite/core/decode.vhd
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add_files -norecurse ../../src/rtl/mblite/core/execute.vhd
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add_files -norecurse ../../src/rtl/mblite/core/fetch.vhd
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add_files -norecurse ../../src/rtl/mblite/core/gprf.vhd
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add_files -norecurse ../../src/rtl/mblite/core/mem.vhd
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add_files -norecurse ../../src/rtl/mblite/mblite_unit.vhd
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set obj [get_filesets sources_1]
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set_property "top" "mblite_top" $obj
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update_compile_order -fileset sources_1
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update_compile_order -fileset sim_1
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close_project

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