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Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [msim/] [start_sim.tcl] - Blame information for rev 7

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Line No. Rev Author Line
1 7 kuzmi4 
#
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quit -sim
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#
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quietly set SYS_PATH "~/Xilinx/Vivado/2015.4/data/verilog/src"
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# cfg-env
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quietly set FAST_SIM $::env(FAST_SIM)
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quietly set GATE_SIM $::env(GATE_SIM)
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#
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if { [file exists "work"] } { file delete -force "work" }
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vlib work
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if { [file exists "mblite"] } { file delete -force "mblite" }
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vlib mblite
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#
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if { $GATE_SIM > 0 } {
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 vlog -quiet *.v
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} else {
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 vlog -quiet -work work $SYS_PATH/glbl.v
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 vcom -quiet     -work mblite -f vcom_synth.f
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 vlog -quiet -sv -work work   -f vlog_synth.f
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}
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#
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if { $GATE_SIM > 0 } {
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 vlog -quiet -sv -work work +define+GATE_LEVEL=1 -f vlog_sim.f
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} else {
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 vlog -quiet -sv -work work -f vlog_sim.f
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}
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# sim
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if { $GATE_SIM == 1 } {
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 vsim -t ps -L secureip -L simprims_ver work.testcase work.glbl
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 log -r /*
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 do wave.do
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} elseif { $GATE_SIM == 2 } {
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 vsim -novopt +sdf_verbose -t 1ps +transport_int_delays +pulse_r/0 +pulse_int_r/0 -L simprims_ver -L secureip -L mblite work.testcase work.glbl
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 log -r /*
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 do wave.do
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} else {
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 if { $FAST_SIM == 1 } {
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  vsim -quiet  -t ps -L unisims_ver -L mblite work.testcase work.glbl
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 } else {
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  vsim -novopt -t ps -L unisims_ver -L mblite work.testcase work.glbl
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  log -r /*
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  do wave.do
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 }
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}
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quietly set StdArithNoWarnings 1
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quietly set NumericStdNoWarnings 1
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run -all

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