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[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [src/] [rtl/] [mblite/] [std/] [sram_4en.vhd] - Blame information for rev 7

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1 7 kuzmi4
----------------------------------------------------------------------------------------------
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--
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--      Input file         : sram_4en.vhd
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--      Design name        : sram_4en
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--      Author             : Tamar Kranenburg
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--      Company            : Delft University of Technology
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--                         : Faculty EEMCS, Department ME&CE
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--                         : Systems and Circuits group
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--
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--      Description          : Single Port Synchronous Random Access Memory with 4 write enable
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--                             ports.
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--
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----------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library std;
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use std.textio.all; -- string
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library mblite;
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use mblite.std_Pkg.all;
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entity sram_4en is generic
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(
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    WIDTH : positive := 32;
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    SIZE  : positive := 16
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);
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port
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(
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    dat_o : out std_logic_vector(WIDTH - 1 downto 0);
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    dat_i : in std_logic_vector(WIDTH - 1 downto 0);
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    adr_i : in std_logic_vector(SIZE - 1 downto 0);
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    wre_i : in std_logic_vector(WIDTH/8 - 1 downto 0);
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    ena_i : in std_logic;
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    clk_i : in std_logic
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);
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end sram_4en;
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architecture arch of sram_4en is
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--
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type type_name is array (0 to 3) of string(1 to 8);
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constant ram_fname : type_name := ("rom0.mem", "rom1.mem", "rom2.mem", "rom3.mem");
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--
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begin
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   mem: for i in 0 to WIDTH/8 - 1 generate
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       mem : sram
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       generic map
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       (
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           FNAME   => ram_fname(i),
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           WIDTH   => 8,
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           SIZE    => SIZE
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       )
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       port map
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       (
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           dat_o   => dat_o((i+1)*8 - 1 downto i*8),
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           dat_i   => dat_i((i+1)*8 - 1 downto i*8),
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           adr_i   => adr_i,
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           wre_i   => wre_i(i),
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           ena_i   => ena_i,
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           clk_i   => clk_i
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       );
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   end generate;
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end arch;

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