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[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [src/] [rtl/] [wb_uart/] [hdl/] [wb_uart_mscfifo.v] - Blame information for rev 7

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1 7 kuzmi4 
//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:        IK
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//
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// Create Date:
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// Design Name:
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// Module Name:     wb_uart_mscfifo
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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//                  single clock FWFT FIFO
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//
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//
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//
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// Revision:
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// Revision 0.01 - File Created,
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module wb_uart_mscfifo #(parameter p_DW = 0, p_AW = 0)
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(
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    // SYS_CON
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    input   i_clk,
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    input   i_arst,
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    // DIN
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    input               i_wr,
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    input   [p_DW-1:0]  iv_data,
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    // DOUT
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    input               i_rd,
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    output  [p_DW-1:0]  ov_data,
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    // STS-OUT
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    output  [p_AW-1:0]  ov_count,
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    output              o_full,
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    output  reg         o_empty
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);
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//////////////////////////////////////////////////////////////////////////////////
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    // LEN
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    reg     [p_AW-1:0]  sv_length;
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    wire                s_last_data;
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    // ADDR
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    reg     [p_AW-1:0]  sv_raddr;
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    reg     [p_AW-1:0]  sv_waddr;
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    wire                s_rd;
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    reg                 s_1st_wr;
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    // FWFT
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    reg                 s_fwft_flag;
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    reg     [p_DW-1:0]  sv_fwft_data;
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    // BRAM
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    wire    [p_DW-1:0]  sv_data_bram;
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//////////////////////////////////////////////////////////////////////////////////
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    // LAST-DATA flag
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    assign  s_last_data =   (sv_length == 1);
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    // inner-RD
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    assign  s_rd        =   s_1st_wr | (i_rd & ((!s_last_data & !o_empty) | i_wr));
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    //
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    // DOUT
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    assign  ov_data     =   (s_fwft_flag)? sv_fwft_data : sv_data_bram;
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    // FF
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    assign  o_full      =   (sv_length == {p_AW{1'b1}});
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    // CNT
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    assign  ov_count    =   sv_length;
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Construct FIFO-CTRL logic
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//
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always @ (posedge i_clk or posedge i_arst)
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begin   :   FIFO_CTRL_LOGIC
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    if (i_arst)
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        begin   :   RST
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            sv_length <= 0;
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            s_1st_wr <= 0;
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            sv_raddr <= 0;
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            sv_waddr <= 0;
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            s_fwft_flag <= 0;
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            sv_fwft_data <= 0;
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        end
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    else
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        begin   :   WRK
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            // FIFO-LEN
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            if (i_wr & !i_rd & !o_full)
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                sv_length <= sv_length + 1'b1;
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            else if (!i_wr & i_rd & !o_empty)
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                sv_length <= sv_length - 1'b1;
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            // 1st-wr flag (in empty fifo)
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            s_1st_wr <= i_wr & (sv_length == 0);
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            // rd-addr
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            if (s_rd)
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                sv_raddr <= sv_raddr + 1'b1;
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            // wr-addr
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            if (i_wr)
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                sv_waddr <= sv_waddr + 1'b1;
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            // fwft-flag
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            if (i_rd & !i_wr)
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                s_fwft_flag <= 0;
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            else if (i_rd & i_wr & s_last_data)
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                s_fwft_flag <= 1;
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            // fwft-data
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            if (i_rd & i_wr & s_last_data)
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                sv_fwft_data <= iv_data;
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        end
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end
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Construct EF
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//
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always @ (posedge i_clk or posedge i_arst)
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begin   :   EF_LOGIC
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    if (i_arst)
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        begin   :   RST
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            o_empty <= 1;
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        end
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    else
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        begin   :   WRK
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            if (s_1st_wr)
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                o_empty <= 0;
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            else if (i_rd & !i_wr & s_last_data)
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                o_empty <= 1;
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        end
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end
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//////////////////////////////////////////////////////////////////////////////////
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//
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// Instantiate BRAM
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//
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sdpram      #(p_DW, p_AW) // p_DW, p_AW
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            U_SDPRAM
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(
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// SYS_CON
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.i_clk      (i_clk),
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// IN / port-a
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.i_we_a     (i_wr),
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.iv_addr_a  (sv_waddr),
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.iv_data_a  (iv_data),
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// OUT / port-b
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.i_rd_b     (s_rd),
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.iv_addr_b  (sv_raddr),
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.ov_data_b  (sv_data_bram)
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);
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//////////////////////////////////////////////////////////////////////////////////
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endmodule

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