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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 12

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Line No. Rev Author Line
1 4 ale500
Changelong
2
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3 11 ale500
 
4 12 ale500
06.07.14
5
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- decoders.v : fixed missing left/dest paths for sex
7
- alu16.v : fixed sex, mul, c flag for shifts, ror
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- MC6809_cpu.v : fixed indirect indexed
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05.07.14
10
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11
- decoders.v : fixed missing left/dest paths for daa
12
- alu16.v : fixed daa, h flag store and generation
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04.07.14
15
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- decoders.v : fixed page 2&3 operands, jmp, cmp
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- MC6809_cpu.v : fixed jmp
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20 11 ale500
02.07.14
21
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- decoders.v : fixed dec, fixed inc (didn't read before write), fixed clr for ea direct, extended, indexed
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               added a path with the decoded sources/destination for the decode stage
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- MC6809_cpu.v : implemented two paths for source/dest from the decoder
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- rumsim.bat : added batch file for simulation
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27 10 ale500
22.06.14
28
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29 4 ale500
 
30 10 ale500
- decoders.v : fixed wrong left/right/dest paths for several extended, page 2, 3 opcodes.
31
- MC6809_cpu.v : fixed jsr extended, indexed
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06.02.14
34
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- regblock.v : dropped double write of PC
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- MC6809_cpu.v : fixed loading of new PC from reset vector, rel8 displacement calculation.
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39 9 ale500
06.01.14
40
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- decoders.v : added registered outputs for the source/destination address registers
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44 7 ale500
05.01.14
45
--------
46
 
47
- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC
48 9 ale500
- decoders.v : fixed destination for BIT
49
- defs.v : reduced the number of ALU opcodes
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- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB
51 7 ale500
 
52 6 ale500
01.01.14
53
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54
 
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- alu16.v : the alu has been bronken in two units
56
- MC6809_cpu.v : added CWAI states and decoding
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- decodres.v : added CWAI decoding
58
 
59 5 ale500
31.12.13
60
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61
 
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- Implemented TFR/EXG
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- MC6809_cpu.v: Added one more state to execute TFR or EXG
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- decoders.v: added source/dest for TFR and EXG
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- regblock.v : added second write path to the registers for TFR&EXG
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- defs.v defined new SEQ_TFREXG for tfr&exg execution
67
 
68 4 ale500
30.12.13
69
--------
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- Fixed increment/decrement of the stack pointer
72
 
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- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states
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                Added eamem source to the left alu data path to check for zero in the ea (leax/leay)
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29.12.13
77
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79
- Fixed wrong byte in SEQ_MEM_WRITE_H
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- Fixed unaffected Z flag for LEAX/LEAY
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- Moved increment of pc from FETCH_2 to FETCH_1
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- Fixed CMPA/CMPB/CMPX, they don't write a register back
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- Fixed late write of pc
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- decoders.v: Merged separated write_dest_x into one wire
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              Added a source_size wire to indicate the width of the source argument
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              Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY
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- MC6809_cpu.v: Dropped checks for source size from the individual states and moved
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                into SEQ_MEM_READ_H
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                Merged write flags into k_dest_write
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- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected
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95
- defs.v : added a LEA define to the ALU section

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