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ale500 |
/*
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*
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* MC6809/HD6309 Compatible code
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* (c) 2013 R.A. Paz Schmidt
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* distributed under the terms of the Lesser GPL, see LICENSE.TXT
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*
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*/
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`include "defs.v"
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module MC6809_cpu(
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input wire cpu_clk,
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input wire cpu_reset,
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input wire cpu_nmi_n,
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input wire cpu_irq_n,
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input wire cpu_firq_n,
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output wire [5:0] cpu_state_o,
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output wire cpu_we_o,
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output wire cpu_oe_o,
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output wire [15:0] cpu_addr_o,
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input wire [7:0] cpu_data_i,
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output wire [7:0] cpu_data_o
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);
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wire k_reset;
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wire k_clk;
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assign k_clk = cpu_clk;
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reg [7:0] k_opcode, k_postbyte0, k_ind_ea; /* all bytes of an instruction */
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reg [7:0] k_pp_regs, k_pp_active_reg; // push/pull mask
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reg [7:0] k_memhi, k_memlo, k_cpu_data_o; /* operand read from memory */
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reg [7:0] k_ofslo, k_ofshi, k_eahi, k_ealo;
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reg [5:0] state, // state of the main state machine
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next_state, // next state to exit to from the read from [PC] state machine
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next_mem_state, // next state to exit to from the read from memory state machine
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next_push_state; // next state to exit to from push multiple state machine
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4 |
ale500 |
reg k_cpu_oe, k_cpu_we, k_inc_pc;
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2 |
ale500 |
reg [15:0] k_cpu_addr, k_new_pc;
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reg k_write_pc, k_inc_su, k_dec_su, k_set_e, k_clear_e;
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4 |
ale500 |
reg [1:0] k_mem_dest;
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reg k_write_dest; // set for 1 clock when a register has to be written, dec_o_dest_reg_addr has the register source
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reg k_write_post_incdec; // asserted when in the last write cycle or in write back for loads
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reg k_forced_mem_size; // used to force the size of a memory read to be 16 bits, used for vector fetch
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2 |
ale500 |
/****
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* Decoder outputs
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*/
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wire [2:0] dec_o_p1_mode; // addressing mode
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wire [2:0] dec_o_p1_optype; // k_opcode type
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wire dec_o_use_s; // signals when S should be used instead of U
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wire dec_o_alu_size;
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/* ea decoder */
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wire dec_o_ea_ofs8, dec_o_ea_ofs16, dec_o_ea_wpost, dec_o_ea_ofs0, dec_o_ea_indirect;
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/* alu k_opcode decoder */
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wire [4:0] dec_o_alu_opcode;
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wire [1:0] dec_o_right_path_mod; /* Modifier for alu's right path input */
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/* register decoder */
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4 |
ale500 |
wire dec_o_wdest, dec_o_source_size, dec_o_write_flags;
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2 |
ale500 |
wire [3:0] dec_o_left_path_addr, dec_o_right_path_addr, dec_o_dest_reg_addr;
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/* test condition */
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wire dec_o_cond_taken;
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/* ALU outputs */
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wire [15:0] alu_o_result;
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wire [7:0] alu_o_CCR;
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/* Register Module outputs */
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wire [15:0] regs_o_left_path_data, regs_o_right_path_data, regs_o_eamem_addr, regs_o_su;
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wire [7:0] regs_o_dp;
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wire [15:0] regs_o_pc;
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wire [7:0] regs_o_CCR;
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/* Data Muxes */
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reg [3:0] datamux_o_dest_reg_addr, datamux_o_alu_in_left_path_addr;
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reg [15:0] datamux_o_alu_in_left_path_data, datamux_o_alu_in_right_path_data, datamux_o_dest;
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reg k_p2_valid, k_p3_valid; /* 1 when k_postbyte0 has been loaded for page 2 or page 3 */
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4 |
ale500 |
/*
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* Interrupt sync registers
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*/
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2 |
ale500 |
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reg [2:0] k_reg_nmi, k_reg_irq, k_reg_firq;
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wire k_nmi_req, k_firq_req, k_irq_req;
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assign k_nmi_req = k_reg_nmi[2] & k_reg_nmi[1];
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assign k_firq_req = k_reg_firq[2] & k_reg_firq[1];
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assign k_irq_req = k_reg_irq[2] & k_reg_irq[1];
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alu16 alu(
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.clk(k_clk),
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.a_in(datamux_o_alu_in_left_path_data),
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.b_in(datamux_o_alu_in_right_path_data),
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.CCR(regs_o_CCR), /* flags */
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.opcode_in(dec_o_alu_opcode), /* ALU k_opcode */
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.sz_in(dec_o_alu_size), /* size, low 8 bit, high 16 bit */
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.q_out(alu_o_result), /* ALU result */
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.CCRo(alu_o_CCR)
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);
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regblock regs(
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.clk_in(k_clk),
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.path_left_addr(datamux_o_alu_in_left_path_addr),
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.path_right_addr(dec_o_right_path_addr),
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.write_reg_addr(datamux_o_dest_reg_addr),
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.eapostbyte( k_ind_ea ),
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.offset16({ k_ofshi, k_ofslo }),
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4 |
ale500 |
.write_reg(k_write_dest),
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//.write_reg_16(dec_o_wdest_16 & (state == `SEQ_GRAL_WBACK)),
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//.write_pull_reg(k_pull_reg_write),
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2 |
ale500 |
.write_post(k_write_post_incdec),
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.write_pc(k_write_pc),
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.inc_pc(k_inc_pc),
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.inc_su(k_inc_su),
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.dec_su(k_dec_su),
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.use_s(dec_o_use_s),
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.data_w(datamux_o_dest),
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.new_pc(k_new_pc),
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.CCR_in(alu_o_CCR),
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.write_flags(dec_o_write_flags & (state == `SEQ_GRAL_WBACK)),
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.set_e(k_set_e),
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.clear_e(k_clear_e),
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.CCR_o(regs_o_CCR),
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.path_left_data(regs_o_left_path_data),
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.path_right_data(regs_o_right_path_data),
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.eamem_addr(regs_o_eamem_addr),
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.reg_pc(regs_o_pc),
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.reg_dp(regs_o_dp),
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.reg_su(regs_o_su)
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);
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decode_regs dec_regs(
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.opcode(k_opcode),
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.postbyte0(k_postbyte0),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.path_left_addr(dec_o_left_path_addr),
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.path_right_addr(dec_o_right_path_addr),
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.dest_reg(dec_o_dest_reg_addr),
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4 |
ale500 |
.write_dest(dec_o_wdest),
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.source_size(dec_o_source_size),
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2 |
ale500 |
.result_size(dec_o_alu_size)
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);
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decode_op dec_op(
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.opcode(k_opcode),
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.postbyte0(k_postbyte0),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.mode(dec_o_p1_mode),
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.optype(dec_o_p1_optype),
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.use_s(dec_o_use_s)
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);
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decode_ea dec_ea(
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.eapostbyte( k_ind_ea ),
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.noofs(dec_o_ea_ofs0),
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.ofs8(dec_o_ea_ofs8),
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.ofs16(dec_o_ea_ofs16),
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.write_post(dec_o_ea_wpost),
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.isind(dec_o_ea_indirect)
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);
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/* Opcodes for the ALU are decoded here
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* Write Flags are also decoded here
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*/
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decode_alu dec_alu(
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.opcode(k_opcode),
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.postbyte0(k_postbyte0),
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.page2_valid(k_p2_valid),
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.page3_valid(k_p3_valid),
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.alu_opcode(dec_o_alu_opcode),
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.dec_alu_right_path_mod(dec_o_right_path_mod),
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.dest_flags(dec_o_write_flags)
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);
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/* Condition decoder */
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test_condition test_cond(
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.opcode(k_opcode),
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.postbyte0(k_postbyte0),
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.page2_valid(k_p2_valid),
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.CCR(regs_o_CCR),
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.cond_taken(dec_o_cond_taken)
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);
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/* Module IO */
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assign cpu_oe_o = k_cpu_oe; // we latch on the rising edge
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assign cpu_we_o = k_cpu_we;
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assign cpu_addr_o = k_cpu_addr;
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assign cpu_data_o = k_cpu_data_o;
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assign k_reset = cpu_reset;
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assign cpu_state_o = state;
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/* Left Register read mux
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*/
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always @(*)
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begin
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datamux_o_alu_in_left_path_addr = dec_o_left_path_addr;
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case (k_pp_active_reg)
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8'h80: datamux_o_alu_in_left_path_addr = `RN_PC;
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8'h40: datamux_o_alu_in_left_path_addr = (dec_o_use_s) ? `RN_U:`RN_S;
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8'h20: datamux_o_alu_in_left_path_addr = `RN_IY;
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8'h10: datamux_o_alu_in_left_path_addr = `RN_IX;
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8'h08: datamux_o_alu_in_left_path_addr = `RN_DP;
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8'h04: datamux_o_alu_in_left_path_addr = `RN_ACCB;
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8'h02: datamux_o_alu_in_left_path_addr = `RN_ACCA;
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8'h01: datamux_o_alu_in_left_path_addr = `RN_CC;
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endcase
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end
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/* Destination register address MUX
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*/
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always @(*)
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begin
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datamux_o_dest_reg_addr = dec_o_dest_reg_addr;
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case (k_pp_active_reg)
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8'h80: datamux_o_dest_reg_addr = `RN_PC;
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8'h40: datamux_o_dest_reg_addr = (dec_o_use_s) ? `RN_U:`RN_S;
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8'h20: datamux_o_dest_reg_addr = `RN_IY;
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8'h10: datamux_o_dest_reg_addr = `RN_IX;
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8'h08: datamux_o_dest_reg_addr = `RN_DP;
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8'h04: datamux_o_dest_reg_addr = `RN_ACCB;
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8'h02: datamux_o_dest_reg_addr = `RN_ACCA;
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8'h01: datamux_o_dest_reg_addr = `RN_CC;
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endcase
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end
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/* Destination register data mux
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* selects the source to write to register. 16 bit registers have to be written at once after reading the low byte
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*
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*/
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always @(*)
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begin
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datamux_o_dest = alu_o_result;
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case (dec_o_p1_optype)
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`OP_PULL, `OP_RTS: // destination register
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datamux_o_dest = { k_memhi, k_memlo };
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`OP_LEA:
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4 |
ale500 |
if (dec_o_ea_indirect)// & dec_o_alu_size)
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2 |
ale500 |
datamux_o_dest = { k_memhi, k_memlo };
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else
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datamux_o_dest = regs_o_eamem_addr;
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endcase
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end
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| 242 |
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/* ALU left input mux */
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always @(*)
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begin
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if (dec_o_left_path_addr == `RN_MEM8)
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datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
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else
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4 |
ale500 |
case (dec_o_p1_optype)
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`OP_LEA:
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if (dec_o_ea_indirect)// & dec_o_alu_size)
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datamux_o_alu_in_left_path_data = { k_memhi, k_memlo };
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| 253 |
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else
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datamux_o_alu_in_left_path_data = regs_o_eamem_addr;
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| 255 |
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default:
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| 256 |
2 |
ale500 |
datamux_o_alu_in_left_path_data = regs_o_left_path_data;
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| 257 |
4 |
ale500 |
endcase
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| 258 |
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end
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| 259 |
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/* PC as destination from jmp/bsr mux */
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| 260 |
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always @(*)
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begin
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| 262 |
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k_new_pc = { k_memhi,k_memlo }; // used to fetch reset vector
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| 263 |
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case (dec_o_p1_mode)
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`REL16: k_new_pc = regs_o_pc + { k_memhi,k_memlo };
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| 265 |
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`REL8: k_new_pc = regs_o_pc + { {8{k_memlo[7]}}, k_memlo };
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| 266 |
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`EXTENDED: k_new_pc = { k_eahi,k_ealo };
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| 267 |
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`DIRECT: k_new_pc = { regs_o_dp, k_ealo };
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`INDEXED:
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if (dec_o_ea_indirect)
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| 270 |
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k_new_pc = { k_memhi,k_memlo };
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else
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k_new_pc = regs_o_eamem_addr;
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endcase
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2 |
ale500 |
end
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| 276 |
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/* ALU right input mux */
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| 277 |
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always @(*)
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| 278 |
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begin
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| 279 |
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case (dec_o_right_path_addr)
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| 280 |
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`RN_MEM8:
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| 281 |
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datamux_o_alu_in_right_path_data = { 8'h00, k_memlo };
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| 282 |
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`RN_MEM16:
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datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
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| 284 |
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`RN_IMM8:
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| 285 |
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datamux_o_alu_in_right_path_data = { 8'h0, k_memlo };
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| 286 |
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`RN_IMM16:
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| 287 |
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datamux_o_alu_in_right_path_data = { k_memhi, k_memlo };
|
| 288 |
|
|
default:
|
| 289 |
|
|
case (dec_o_right_path_mod)
|
| 290 |
|
|
`MOD_DEFAULT: datamux_o_alu_in_right_path_data = regs_o_right_path_data;
|
| 291 |
|
|
`MOD_ONE: datamux_o_alu_in_right_path_data = 16'h0001;
|
| 292 |
|
|
`MOD_ZERO: datamux_o_alu_in_right_path_data = 16'h0000;
|
| 293 |
|
|
`MOD_MINUS1: datamux_o_alu_in_right_path_data = 16'hffff;
|
| 294 |
|
|
endcase
|
| 295 |
|
|
endcase
|
| 296 |
|
|
end
|
| 297 |
|
|
|
| 298 |
|
|
always @(posedge k_clk or posedge k_reset)
|
| 299 |
|
|
begin
|
| 300 |
|
|
if (k_reset == 1'b1)
|
| 301 |
|
|
begin
|
| 302 |
|
|
state <= `SEQ_COLDRESET;
|
| 303 |
|
|
k_reg_nmi <= 0;
|
| 304 |
|
|
k_reg_firq <= 0;
|
| 305 |
|
|
k_reg_irq <= 0;
|
| 306 |
|
|
end
|
| 307 |
|
|
else
|
| 308 |
|
|
begin
|
| 309 |
|
|
/* Inrerrupt recognition and acknowledge */
|
| 310 |
|
|
if (!k_reg_nmi[2])
|
| 311 |
|
|
k_reg_nmi <= { k_reg_nmi[1:0], cpu_nmi_n };
|
| 312 |
|
|
if (!k_reg_irq[2])
|
| 313 |
|
|
k_reg_irq <= { k_reg_irq[1:0], cpu_irq_n };
|
| 314 |
|
|
if (!k_reg_firq[2])
|
| 315 |
|
|
k_reg_firq <= { k_reg_firq[1:0], cpu_firq_n };
|
| 316 |
|
|
/* modifier registers */
|
| 317 |
|
|
if (k_inc_pc)
|
| 318 |
|
|
k_inc_pc <= 0;
|
| 319 |
|
|
if (k_write_pc)
|
| 320 |
|
|
k_write_pc <= 0;
|
| 321 |
|
|
if (k_cpu_we)
|
| 322 |
|
|
k_cpu_we <= 0;
|
| 323 |
|
|
if (k_cpu_oe)
|
| 324 |
|
|
k_cpu_oe <= 0;
|
| 325 |
|
|
if (k_write_post_incdec)
|
| 326 |
|
|
k_write_post_incdec <= 0;
|
| 327 |
|
|
if (k_dec_su)
|
| 328 |
|
|
k_dec_su <= 0;
|
| 329 |
|
|
if (k_inc_su)
|
| 330 |
|
|
k_inc_su <= 0;
|
| 331 |
4 |
ale500 |
//if (k_pull_reg_write)
|
| 332 |
|
|
// k_pull_reg_write <= 0;
|
| 333 |
2 |
ale500 |
if (k_set_e)
|
| 334 |
|
|
k_set_e <= 0;
|
| 335 |
|
|
if (k_clear_e)
|
| 336 |
4 |
ale500 |
k_clear_e <= 0;
|
| 337 |
|
|
if (k_write_dest)
|
| 338 |
|
|
k_write_dest <= 0;
|
| 339 |
2 |
ale500 |
case (state)
|
| 340 |
|
|
`SEQ_COLDRESET:
|
| 341 |
4 |
ale500 |
begin
|
| 342 |
|
|
k_forced_mem_size <= 1;
|
| 343 |
2 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 344 |
|
|
k_eahi <= 8'hff;
|
| 345 |
|
|
k_ealo <= 8'hfe;
|
| 346 |
|
|
next_mem_state <= `SEQ_LOADPC;
|
| 347 |
|
|
end
|
| 348 |
|
|
`SEQ_NMI:
|
| 349 |
|
|
begin
|
| 350 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 351 |
2 |
ale500 |
k_reg_nmi <= 2'h0;
|
| 352 |
|
|
{ k_eahi, k_ealo } <= 16'hfffc;
|
| 353 |
|
|
k_pp_regs <= 8'hff;
|
| 354 |
|
|
k_set_e <= 1;
|
| 355 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 356 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 357 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 358 |
|
|
end
|
| 359 |
|
|
`SEQ_SWI:
|
| 360 |
|
|
begin
|
| 361 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 362 |
2 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 363 |
|
|
{ k_eahi, k_ealo } <= 16'hfffa;
|
| 364 |
|
|
k_pp_regs <= 8'hff;
|
| 365 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 366 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 367 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 368 |
|
|
k_set_e <= 1;
|
| 369 |
|
|
end
|
| 370 |
|
|
`SEQ_IRQ:
|
| 371 |
|
|
begin
|
| 372 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 373 |
2 |
ale500 |
k_reg_irq <= 2'h0;
|
| 374 |
|
|
state <= `SEQ_MEM_READ_H;
|
| 375 |
|
|
{ k_eahi, k_ealo } <= 16'hfff8;
|
| 376 |
|
|
k_pp_regs <= 8'hff;
|
| 377 |
|
|
next_mem_state <= `SEQ_PREPUSH;
|
| 378 |
|
|
k_set_e <= 1;
|
| 379 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 380 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 381 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 382 |
|
|
end
|
| 383 |
|
|
`SEQ_FIRQ:
|
| 384 |
|
|
begin
|
| 385 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 386 |
2 |
ale500 |
k_reg_firq <= 2'h0;
|
| 387 |
|
|
{ k_eahi, k_ealo } <= 16'hfff6;
|
| 388 |
|
|
k_pp_regs <= 8'h81; // PC & CC
|
| 389 |
|
|
k_clear_e <= 1;
|
| 390 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 391 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 392 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 393 |
|
|
end
|
| 394 |
|
|
`SEQ_SWI2:
|
| 395 |
|
|
begin
|
| 396 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 397 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff4;
|
| 398 |
|
|
k_pp_regs <= 8'hff;
|
| 399 |
|
|
k_set_e <= 1;
|
| 400 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 401 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 402 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 403 |
|
|
end
|
| 404 |
|
|
`SEQ_SWI3:
|
| 405 |
|
|
begin
|
| 406 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 407 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff2;
|
| 408 |
|
|
k_pp_regs <= 8'hff;
|
| 409 |
|
|
k_set_e <= 1;
|
| 410 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 411 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 412 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 413 |
|
|
end
|
| 414 |
|
|
`SEQ_UNDEF:
|
| 415 |
|
|
begin
|
| 416 |
4 |
ale500 |
k_forced_mem_size <= 1;
|
| 417 |
2 |
ale500 |
{ k_eahi, k_ealo } <= 16'hfff0;
|
| 418 |
|
|
k_pp_regs <= 8'hff;
|
| 419 |
|
|
k_set_e <= 1;
|
| 420 |
|
|
state <= `SEQ_PREPUSH; // first stack the registers
|
| 421 |
|
|
next_push_state <= `SEQ_MEM_READ_H; // than load new PC
|
| 422 |
|
|
next_mem_state <= `SEQ_FETCH; // than continue fetching instructions
|
| 423 |
|
|
end
|
| 424 |
|
|
`SEQ_LOADPC: /* loads the PC with the address taken from the reset vector */
|
| 425 |
|
|
begin
|
| 426 |
|
|
$display("cpu_data_i %02x %t", cpu_data_i, $time);
|
| 427 |
|
|
state <= `SEQ_FETCH;
|
| 428 |
|
|
end
|
| 429 |
|
|
`SEQ_FETCH: /* execution starts here */
|
| 430 |
|
|
begin
|
| 431 |
|
|
if (k_nmi_req)
|
| 432 |
|
|
state <= `SEQ_NMI;
|
| 433 |
|
|
else
|
| 434 |
|
|
if (k_firq_req)
|
| 435 |
|
|
state <= `SEQ_FIRQ;
|
| 436 |
|
|
else
|
| 437 |
|
|
if (k_irq_req)
|
| 438 |
|
|
state <= `SEQ_IRQ;
|
| 439 |
|
|
else
|
| 440 |
|
|
begin
|
| 441 |
|
|
state <= `SEQ_FETCH_1;
|
| 442 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 443 |
|
|
end
|
| 444 |
|
|
end
|
| 445 |
|
|
`SEQ_FETCH_1:
|
| 446 |
|
|
begin
|
| 447 |
|
|
k_cpu_oe <= 1;
|
| 448 |
4 |
ale500 |
state <= `SEQ_FETCH_2;
|
| 449 |
|
|
k_inc_pc <= 1;
|
| 450 |
2 |
ale500 |
end
|
| 451 |
|
|
`SEQ_FETCH_2:
|
| 452 |
|
|
begin
|
| 453 |
|
|
k_opcode <= cpu_data_i;
|
| 454 |
|
|
case (cpu_data_i[7:0]) /* page 2 & 3 opcodes are recognized here */
|
| 455 |
|
|
8'h10:
|
| 456 |
|
|
begin
|
| 457 |
|
|
k_p2_valid <= 1;
|
| 458 |
|
|
k_p3_valid <= 0;
|
| 459 |
|
|
state <= `SEQ_FETCH_3;
|
| 460 |
|
|
end
|
| 461 |
|
|
8'h11:
|
| 462 |
|
|
begin
|
| 463 |
|
|
k_p2_valid <= 0;
|
| 464 |
|
|
k_p3_valid <= 1;
|
| 465 |
|
|
state <= `SEQ_FETCH_3;
|
| 466 |
|
|
end
|
| 467 |
|
|
default:
|
| 468 |
|
|
begin
|
| 469 |
|
|
state <= `SEQ_DECODE;
|
| 470 |
|
|
k_p2_valid <= 0; // set when an k_opcode is page 2
|
| 471 |
|
|
k_p3_valid <= 0; // set when an k_opcode is page 3
|
| 472 |
|
|
end
|
| 473 |
|
|
endcase
|
| 474 |
|
|
k_pp_active_reg <= 8'h00; // prevents wrong register in left/dest data muxes
|
| 475 |
|
|
end
|
| 476 |
|
|
`SEQ_FETCH_3:
|
| 477 |
|
|
begin
|
| 478 |
|
|
state <= `SEQ_FETCH_4;
|
| 479 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 480 |
|
|
end
|
| 481 |
|
|
`SEQ_FETCH_4:
|
| 482 |
|
|
begin
|
| 483 |
|
|
k_cpu_oe <= 1;
|
| 484 |
|
|
state <= `SEQ_FETCH_5;
|
| 485 |
|
|
end
|
| 486 |
|
|
`SEQ_FETCH_5: /* fetches a page 2 or 3 opcode */
|
| 487 |
|
|
begin
|
| 488 |
|
|
k_postbyte0 <= cpu_data_i;
|
| 489 |
|
|
k_inc_pc <= 1;
|
| 490 |
|
|
state <= `SEQ_DECODE_P23;
|
| 491 |
|
|
end
|
| 492 |
|
|
`SEQ_DECODE:
|
| 493 |
|
|
begin
|
| 494 |
|
|
/* here we have the first byte of the k_opcode and should be decided to which state we jump
|
| 495 |
|
|
* inherent means that no extra info is needed
|
| 496 |
|
|
* ALU opcodes need routing of registers to/from the ALU to the registers
|
| 497 |
|
|
*/
|
| 498 |
|
|
case (dec_o_p1_mode)
|
| 499 |
4 |
ale500 |
`NONE: // unknown k_opcode or push/pull... refetch ?
|
| 500 |
2 |
ale500 |
begin
|
| 501 |
|
|
casex (k_opcode)
|
| 502 |
|
|
8'h39: // RTS
|
| 503 |
4 |
ale500 |
begin
|
| 504 |
2 |
ale500 |
state <= `SEQ_PREPULL;
|
| 505 |
|
|
k_pp_regs <= 8'h80; // Pull PC (RTS)all regs
|
| 506 |
|
|
end
|
| 507 |
|
|
8'h3B: // RTI
|
| 508 |
4 |
ale500 |
begin
|
| 509 |
2 |
ale500 |
state <= `SEQ_PREPULL;
|
| 510 |
|
|
k_pp_regs <= 8'hff; // all regs
|
| 511 |
|
|
end
|
| 512 |
|
|
8'b001101x0: // PUSH S&U
|
| 513 |
|
|
begin
|
| 514 |
|
|
state <= `SEQ_PC_READ_L;
|
| 515 |
|
|
next_state <= `SEQ_PREPUSH;
|
| 516 |
|
|
next_push_state <= `SEQ_FETCH;
|
| 517 |
|
|
end
|
| 518 |
|
|
8'b001101x1: // PULL S&U
|
| 519 |
|
|
begin
|
| 520 |
|
|
next_state <= `SEQ_PREPULL;
|
| 521 |
|
|
state <= `SEQ_PC_READ_L;
|
| 522 |
|
|
end
|
| 523 |
|
|
default: /* we ignore unknown opcodes */
|
| 524 |
|
|
state <= `SEQ_FETCH;
|
| 525 |
|
|
endcase
|
| 526 |
|
|
end
|
| 527 |
|
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
| 528 |
|
|
begin
|
| 529 |
|
|
if (dec_o_alu_size)
|
| 530 |
|
|
state <= `SEQ_PC_READ_H;
|
| 531 |
|
|
else
|
| 532 |
|
|
state <= `SEQ_PC_READ_L;
|
| 533 |
|
|
next_state <= `SEQ_GRAL_ALU;
|
| 534 |
|
|
end
|
| 535 |
|
|
`INHERENT:
|
| 536 |
|
|
begin
|
| 537 |
|
|
case (k_opcode)
|
| 538 |
|
|
8'h3f: state <= `SEQ_SWI;
|
| 539 |
|
|
default: state <= `SEQ_GRAL_ALU;
|
| 540 |
|
|
endcase
|
| 541 |
|
|
end
|
| 542 |
|
|
`DIRECT:
|
| 543 |
|
|
begin
|
| 544 |
|
|
state <= `SEQ_PC_READ_L;
|
| 545 |
|
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
| 546 |
|
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| 547 |
|
|
(dec_o_left_path_addr == `RN_MEM8))
|
| 548 |
|
|
begin
|
| 549 |
4 |
ale500 |
next_state <= `SEQ_MEM_READ_H;
|
| 550 |
2 |
ale500 |
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
| 551 |
|
|
end
|
| 552 |
|
|
else
|
| 553 |
|
|
next_state <= `SEQ_GRAL_ALU; // no read
|
| 554 |
|
|
k_eahi <= regs_o_dp;
|
| 555 |
|
|
end
|
| 556 |
|
|
`INDEXED:
|
| 557 |
|
|
state <= `SEQ_IND_READ_EA;
|
| 558 |
|
|
`EXTENDED:
|
| 559 |
|
|
begin
|
| 560 |
|
|
state <= `SEQ_PC_READ_H; // loads address
|
| 561 |
|
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
| 562 |
|
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| 563 |
|
|
(dec_o_left_path_addr == `RN_MEM8))
|
| 564 |
|
|
begin
|
| 565 |
4 |
ale500 |
next_state <= `SEQ_MEM_READ_H;
|
| 566 |
2 |
ale500 |
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
| 567 |
|
|
end
|
| 568 |
|
|
else
|
| 569 |
|
|
next_state <= `SEQ_GRAL_ALU; // no read
|
| 570 |
|
|
end
|
| 571 |
|
|
`REL8:
|
| 572 |
|
|
begin
|
| 573 |
|
|
state <= `SEQ_PC_READ_L; // loads address
|
| 574 |
|
|
if (dec_o_p1_optype == `OP_JSR) // bsr
|
| 575 |
|
|
next_state <= `SEQ_JSR_PUSH;
|
| 576 |
|
|
else
|
| 577 |
|
|
next_state <= `SEQ_JMP_LOAD_PC; // offset loaded in this cycle, jump if needed
|
| 578 |
|
|
end
|
| 579 |
|
|
`REL16:
|
| 580 |
|
|
begin
|
| 581 |
|
|
state <= `SEQ_PC_READ_H; // loads address
|
| 582 |
|
|
if (dec_o_p1_optype == `OP_JSR) // lbsr
|
| 583 |
|
|
next_state <= `SEQ_JSR_PUSH;
|
| 584 |
|
|
else
|
| 585 |
|
|
next_state <= `SEQ_JMP_LOAD_PC;
|
| 586 |
|
|
end
|
| 587 |
|
|
endcase
|
| 588 |
|
|
end
|
| 589 |
|
|
`SEQ_DECODE_P23:
|
| 590 |
|
|
begin // has prefix 10 or 11
|
| 591 |
|
|
k_inc_pc <= 0;
|
| 592 |
|
|
case (dec_o_p1_mode)
|
| 593 |
|
|
`NONE: // unknown k_opcode... re-fetch ?
|
| 594 |
|
|
state <= `SEQ_FETCH;
|
| 595 |
|
|
`IMMEDIATE: // 8 or 16 bits as result decides..
|
| 596 |
|
|
begin
|
| 597 |
|
|
if (dec_o_alu_size)
|
| 598 |
|
|
state <= `SEQ_PC_READ_H;
|
| 599 |
|
|
else
|
| 600 |
|
|
state <= `SEQ_PC_READ_L;
|
| 601 |
|
|
next_state <= `SEQ_GRAL_ALU;
|
| 602 |
|
|
end
|
| 603 |
|
|
`INHERENT:
|
| 604 |
|
|
case (k_opcode)
|
| 605 |
|
|
8'h3f: if (k_p2_valid) state <= `SEQ_SWI2;
|
| 606 |
|
|
else state <= `SEQ_SWI3;
|
| 607 |
|
|
default: state <= `SEQ_GRAL_ALU;
|
| 608 |
|
|
endcase
|
| 609 |
|
|
`DIRECT:
|
| 610 |
|
|
begin
|
| 611 |
|
|
state <= `SEQ_PC_READ_L;
|
| 612 |
|
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
| 613 |
|
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| 614 |
|
|
(dec_o_left_path_addr == `RN_MEM8))
|
| 615 |
|
|
begin
|
| 616 |
4 |
ale500 |
next_state <= `SEQ_MEM_READ_H;
|
| 617 |
2 |
ale500 |
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
| 618 |
|
|
end
|
| 619 |
|
|
else
|
| 620 |
|
|
next_state <= `SEQ_GRAL_ALU; // no read
|
| 621 |
|
|
k_eahi <= regs_o_dp;
|
| 622 |
|
|
end
|
| 623 |
|
|
`INDEXED:
|
| 624 |
|
|
state <= `SEQ_IND_READ_EA;
|
| 625 |
|
|
`EXTENDED:
|
| 626 |
|
|
begin
|
| 627 |
|
|
state <= `SEQ_PC_READ_H; // loads address
|
| 628 |
|
|
k_mem_dest <= `MEMDEST_MH; // operand to memlo/memhi
|
| 629 |
|
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| 630 |
|
|
(dec_o_left_path_addr == `RN_MEM8))
|
| 631 |
|
|
begin
|
| 632 |
4 |
ale500 |
next_state <= `SEQ_MEM_READ_H;
|
| 633 |
2 |
ale500 |
next_mem_state <= `SEQ_GRAL_ALU; // read then alu
|
| 634 |
|
|
end
|
| 635 |
|
|
else
|
| 636 |
|
|
next_state <= `SEQ_GRAL_ALU; // no read
|
| 637 |
|
|
end
|
| 638 |
|
|
`REL16:
|
| 639 |
|
|
begin // long branches only
|
| 640 |
|
|
state <= `SEQ_PC_READ_H; // loads address
|
| 641 |
|
|
next_state <= `SEQ_JMP_LOAD_PC;
|
| 642 |
|
|
end
|
| 643 |
|
|
endcase
|
| 644 |
|
|
end
|
| 645 |
4 |
ale500 |
`SEQ_GRAL_ALU:
|
| 646 |
|
|
begin
|
| 647 |
|
|
state <= `SEQ_GRAL_WBACK;
|
| 648 |
|
|
k_write_dest <= 1; /* write destination on wback */
|
| 649 |
|
|
end
|
| 650 |
2 |
ale500 |
`SEQ_GRAL_WBACK:
|
| 651 |
|
|
begin
|
| 652 |
4 |
ale500 |
next_mem_state <= `SEQ_FETCH;
|
| 653 |
2 |
ale500 |
case (dec_o_dest_reg_addr)
|
| 654 |
|
|
`RN_MEM8: state <= `SEQ_MEM_WRITE_L;
|
| 655 |
|
|
`RN_MEM16: state <= `SEQ_MEM_WRITE_H;
|
| 656 |
|
|
default:
|
| 657 |
|
|
begin
|
| 658 |
|
|
state <= `SEQ_FETCH;
|
| 659 |
|
|
k_write_post_incdec <= dec_o_ea_wpost;
|
| 660 |
|
|
end
|
| 661 |
|
|
endcase
|
| 662 |
|
|
end
|
| 663 |
|
|
`SEQ_INH_ALU:
|
| 664 |
|
|
state <= `SEQ_GRAL_WBACK;
|
| 665 |
|
|
`SEQ_IND_READ_EA: // reads EA byte
|
| 666 |
|
|
begin
|
| 667 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 668 |
|
|
state <= `SEQ_IND_READ_EA_1;
|
| 669 |
|
|
k_inc_pc <= 1;
|
| 670 |
|
|
end
|
| 671 |
|
|
`SEQ_IND_READ_EA_1:
|
| 672 |
|
|
begin
|
| 673 |
|
|
k_cpu_oe <= 1; // read
|
| 674 |
|
|
state <= `SEQ_IND_READ_EA_2;
|
| 675 |
|
|
end
|
| 676 |
|
|
`SEQ_IND_READ_EA_2:
|
| 677 |
|
|
begin
|
| 678 |
|
|
k_ind_ea <= cpu_data_i;
|
| 679 |
|
|
state <= `SEQ_IND_DECODE;
|
| 680 |
|
|
end
|
| 681 |
|
|
`SEQ_IND_DECODE: // here we have to see what we need for indexed...
|
| 682 |
|
|
begin
|
| 683 |
|
|
if (dec_o_ea_ofs8)
|
| 684 |
|
|
begin // load 1 byte offset
|
| 685 |
|
|
state <= `SEQ_PC_READ_L;
|
| 686 |
|
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
| 687 |
|
|
end
|
| 688 |
|
|
else
|
| 689 |
|
|
if (dec_o_ea_ofs16)
|
| 690 |
|
|
begin // load 2 bytes offset
|
| 691 |
|
|
state <= `SEQ_PC_READ_H;
|
| 692 |
|
|
next_state <= `SEQ_IND_DECODE_OFS; // has some offset, load arg
|
| 693 |
|
|
end
|
| 694 |
|
|
else
|
| 695 |
|
|
//if (dec_o_ea_ofs0)
|
| 696 |
|
|
begin // no extra load...
|
| 697 |
|
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| 698 |
|
|
(dec_o_left_path_addr == `RN_MEM8))
|
| 699 |
|
|
begin
|
| 700 |
|
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
| 701 |
|
|
next_mem_state <= `SEQ_GRAL_ALU;
|
| 702 |
4 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 703 |
2 |
ale500 |
end
|
| 704 |
|
|
else
|
| 705 |
|
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
| 706 |
|
|
end
|
| 707 |
|
|
end
|
| 708 |
|
|
`SEQ_IND_DECODE_OFS: // loads argument if needed
|
| 709 |
|
|
begin
|
| 710 |
|
|
if ((dec_o_right_path_addr == `RN_MEM8) || (dec_o_right_path_addr == `RN_MEM16) ||
|
| 711 |
|
|
(dec_o_left_path_addr == `RN_MEM8))
|
| 712 |
|
|
begin
|
| 713 |
|
|
k_mem_dest <= `MEMDEST_MH; // operand land in k_memhi/lo
|
| 714 |
|
|
next_mem_state <= `SEQ_GRAL_ALU;
|
| 715 |
4 |
ale500 |
state <= `SEQ_MEM_READ_H;
|
| 716 |
2 |
ale500 |
end
|
| 717 |
|
|
else
|
| 718 |
|
|
state <= `SEQ_GRAL_ALU; // no load, then store
|
| 719 |
|
|
end
|
| 720 |
|
|
`SEQ_JMP_LOAD_PC:
|
| 721 |
|
|
begin
|
| 722 |
|
|
state <= `SEQ_FETCH;
|
| 723 |
|
|
end
|
| 724 |
|
|
`SEQ_JSR_PUSH:
|
| 725 |
|
|
begin
|
| 726 |
|
|
k_pp_active_reg <= 8'h80; // push PC
|
| 727 |
|
|
state <= `SEQ_PUSH_WRITE_L;
|
| 728 |
|
|
next_state <= `SEQ_JMP_LOAD_PC;
|
| 729 |
|
|
end
|
| 730 |
|
|
`SEQ_PREPUSH:
|
| 731 |
|
|
begin
|
| 732 |
|
|
next_state <= `SEQ_PREPUSH;
|
| 733 |
4 |
ale500 |
if (k_pp_regs > 0)
|
| 734 |
|
|
begin
|
| 735 |
|
|
state <= `SEQ_PUSH_WRITE_L;
|
| 736 |
|
|
//k_dec_su <= 1;
|
| 737 |
|
|
end
|
| 738 |
2 |
ale500 |
else
|
| 739 |
|
|
state <= next_push_state;
|
| 740 |
|
|
if (k_pp_regs[7]) begin k_pp_regs[7] <= 0; k_pp_active_reg <= 8'h80; end
|
| 741 |
|
|
else
|
| 742 |
|
|
if (k_pp_regs[6]) begin k_pp_regs[6] <= 0; k_pp_active_reg <= 8'h40; end
|
| 743 |
|
|
else
|
| 744 |
|
|
if (k_pp_regs[5]) begin k_pp_regs[5] <= 0; k_pp_active_reg <= 8'h20; end
|
| 745 |
|
|
else
|
| 746 |
|
|
if (k_pp_regs[4]) begin k_pp_regs[4] <= 0; k_pp_active_reg <= 8'h10; end
|
| 747 |
|
|
else
|
| 748 |
|
|
if (k_pp_regs[3]) begin k_pp_regs[3] <= 0; k_pp_active_reg <= 8'h08; end
|
| 749 |
|
|
else
|
| 750 |
|
|
if (k_pp_regs[2]) begin k_pp_regs[2] <= 0; k_pp_active_reg <= 8'h04; end
|
| 751 |
|
|
else
|
| 752 |
|
|
if (k_pp_regs[1]) begin k_pp_regs[1] <= 0; k_pp_active_reg <= 8'h02; end
|
| 753 |
|
|
else
|
| 754 |
|
|
if (k_pp_regs[0]) begin k_pp_regs[0] <= 0; k_pp_active_reg <= 8'h01; end
|
| 755 |
|
|
end
|
| 756 |
|
|
`SEQ_PREPULL:
|
| 757 |
4 |
ale500 |
begin
|
| 758 |
|
|
if (k_pp_regs != 8'h0)
|
| 759 |
|
|
begin
|
| 760 |
|
|
k_mem_dest <= `MEMDEST_MH;
|
| 761 |
|
|
next_mem_state <= `SEQ_PREPULL;
|
| 762 |
|
|
end
|
| 763 |
|
|
else
|
| 764 |
|
|
state <= `SEQ_FETCH; // end of sequence
|
| 765 |
2 |
ale500 |
if (k_pp_regs[0]) begin k_pp_active_reg <= 8'h01; k_pp_regs[0] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 766 |
|
|
else
|
| 767 |
|
|
if (k_pp_regs[1]) begin k_pp_active_reg <= 8'h02; k_pp_regs[1] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 768 |
|
|
else
|
| 769 |
|
|
if (k_pp_regs[2]) begin k_pp_active_reg <= 8'h04; k_pp_regs[2] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 770 |
|
|
else
|
| 771 |
|
|
if (k_pp_regs[3]) begin k_pp_active_reg <= 8'h08; k_pp_regs[3] <= 0; state <= `SEQ_MEM_READ_L; end
|
| 772 |
|
|
else
|
| 773 |
|
|
if (k_pp_regs[4]) begin k_pp_active_reg <= 8'h10; k_pp_regs[4] <= 0; state <= `SEQ_MEM_READ_H;end
|
| 774 |
|
|
else
|
| 775 |
|
|
if (k_pp_regs[5]) begin k_pp_active_reg <= 8'h20; k_pp_regs[5] <= 0; state <= `SEQ_MEM_READ_H;end
|
| 776 |
|
|
else
|
| 777 |
|
|
if (k_pp_regs[6]) begin k_pp_active_reg <= 8'h40; k_pp_regs[6] <= 0; state <= `SEQ_MEM_READ_H; end
|
| 778 |
|
|
else
|
| 779 |
4 |
ale500 |
if (k_pp_regs[7]) begin k_pp_active_reg <= 8'h80; k_pp_regs[7] <= 0; state <= `SEQ_MEM_READ_H; end
|
| 780 |
2 |
ale500 |
end
|
| 781 |
|
|
`SEQ_PUSH_WRITE_L: // first low byte push
|
| 782 |
|
|
begin
|
| 783 |
|
|
k_cpu_data_o <= regs_o_left_path_data[7:0];
|
| 784 |
|
|
state <= `SEQ_PUSH_WRITE_L_1;
|
| 785 |
|
|
k_cpu_we <= 1; // write
|
| 786 |
4 |
ale500 |
k_cpu_addr <= regs_o_su - 16'h1;
|
| 787 |
|
|
k_dec_su <= 1;
|
| 788 |
2 |
ale500 |
end
|
| 789 |
|
|
`SEQ_PUSH_WRITE_L_1:
|
| 790 |
|
|
begin
|
| 791 |
|
|
if (k_pp_active_reg[7:4] > 0)
|
| 792 |
|
|
state <= `SEQ_PUSH_WRITE_H;
|
| 793 |
|
|
else
|
| 794 |
|
|
if (k_pp_regs[3:0] > 0)
|
| 795 |
|
|
state <= `SEQ_PREPUSH;
|
| 796 |
|
|
else
|
| 797 |
4 |
ale500 |
state <= next_push_state;
|
| 798 |
|
|
k_cpu_addr <= k_cpu_addr - 16'h1; // when pushing 16 bits the second decrement comes too late
|
| 799 |
2 |
ale500 |
end
|
| 800 |
|
|
`SEQ_PUSH_WRITE_H: // reads high byte
|
| 801 |
|
|
begin
|
| 802 |
|
|
k_cpu_data_o <= regs_o_left_path_data[15:8];
|
| 803 |
|
|
state <= `SEQ_PUSH_WRITE_H_1;
|
| 804 |
4 |
ale500 |
k_cpu_we <= 1; // write
|
| 805 |
|
|
if (k_pp_active_reg[3:0] > 0)
|
| 806 |
|
|
k_cpu_addr <= regs_o_su;
|
| 807 |
2 |
ale500 |
k_dec_su <= 1; // decrement stack pointer
|
| 808 |
|
|
end
|
| 809 |
|
|
`SEQ_PUSH_WRITE_H_1:
|
| 810 |
4 |
ale500 |
begin
|
| 811 |
|
|
if (next_state == `SEQ_JMP_LOAD_PC)
|
| 812 |
|
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
| 813 |
2 |
ale500 |
state <= next_state;
|
| 814 |
|
|
end
|
| 815 |
|
|
`SEQ_PC_READ_H: // reads high byte for [PC], used by IMM, DIR, EXT
|
| 816 |
|
|
begin
|
| 817 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 818 |
|
|
state <= `SEQ_PC_READ_H_1;
|
| 819 |
|
|
k_inc_pc <= 1;
|
| 820 |
|
|
end
|
| 821 |
|
|
`SEQ_PC_READ_H_1:
|
| 822 |
|
|
begin
|
| 823 |
|
|
k_cpu_oe <= 1; // read
|
| 824 |
|
|
state <= `SEQ_PC_READ_H_2;
|
| 825 |
|
|
end
|
| 826 |
|
|
`SEQ_PC_READ_H_2:
|
| 827 |
|
|
begin
|
| 828 |
|
|
case (dec_o_p1_mode)
|
| 829 |
|
|
`REL16, `IMMEDIATE: k_memhi <= cpu_data_i;
|
| 830 |
|
|
`EXTENDED: k_eahi <= cpu_data_i;
|
| 831 |
|
|
`INDEXED: k_ofshi <= cpu_data_i;
|
| 832 |
|
|
endcase
|
| 833 |
|
|
state <= `SEQ_PC_READ_L;
|
| 834 |
|
|
end
|
| 835 |
|
|
`SEQ_PC_READ_L: // reads low byte [PC]
|
| 836 |
|
|
begin
|
| 837 |
|
|
k_cpu_addr <= regs_o_pc;
|
| 838 |
|
|
state <= `SEQ_PC_READ_L_1;
|
| 839 |
|
|
k_inc_pc <= 1;
|
| 840 |
|
|
end
|
| 841 |
|
|
`SEQ_PC_READ_L_1:
|
| 842 |
|
|
begin
|
| 843 |
|
|
k_cpu_oe <= 1; // read
|
| 844 |
|
|
state <= `SEQ_PC_READ_L_2;
|
| 845 |
|
|
end
|
| 846 |
|
|
`SEQ_PC_READ_L_2:
|
| 847 |
|
|
begin
|
| 848 |
|
|
case (dec_o_p1_mode)
|
| 849 |
|
|
`NONE: k_pp_regs <= cpu_data_i; // push & pull
|
| 850 |
|
|
`REL8, `REL16, `IMMEDIATE: k_memlo <= cpu_data_i;
|
| 851 |
|
|
`DIRECT, `EXTENDED: k_ealo <= cpu_data_i;
|
| 852 |
|
|
`INDEXED: k_ofslo <= cpu_data_i;
|
| 853 |
4 |
ale500 |
endcase
|
| 854 |
|
|
if ((next_state == `SEQ_JMP_LOAD_PC) & (dec_o_cond_taken))
|
| 855 |
|
|
k_write_pc <= 1; // load PC in the next cycle, the mux output will have the right source
|
| 856 |
2 |
ale500 |
state <= next_state;
|
| 857 |
|
|
end
|
| 858 |
|
|
`SEQ_MEM_READ_H: // reads high byte
|
| 859 |
|
|
begin
|
| 860 |
|
|
case (dec_o_p1_mode)
|
| 861 |
|
|
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
| 862 |
|
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
| 863 |
|
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
| 864 |
4 |
ale500 |
endcase
|
| 865 |
|
|
if (k_forced_mem_size | dec_o_source_size | (k_pp_active_reg[7:4] != 0))
|
| 866 |
|
|
state <= `SEQ_MEM_READ_H_1;
|
| 867 |
|
|
else
|
| 868 |
|
|
state <= `SEQ_MEM_READ_L_1;
|
| 869 |
|
|
k_forced_mem_size <= 0; // used for vector fetch
|
| 870 |
2 |
ale500 |
end
|
| 871 |
|
|
`SEQ_MEM_READ_H_1:
|
| 872 |
|
|
begin
|
| 873 |
|
|
k_cpu_oe <= 1; // read
|
| 874 |
|
|
state <= `SEQ_MEM_READ_H_2;
|
| 875 |
|
|
end
|
| 876 |
|
|
`SEQ_MEM_READ_H_2:
|
| 877 |
|
|
begin
|
| 878 |
|
|
case (k_mem_dest)
|
| 879 |
4 |
ale500 |
`MEMDEST_PC,//: k_new_pc[15:8] <= cpu_data_i;
|
| 880 |
2 |
ale500 |
`MEMDEST_MH: k_memhi <= cpu_data_i;
|
| 881 |
|
|
`MEMDEST_AH: k_eahi <= cpu_data_i;
|
| 882 |
|
|
endcase
|
| 883 |
|
|
state <= `SEQ_MEM_READ_L_1;
|
| 884 |
4 |
ale500 |
k_cpu_addr <= k_cpu_addr + 16'h1;
|
| 885 |
|
|
case (dec_o_p1_mode)
|
| 886 |
|
|
`NONE: begin k_inc_su <= 1; end // pull, rts, rti
|
| 887 |
|
|
endcase
|
| 888 |
2 |
ale500 |
end
|
| 889 |
4 |
ale500 |
`SEQ_MEM_READ_L: // reads low byte
|
| 890 |
2 |
ale500 |
begin
|
| 891 |
4 |
ale500 |
// falls through from READ_MEM_H with the right address
|
| 892 |
2 |
ale500 |
case (dec_o_p1_mode)
|
| 893 |
4 |
ale500 |
`NONE: begin k_cpu_addr <= regs_o_su; k_inc_su <= 1; end // pull, rts, rti
|
| 894 |
2 |
ale500 |
endcase
|
| 895 |
|
|
state <= `SEQ_MEM_READ_L_1;
|
| 896 |
|
|
end
|
| 897 |
|
|
`SEQ_MEM_READ_L_1:
|
| 898 |
|
|
begin
|
| 899 |
|
|
k_cpu_oe <= 1; // read
|
| 900 |
|
|
state <= `SEQ_MEM_READ_L_2;
|
| 901 |
|
|
end
|
| 902 |
|
|
`SEQ_MEM_READ_L_2:
|
| 903 |
|
|
begin
|
| 904 |
|
|
case (k_mem_dest)
|
| 905 |
4 |
ale500 |
`MEMDEST_PC: begin k_memlo <= cpu_data_i; k_write_pc <= 1; end
|
| 906 |
2 |
ale500 |
`MEMDEST_MH: k_memlo <= cpu_data_i;
|
| 907 |
|
|
`MEMDEST_AH: k_ealo <= cpu_data_i;
|
| 908 |
|
|
endcase
|
| 909 |
|
|
case (dec_o_p1_mode)
|
| 910 |
4 |
ale500 |
`NONE, `INHERENT: k_write_dest <= 1; // pull, rts, rti
|
| 911 |
2 |
ale500 |
endcase
|
| 912 |
|
|
state <= next_mem_state;
|
| 913 |
|
|
end
|
| 914 |
|
|
`SEQ_MEM_WRITE_H: // writes high byte
|
| 915 |
|
|
begin
|
| 916 |
|
|
case (dec_o_p1_mode)
|
| 917 |
|
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
| 918 |
|
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
| 919 |
|
|
endcase
|
| 920 |
4 |
ale500 |
k_cpu_data_o <= datamux_o_dest[15:8];
|
| 921 |
2 |
ale500 |
state <= `SEQ_MEM_WRITE_H_1;
|
| 922 |
|
|
k_cpu_we <= 1; // read
|
| 923 |
|
|
end
|
| 924 |
|
|
`SEQ_MEM_WRITE_H_1:
|
| 925 |
|
|
begin
|
| 926 |
|
|
state <= `SEQ_MEM_WRITE_L;
|
| 927 |
|
|
k_cpu_addr <= k_cpu_addr + 16'h1;
|
| 928 |
|
|
end
|
| 929 |
|
|
`SEQ_MEM_WRITE_L: // reads high byte
|
| 930 |
|
|
begin
|
| 931 |
4 |
ale500 |
if (!dec_o_alu_size) // only if it is a n 8 bit write
|
| 932 |
2 |
ale500 |
case (dec_o_p1_mode)
|
| 933 |
|
|
`INDEXED: k_cpu_addr <= regs_o_eamem_addr;
|
| 934 |
|
|
default: k_cpu_addr <= { k_eahi, k_ealo };
|
| 935 |
|
|
endcase
|
| 936 |
|
|
k_cpu_data_o <= datamux_o_dest[7:0];
|
| 937 |
|
|
state <= `SEQ_MEM_WRITE_L_1;
|
| 938 |
|
|
k_cpu_we <= 1; // write
|
| 939 |
|
|
end
|
| 940 |
|
|
`SEQ_MEM_WRITE_L_1:
|
| 941 |
|
|
begin
|
| 942 |
|
|
k_write_post_incdec <= dec_o_ea_wpost;
|
| 943 |
|
|
state <= next_mem_state;
|
| 944 |
|
|
end
|
| 945 |
|
|
|
| 946 |
|
|
endcase
|
| 947 |
|
|
end
|
| 948 |
|
|
end
|
| 949 |
|
|
|
| 950 |
|
|
initial
|
| 951 |
|
|
begin
|
| 952 |
|
|
k_cpu_oe = 0;
|
| 953 |
|
|
k_cpu_we = 0;
|
| 954 |
|
|
k_mem_dest = 0;
|
| 955 |
|
|
k_new_pc = 16'hffff;
|
| 956 |
|
|
end
|
| 957 |
|
|
endmodule
|
