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/*
 * Signals which registers have to be read/written for the current opcode
 *
 *
 *
 */
`include "defs.v"
module decode_regs(
        input wire cpu_clk,
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        output wire [3:0] path_left_addr_o,
        output wire [3:0] path_right_addr_o,
        output wire [3:0] dest_reg_o,
        output reg [3:0] path_left_addr_lo,
        output reg [3:0] path_right_addr_lo,
        output reg [3:0] dest_reg_lo,
        output wire write_dest,
        output wire source_size,
        output wire result_size
        );
reg [3:0] path_left_addr, path_right_addr, dest_reg;
// for registers, memory writes are handled differently
assign write_dest = (dest_reg != `RN_INV);
assign source_size = (path_left_addr < `RN_ACCA);
// result size is used to determine the size of the argument
// to load, compare has no result, thus the source is used instead,
// why do we need the result size ?... because of tfr&exg 
assign result_size = (dest_reg == `RN_INV) ? (path_left_addr < `RN_ACCA):
                     (dest_reg < `RN_IMM16) ? 1:0;
 
assign path_right_addr_o = path_right_addr;
assign path_left_addr_o = path_left_addr;
assign dest_reg_o = dest_reg;
 
 
always @(opcode, postbyte0, page2_valid, page3_valid)
        begin
                path_left_addr = `RN_INV;
                path_right_addr = `RN_INV;
                dest_reg = `RN_INV;
                if (page2_valid)
                        begin
                                casex(postbyte0)
                                        8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
                                        8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
                                        8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
                                        8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
                                endcase
                                casex (postbyte0) // right arm
                                        8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
                                        8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
                                        8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
                                        8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
                                        8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
                                        8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
                                endcase
                                casex(postbyte0) // dest
                                        8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy
                                        8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
                                        8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
                                        8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
                                        8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
                                endcase
                        end
                if (page3_valid)
                        begin
                                casex(postbyte0)
                                        8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
                                endcase
                                casex (postbyte0) // right arm
                                        8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
                                        8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
                                        8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
                                endcase
                                casex(postbyte0) // dest
                                        8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
                                endcase
                        end
                // destination
                casex(opcode)
                        8'h1a, 8'h1c: begin path_left_addr = `RN_CC; path_right_addr = `RN_IMM8; dest_reg = `RN_CC; end // ANDCC, ORCC
                        8'h19: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end // DAA
                        8'h1d: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCA; end // SEX
                        8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg
                        8'h30: dest_reg = `RN_IX;
                        8'h31: dest_reg = `RN_IY;
                        8'h32: dest_reg = `RN_S;
                        8'h33: dest_reg = `RN_U;
                        8'h39: dest_reg = `RN_PC; // rts
                        8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
                        8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
                        8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
                        8'h0x, 8'h6x, 8'h7x:
                                case (opcode[3:0])
                                        4'he: begin end // no source or dest for jmp
                                        4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
                                        default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
                                endcase
                        8'h8x, 8'h9x, 8'hax, 8'hbx:
                                case (opcode[3:0]) // default A->A
                                        4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
                                        4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
                                        4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
                                        4'hc: path_left_addr = `RN_IX; // cmpx
                                        4'hd: begin end // nothing active, jsr
                                        4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
                                        4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
                                        default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
                                endcase
                        8'hcx, 8'hdx, 8'hex, 8'hfx:
                                case (opcode[3:0])
                                        4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
                                        4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
                                        4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
                                        4'hd: begin path_left_addr = `RN_ACCD; end // LDD
                                        4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
                                        4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
                                        default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
                                endcase
                endcase
                casex (opcode) // right arm
                        // 8x and Cx
                        8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
                        8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
                        8'b1x00_010x, 8'b1x00_0110,     8'b1x00_10xx: path_right_addr = `RN_IMM8;
                        // 9, A, B, D, E, F
                        8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
                        8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
                        8'b1x01_010x, 8'b1x01_0110,     8'b1x01_10xx: path_right_addr = `RN_MEM8;
                        8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
                        8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
                        8'b1x1x_010x, 8'b1x1x_0110,     8'b1x1x_10xx: path_right_addr = `RN_MEM8;
                endcase
        end
// latched versions are used to fetch regsiters
// not-latched version in the decoder
always @(posedge cpu_clk)
        begin
                path_right_addr_lo <= path_right_addr;
                path_left_addr_lo <= path_left_addr;
                dest_reg_lo <= dest_reg;
        end
 
endmodule
 
/* Decodes module and addressing mode for page 1 opcodes */
module decode_op(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        output reg [2:0] mode,
        output reg [2:0] optype,
        output reg op_SYNC,
        output reg op_EXG,
        output reg op_TFR,
        output reg op_RTS,
        output reg op_RTI,
        output reg op_CWAI,
        output reg op_MUL,
        output reg op_SWI,
        output reg op_PUSH,
        output reg op_PULL,
        output reg op_LEA,
        output reg op_JMP,
        output reg op_JSR,
        output reg use_s
        );
 
wire [3:0] oplo;
reg size;
assign oplo = opcode[3:0];
 
always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
        begin
                //dsize = `DSZ_8; // data operand size
                //msize = `MSZ_8; // memory operand size
                use_s = 1;
                mode = `NONE;
                size = 0;
                op_SYNC = 0;
                op_EXG = 0;
                op_TFR = 0;
                op_RTS = 0;
                op_RTI = 0;
                op_CWAI = 0;
                op_MUL = 0;
                op_SWI = 0;
                op_PUSH = 0;
                op_PULL = 0;
                op_LEA = 0;
                op_JMP = 0;
                op_JSR = 0;
                // Addressing mode
                casex(opcode)
                        8'h0x: begin mode = `DIRECT; end
                        //8'h0e: begin optype = `OP_JMP; end
                        8'h12, 8'h13, 8'h19: mode = `INHERENT;
                        8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
                        8'h16: mode = `REL16;
                        8'h17: begin mode = `REL16; op_JSR = 1; end
                        8'h1a, 8'h1c, 8'h1d: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
                        8'h1e: op_EXG = 1;
                        8'h1f: op_TFR = 1;
                        8'h2x: mode = `REL8;
                        8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; op_LEA = 1; end
                        8'h34: op_PUSH = 1;
                        8'h35: op_PULL = 1;
                        8'h36: begin op_PUSH = 1; use_s = 0; end
                        8'h37: begin op_PULL = 1; use_s = 0; end
                        8'h38, 8'h3e: mode = `NONE;
                        // don't change to inh because SEQ_MEM_READ_x would not use register S as address
                        8'h39: begin op_RTS = 1; mode = `INHERENT; end
                        8'h3b: begin op_RTI = 1; mode = `INHERENT; end
                        8'h3a, 8'h3c: mode = `INHERENT;
                        8'h3d: begin op_MUL = 1; mode = `INHERENT; end
                        8'h3f: begin op_SWI = 1; mode = `INHERENT; end
                        8'h4x: begin mode = `INHERENT; end
                        8'h5x: begin mode = `INHERENT; end
                        8'h6x: begin mode = `INDEXED; end
                        //8'h6e: begin optype = `OP_JMP; end
                        8'h7x: begin mode = `EXTENDED; end
                        //8'h7e: begin optype = `OP_JMP; end
                        8'h8x:
                                begin
                                        case (oplo)
                                                4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
                                                4'hd: mode = `REL8; // bsr
                                                default: mode = `IMMEDIATE;
                                        endcase
                                end
                        8'hcx:
                                begin
                                        case (oplo)
                                                4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
                                                default: mode = `IMMEDIATE;
                                        endcase
                                end
                        8'h9x, 8'hdx: begin mode = `DIRECT; end
                        8'hax, 8'hex: begin mode = `INDEXED; end
                        8'hbx, 8'hfx: begin mode = `EXTENDED; end
                endcase
                // Opcode type
                casex(opcode)
                        8'h0e, 8'h6e, 8'h7e: op_JMP = 1;
                        8'b10xx1101: op_JSR = 1; // bsr & jsr
                endcase
                if (page2_valid == 1'b1)
                        begin
                                casex(postbyte0)
                                        8'h2x: mode = `REL16;
                                        8'h3f: op_SWI = 1;
                                        8'h83: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
                                        8'h8c: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
                                        8'h8e: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
                                        //8'h9f, 8'haf, 8'hbf: begin  mem16 = 1; size = 1; end
                                        8'hce: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
                                        //8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
                                endcase
                                casex( postbyte0)
                                        8'h9x, 8'hdx: mode = `DIRECT;
                                        8'hax, 8'hex: mode = `INDEXED;
                                        8'hbx, 8'hfx: mode = `EXTENDED;
                                endcase
                        end
                if (page3_valid == 1'b1)
                        begin
                                casex(postbyte0)
                                        8'h3f: op_SWI = 1;
                                        8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
                                        //8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
                                        8'h8c: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
                                        8'h8e: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
                                        //8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
                                        8'hce: begin mode = `IMMEDIATE; size = 1; end
                                        //8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
                                        //8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
                                endcase
                                casex( postbyte0)
                                        8'h9x, 8'hdx: mode = `DIRECT;
                                        8'hax, 8'hex: mode = `INDEXED;
                                        8'hbx, 8'hfx: mode = `EXTENDED;
                                endcase
                        end
        end
 
endmodule
 
/* Decodes the Effective Address postbyte
   to recover size of offset to load and post-incr/pre-decr info
 */
module decode_ea(
        input wire [7:0] eapostbyte,
        output reg noofs,
        output reg ofs8, // needs an 8 bit offset
        output reg ofs16, // needs an 16 bit offset
        output reg write_post, // needs to write back a predecr or post incr
        output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address
        );
 
assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;
always @(*)
        begin
                noofs = 0;
                ofs8 = 0;
                ofs16 = 0;
                write_post = 0;
                casex (eapostbyte)
                        8'b0xxxxxxx, 8'b1xx00100: noofs = 1;
                        8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;
                        8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;
                        8'b1xx11111: ofs16 = 1; // extended indirect
                        8'b1xxx00xx: write_post = 1;
                endcase
        end
endmodule
 
module decode_alu(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode
        input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode
        output reg [4:0] alu_opcode,
        output reg [1:0] dec_alu_right_path_mod,
        output wire dest_flags
        );
// flags are written for alu opcodes as long as the opcode is not ANDCC or ORCC
assign dest_flags = (alu_opcode != `NOP) && (opcode != 8'h1a) && (opcode != 8'h1c);
always @(*)
        begin
                alu_opcode = `NOP;
                dec_alu_right_path_mod = `MOD_DEFAULT;
                casex (opcode)
                        8'b1xxx_0000: alu_opcode = `SUB;
                        8'b1xxx_0001: alu_opcode = `SUB; // CMP
                        8'b1xxx_0010: alu_opcode = `SBC;
                        8'b10xx_0011: alu_opcode = `SUB;
                        8'b11xx_0011: alu_opcode = `ADD;
                        8'b1xxx_0100: alu_opcode = `AND;
                        8'b1xxx_0101: alu_opcode = `AND; // BIT
                        8'b1xxx_0110: alu_opcode = `LD;
                        8'b1xxx_0111: alu_opcode = `ST;
                        8'b1xxx_1000: alu_opcode = `EOR;
                        8'b1xxx_1001: alu_opcode = `ADC;
                        8'b1xxx_1010: alu_opcode = `OR;
                        8'b1xxx_1011: alu_opcode = `ADD;
                        8'b10xx_1100: alu_opcode = `SUB; // CMP
                        8'b11xx_1100: alu_opcode = `LD;
                        8'b11xx_1101: alu_opcode = `LD;
                        8'b1xxx_1110: alu_opcode = `LD;
                        8'b1xxx_1111: alu_opcode = `ST;
 
                        8'h00, 8'b01xx_0000: alu_opcode = `NEG;
                        8'h03, 8'b01xx_0011: alu_opcode = `COM;
                        8'h04, 8'b01xx_0100: alu_opcode = `LSR;
                        8'h06, 8'b01xx_0110: alu_opcode = `ROR;
                        8'h07, 8'b01xx_0111: alu_opcode = `ASR;
                        8'h08, 8'b01xx_1000: alu_opcode = `LSL;
                        8'h09, 8'b01xx_1001: alu_opcode = `ROL;
                        8'h0a, 8'b01xx_1010: begin alu_opcode = `DEC; dec_alu_right_path_mod = `MOD_ONE; end // dec
                        8'h0c, 8'b01xx_1100: begin alu_opcode = `INC; dec_alu_right_path_mod = `MOD_ONE; end // inc
                        8'h0d, 8'b01xx_1101: alu_opcode = `AND;
                        8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
 
                        8'h19: alu_opcode = `DAA;
                        8'h1a: alu_opcode = `OR;
                        8'h1c: alu_opcode = `AND;
                        8'h1d: alu_opcode = `SEXT;
                        //8'h1e: alu_opcode = `EXG;
                        8'b0011_000x: alu_opcode = `LEA;
                        8'h3d: alu_opcode = `MUL;
                endcase
                if (page2_valid)
                        casex (postbyte0)
                                8'b10xx_0011,
                                8'b10xx_1100: alu_opcode = `SUB; //CMP
                                8'b1xxx_1110: alu_opcode = `LD;
                                8'b1xxx_1111: alu_opcode = `ST;
                        endcase
                if (page3_valid)
                        casex (postbyte0)
                                8'b10xx_0011,
                                8'b10xx_1100: alu_opcode = `SUB; //CMP
                                8'b1xxx_1110: alu_opcode = `LD;
                                8'b1xxx_1111: alu_opcode = `ST;
                        endcase
        end
 
endmodule
/* decodes the condition and checks the flags to see if it is met */
module test_condition(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid,
        input wire [7:0] CCR,
        output reg cond_taken
        );
 
wire [7:0] op = page2_valid ? postbyte0:opcode;
 
always @(*)
        begin
                cond_taken = 1'b0;
                if ((op == 8'h16) || (op == 8'h17) || (op == 8'h8D) ||
                        (op == 8'h0e) || (op == 8'h6e) || (op == 8'h7e)) // jmp
                        cond_taken = 1'b1; // LBRA/LBSR, BSR
                if (op[7:4] == 4'h2)
                        case (op[3:0])
                                4'h0: cond_taken = 1'b1; // BRA
                                4'h1: cond_taken = 0; // BRN
                                4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
                                4'h3: cond_taken = `DFLAGC | `DFLAGZ; // BLS
                                4'h4: cond_taken = !`DFLAGC; // BCC, BHS
                                4'h5: cond_taken = `DFLAGC; // BCS, BLO
                                4'h6: cond_taken = !`DFLAGZ; // BNE
                                4'h7: cond_taken = `DFLAGZ; // BEQ
                                4'h8: cond_taken = !`DFLAGV; // BVC
                                4'h9: cond_taken = `DFLAGV; // BVS
                                4'ha: cond_taken = !`DFLAGN; // BPL
                                4'hb: cond_taken = `DFLAGN; // BMI
                                4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
                                4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
                                4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
                                4'hf: cond_taken = (`DFLAGN != `DFLAGV) | (`DFLAGZ); // BLE
                endcase
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	ale500
2			`/*`
3			`* Signals which registers have to be read/written for the current opcode`
4			`*`
5			`*`
6			`*`
7			`*/`
8			`include "defs.v"
9	9	ale500	`module decode_regs(`
10			`input wire cpu_clk,`
11	2	ale500	`input wire [7:0] opcode,`
12			`input wire [7:0] postbyte0,`
13			`input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
14			`input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
15	11	ale500	`output wire [3:0] path_left_addr_o,`
16			`output wire [3:0] path_right_addr_o,`
17			`output wire [3:0] dest_reg_o,`
18			`output reg [3:0] path_left_addr_lo,`
19			`output reg [3:0] path_right_addr_lo,`
20			`output reg [3:0] dest_reg_lo,`
21	4	ale500	`output wire write_dest,`
22			`output wire source_size,`
23	2	ale500	`output wire result_size`
24	9	ale500	`);`
25			`reg [3:0] path_left_addr, path_right_addr, dest_reg;`
26	2	ale500	`// for registers, memory writes are handled differently`
27	4	ale500	assign write_dest = (dest_reg != `RN_INV);
28			assign source_size = (path_left_addr < `RN_ACCA);
29	12	ale500	`// result size is used to determine the size of the argument`
30			`// to load, compare has no result, thus the source is used instead,`
31			`// why do we need the result size ?... because of tfr&exg`
32			assign result_size = (dest_reg == `RN_INV) ? (path_left_addr < `RN_ACCA):
33			(dest_reg < `RN_IMM16) ? 1:0;
34	11	ale500
35			`assign path_right_addr_o = path_right_addr;`
36			`assign path_left_addr_o = path_left_addr;`
37			`assign dest_reg_o = dest_reg;`
38
39
40	2	ale500	`always @(opcode, postbyte0, page2_valid, page3_valid)`
41			`begin`
42			path_left_addr = `RN_INV;
43			path_right_addr = `RN_INV;
44			dest_reg = `RN_INV;
45	4	ale500	`if (page2_valid)`
46	2	ale500	`begin`
47			`casex(postbyte0)`
48	4	ale500	8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
49			8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
50			8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
51			8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
52			8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
53	2	ale500	`endcase`
54			`casex (postbyte0) // right arm`
55	4	ale500	8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
56	2	ale500	8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
57			8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
58			8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
59	10	ale500	8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
60	4	ale500	8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
61	2	ale500	`endcase`
62			`casex(postbyte0) // dest`
63	10	ale500	`8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd`
64			`8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy`
65			8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
66	4	ale500	8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
67	10	ale500	8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
68			8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
69	2	ale500	`endcase`
70	4	ale500	`end`
71			`if (page3_valid)`
72			`begin`
73			`casex(postbyte0)`
74			8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
75			8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
76			`endcase`
77			`casex (postbyte0) // right arm`
78	10	ale500	8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
79			8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
80			8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
81	4	ale500	`endcase`
82			`casex(postbyte0) // dest`
83			`8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu`
84			`8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps`
85			`endcase`
86	2	ale500	`end`
87			`// destination`
88	12	ale500	`casex(opcode)`
89			8'h1a, 8'h1c: begin path_left_addr = `RN_CC; path_right_addr = `RN_IMM8; dest_reg = `RN_CC; end // ANDCC, ORCC
90			8'h19: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end // DAA
91			8'h1d: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCA; end // SEX
92	5	ale500	`8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg`
93	2	ale500	8'h30: dest_reg = `RN_IX;
94			8'h31: dest_reg = `RN_IY;
95			8'h32: dest_reg = `RN_S;
96			8'h33: dest_reg = `RN_U;
97			8'h39: dest_reg = `RN_PC; // rts
98			8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
99			8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
100			8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
101	11	ale500	`8'h0x, 8'h6x, 8'h7x:`
102	12	ale500	`case (opcode[3:0])`
103			`4'he: begin end // no source or dest for jmp`
104	2	ale500	4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
105			default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
106			`endcase`
107	10	ale500	`8'h8x, 8'h9x, 8'hax, 8'hbx:`
108			`case (opcode[3:0]) // default A->A`
109	9	ale500	4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
110	2	ale500	4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
111	10	ale500	4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
112	4	ale500	4'hc: path_left_addr = `RN_IX; // cmpx
113	2	ale500	`4'hd: begin end // nothing active, jsr`
114	10	ale500	4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
115			4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
116	2	ale500	default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
117			`endcase`
118	10	ale500	`8'hcx, 8'hdx, 8'hex, 8'hfx:`
119	2	ale500	`case (opcode[3:0])`
120	9	ale500	4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
121	2	ale500	4'h3, 4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
122			4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // store to mem
123	10	ale500	4'hd: begin path_left_addr = `RN_ACCD; end // LDD
124			4'he: begin path_left_addr = `RN_U; dest_reg = `RN_U; end // LDU
125			4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
126	2	ale500	default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
127			`endcase`
128			`endcase`
129			`casex (opcode) // right arm`
130			`// 8x and Cx`
131	10	ale500	8'b1x00_000x, 8'b1x00_0010: path_right_addr = `RN_IMM8; // sub, cmp, scb
132			8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
133			8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
134	2	ale500	`// 9, A, B, D, E, F`
135			8'b1x01_000x, 8'b1x01_0010: path_right_addr = `RN_MEM8;
136	10	ale500	8'b1x01_0011, 8'b1x01_11x0: path_right_addr = `RN_MEM16; // cmpd, cmpx, ldx
137			8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx: path_right_addr = `RN_MEM8;
138	2	ale500	8'b1x1x_000x, 8'b1x1x_0010: path_right_addr = `RN_MEM8;
139	10	ale500	8'b1x1x_0011, 8'b1x1x_11x0: path_right_addr = `RN_MEM16;
140			8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
141	2	ale500	`endcase`
142			`end`
143	11	ale500	`// latched versions are used to fetch regsiters`
144			`// not-latched version in the decoder`
145	9	ale500	`always @(posedge cpu_clk)`
146			`begin`
147	11	ale500	`path_right_addr_lo <= path_right_addr;`
148			`path_left_addr_lo <= path_left_addr;`
149			`dest_reg_lo <= dest_reg;`
150	9	ale500	`end`
151	11	ale500
152	2	ale500	`endmodule`
153
154			`/* Decodes module and addressing mode for page 1 opcodes */`
155			`module decode_op(`
156			`input wire [7:0] opcode,`
157			`input wire [7:0] postbyte0,`
158			`input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
159			`input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
160			`output reg [2:0] mode,`
161			`output reg [2:0] optype,`
162	14	ale500	`output reg op_SYNC,`
163			`output reg op_EXG,`
164			`output reg op_TFR,`
165			`output reg op_RTS,`
166			`output reg op_RTI,`
167			`output reg op_CWAI,`
168			`output reg op_MUL,`
169			`output reg op_SWI,`
170			`output reg op_PUSH,`
171			`output reg op_PULL,`
172			`output reg op_LEA,`
173			`output reg op_JMP,`
174			`output reg op_JSR,`
175	2	ale500	`output reg use_s`
176			`);`
177
178			`wire [3:0] oplo;`
179			`reg size;`
180			`assign oplo = opcode[3:0];`
181
182			`always @(opcode, postbyte0, page2_valid, page3_valid, oplo)`
183			`begin`
184			//dsize = `DSZ_8; // data operand size
185			//msize = `MSZ_8; // memory operand size
186			`use_s = 1;`
187			mode = `NONE;
188			`size = 0;`
189	14	ale500	`op_SYNC = 0;`
190			`op_EXG = 0;`
191			`op_TFR = 0;`
192			`op_RTS = 0;`
193			`op_RTI = 0;`
194			`op_CWAI = 0;`
195			`op_MUL = 0;`
196			`op_SWI = 0;`
197			`op_PUSH = 0;`
198			`op_PULL = 0;`
199			`op_LEA = 0;`
200			`op_JMP = 0;`
201			`op_JSR = 0;`
202	2	ale500	`// Addressing mode`
203			`casex(opcode)`
204			8'h0x: begin mode = `DIRECT; end
205	12	ale500	//8'h0e: begin optype = `OP_JMP; end
206	2	ale500	8'h12, 8'h13, 8'h19: mode = `INHERENT;
207			8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
208			8'h16: mode = `REL16;
209	14	ale500	8'h17: begin mode = `REL16; op_JSR = 1; end
210			8'h1a, 8'h1c, 8'h1d: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
211			`8'h1e: op_EXG = 1;`
212			`8'h1f: op_TFR = 1;`
213	2	ale500	8'h2x: mode = `REL8;
214	14	ale500	8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; op_LEA = 1; end
215			`8'h34: op_PUSH = 1;`
216			`8'h35: op_PULL = 1;`
217			`8'h36: begin op_PUSH = 1; use_s = 0; end`
218			`8'h37: begin op_PULL = 1; use_s = 0; end`
219	2	ale500	8'h38, 8'h3e: mode = `NONE;
220			`// don't change to inh because SEQ_MEM_READ_x would not use register S as address`
221	14	ale500	8'h39: begin op_RTS = 1; mode = `INHERENT; end
222			8'h3b: begin op_RTI = 1; mode = `INHERENT; end
223			8'h3a, 8'h3c: mode = `INHERENT;
224			8'h3d: begin op_MUL = 1; mode = `INHERENT; end
225			8'h3f: begin op_SWI = 1; mode = `INHERENT; end
226	2	ale500	8'h4x: begin mode = `INHERENT; end
227			8'h5x: begin mode = `INHERENT; end
228			8'h6x: begin mode = `INDEXED; end
229	12	ale500	//8'h6e: begin optype = `OP_JMP; end
230	2	ale500	8'h7x: begin mode = `EXTENDED; end
231	12	ale500	//8'h7e: begin optype = `OP_JMP; end
232	2	ale500	`8'h8x:`
233			`begin`
234			`case (oplo)`
235			4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
236			4'hd: mode = `REL8; // bsr
237			default: mode = `IMMEDIATE;
238			`endcase`
239			`end`
240			`8'hcx:`
241			`begin`
242			`case (oplo)`
243			4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
244			default: mode = `IMMEDIATE;
245			`endcase`
246			`end`
247			8'h9x, 8'hdx: begin mode = `DIRECT; end
248			8'hax, 8'hex: begin mode = `INDEXED; end
249			8'hbx, 8'hfx: begin mode = `EXTENDED; end
250			`endcase`
251			`// Opcode type`
252			`casex(opcode)`
253	14	ale500	`8'h0e, 8'h6e, 8'h7e: op_JMP = 1;`
254			`8'b10xx1101: op_JSR = 1; // bsr & jsr`
255	2	ale500	`endcase`
256			`if (page2_valid == 1'b1)`
257			`begin`
258			`casex(postbyte0)`
259	12	ale500	8'h2x: mode = `REL16;
260	14	ale500	`8'h3f: op_SWI = 1;`
261	2	ale500	8'h83: begin mode = `IMMEDIATE; size = 1; end
262			`//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end`
263			8'h8c: begin mode = `IMMEDIATE; size = 1; end
264			`//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end`
265			8'h8e: begin mode = `IMMEDIATE; size = 1; end
266			`//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end`
267			`//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end`
268			8'hce: begin mode = `IMMEDIATE; size = 1; end
269			`//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end`
270			`//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end`
271			`endcase`
272			`casex( postbyte0)`
273			8'h9x, 8'hdx: mode = `DIRECT;
274			8'hax, 8'hex: mode = `INDEXED;
275			8'hbx, 8'hfx: mode = `EXTENDED;
276			`endcase`
277			`end`
278			`if (page3_valid == 1'b1)`
279			`begin`
280			`casex(postbyte0)`
281	14	ale500	`8'h3f: op_SWI = 1;`
282	2	ale500	8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
283			`//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD`
284			8'h8c: begin mode = `IMMEDIATE; size = 1; end
285			`//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end`
286			8'h8e: begin mode = `IMMEDIATE; size = 1; end
287			`//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end`
288			`//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end`
289			8'hce: begin mode = `IMMEDIATE; size = 1; end
290			`//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end`
291			`//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end`
292			`endcase`
293			`casex( postbyte0)`
294			8'h9x, 8'hdx: mode = `DIRECT;
295			8'hax, 8'hex: mode = `INDEXED;
296			8'hbx, 8'hfx: mode = `EXTENDED;
297			`endcase`
298			`end`
299			`end`
300
301			`endmodule`
302
303			`/* Decodes the Effective Address postbyte`
304			`to recover size of offset to load and post-incr/pre-decr info`
305			`*/`
306			`module decode_ea(`
307			`input wire [7:0] eapostbyte,`
308			`output reg noofs,`
309			`output reg ofs8, // needs an 8 bit offset`
310			`output reg ofs16, // needs an 16 bit offset`
311			`output reg write_post, // needs to write back a predecr or post incr`
312			`output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address`
313			`);`
314
315			`assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;`
316			`always @(*)`
317			`begin`
318			`noofs = 0;`
319			`ofs8 = 0;`
320			`ofs16 = 0;`
321			`write_post = 0;`
322			`casex (eapostbyte)`
323			`8'b0xxxxxxx, 8'b1xx00100: noofs = 1;`
324			`8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;`
325			`8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;`
326			`8'b1xx11111: ofs16 = 1; // extended indirect`
327			`8'b1xxx00xx: write_post = 1;`
328			`endcase`
329			`end`
330			`endmodule`
331
332			`module decode_alu(`
333			`input wire [7:0] opcode,`
334			`input wire [7:0] postbyte0,`
335			`input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode`
336			`input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode`
337			`output reg [4:0] alu_opcode,`
338			`output reg [1:0] dec_alu_right_path_mod,`
339			`output wire dest_flags`
340			`);`
341	12	ale500	`// flags are written for alu opcodes as long as the opcode is not ANDCC or ORCC`
342			assign dest_flags = (alu_opcode != `NOP) && (opcode != 8'h1a) && (opcode != 8'h1c);
343	2	ale500	`always @(*)`
344			`begin`
345			alu_opcode = `NOP;
346			dec_alu_right_path_mod = `MOD_DEFAULT;
347			`casex (opcode)`
348			8'b1xxx_0000: alu_opcode = `SUB;
349	9	ale500	8'b1xxx_0001: alu_opcode = `SUB; // CMP
350	2	ale500	8'b1xxx_0010: alu_opcode = `SBC;
351			8'b10xx_0011: alu_opcode = `SUB;
352			8'b11xx_0011: alu_opcode = `ADD;
353			8'b1xxx_0100: alu_opcode = `AND;
354	9	ale500	8'b1xxx_0101: alu_opcode = `AND; // BIT
355	2	ale500	8'b1xxx_0110: alu_opcode = `LD;
356			8'b1xxx_0111: alu_opcode = `ST;
357			8'b1xxx_1000: alu_opcode = `EOR;
358			8'b1xxx_1001: alu_opcode = `ADC;
359			8'b1xxx_1010: alu_opcode = `OR;
360			8'b1xxx_1011: alu_opcode = `ADD;
361	9	ale500	8'b10xx_1100: alu_opcode = `SUB; // CMP
362	2	ale500	8'b11xx_1100: alu_opcode = `LD;
363			8'b11xx_1101: alu_opcode = `LD;
364			8'b1xxx_1110: alu_opcode = `LD;
365			8'b1xxx_1111: alu_opcode = `ST;
366
367			8'h00, 8'b01xx_0000: alu_opcode = `NEG;
368			8'h03, 8'b01xx_0011: alu_opcode = `COM;
369			8'h04, 8'b01xx_0100: alu_opcode = `LSR;
370			8'h06, 8'b01xx_0110: alu_opcode = `ROR;
371			8'h07, 8'b01xx_0111: alu_opcode = `ASR;
372			8'h08, 8'b01xx_1000: alu_opcode = `LSL;
373			8'h09, 8'b01xx_1001: alu_opcode = `ROL;
374	12	ale500	8'h0a, 8'b01xx_1010: begin alu_opcode = `DEC; dec_alu_right_path_mod = `MOD_ONE; end // dec
375			8'h0c, 8'b01xx_1100: begin alu_opcode = `INC; dec_alu_right_path_mod = `MOD_ONE; end // inc
376	2	ale500	8'h0d, 8'b01xx_1101: alu_opcode = `AND;
377			8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
378
379			8'h19: alu_opcode = `DAA;
380	12	ale500	8'h1a: alu_opcode = `OR;
381			8'h1c: alu_opcode = `AND;
382	2	ale500	8'h1d: alu_opcode = `SEXT;
383	9	ale500	//8'h1e: alu_opcode = `EXG;
384	4	ale500	8'b0011_000x: alu_opcode = `LEA;
385	2	ale500	8'h3d: alu_opcode = `MUL;
386			`endcase`
387			`if (page2_valid)`
388			`casex (postbyte0)`
389			`8'b10xx_0011,`
390	12	ale500	8'b10xx_1100: alu_opcode = `SUB; //CMP
391	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
392			8'b1xxx_1111: alu_opcode = `ST;
393			`endcase`
394			`if (page3_valid)`
395			`casex (postbyte0)`
396			`8'b10xx_0011,`
397	12	ale500	8'b10xx_1100: alu_opcode = `SUB; //CMP
398	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
399			8'b1xxx_1111: alu_opcode = `ST;
400			`endcase`
401			`end`
402
403			`endmodule`
404			`/* decodes the condition and checks the flags to see if it is met */`
405			`module test_condition(`
406			`input wire [7:0] opcode,`
407			`input wire [7:0] postbyte0,`
408			`input wire page2_valid,`
409			`input wire [7:0] CCR,`
410			`output reg cond_taken`
411			`);`
412
413			`wire [7:0] op = page2_valid ? postbyte0:opcode;`
414
415			`always @(*)`
416			`begin`
417			`cond_taken = 1'b0;`
418	12	ale500	`if ((op == 8'h16) \|\| (op == 8'h17) \|\| (op == 8'h8D) \|\|`
419			`(op == 8'h0e) \|\| (op == 8'h6e) \|\| (op == 8'h7e)) // jmp`
420	2	ale500	`cond_taken = 1'b1; // LBRA/LBSR, BSR`
421			`if (op[7:4] == 4'h2)`
422			`case (op[3:0])`
423			`4'h0: cond_taken = 1'b1; // BRA`
424			`4'h1: cond_taken = 0; // BRN`
425			4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
426			4'h3: cond_taken = `DFLAGC \| `DFLAGZ; // BLS
427			4'h4: cond_taken = !`DFLAGC; // BCC, BHS
428			4'h5: cond_taken = `DFLAGC; // BCS, BLO
429			4'h6: cond_taken = !`DFLAGZ; // BNE
430			4'h7: cond_taken = `DFLAGZ; // BEQ
431			4'h8: cond_taken = !`DFLAGV; // BVC
432			4'h9: cond_taken = `DFLAGV; // BVS
433			4'ha: cond_taken = !`DFLAGN; // BPL
434			4'hb: cond_taken = `DFLAGN; // BMI
435			4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
436			4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
437			4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
438			4'hf: cond_taken = (`DFLAGN != `DFLAGV) \| (`DFLAGZ); // BLE
439			`endcase`
440			`end`
441
442			`endmodule`

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