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[/] [6809_6309_compatible_core/] [trunk/] [sim/] [README.txt] - Blame information for rev 2

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MC6809/HD6309 compatible core.
 
Simulation can be done with icarus verilog.
 
$ iverilog tb.v ../rtl/verilog/*.v
$ vvp a.out
 
a dump file dump.vcd will be created. This file can be viewed with GTKWave.
Simulation with other tools is also possible.

Line No.	Rev	Author	Line
1	2	ale500	`MC6809/HD6309 compatible core.`
2
3			`Simulation can be done with icarus verilog.`
4
5			`$ iverilog tb.v ../rtl/verilog/*.v`
6			`$ vvp a.out`
7
8			`a dump file dump.vcd will be created. This file can be viewed with GTKWave.`
9			`Simulation with other tools is also possible.`

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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [sim/] [README.txt] - Blame information for rev 2