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/* MC6809/HD6309 Compatible core
 * (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
 *
 * Distributed under the terms of the Lesser GPL
 */
`timescale 1ns/1ns
 
module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);
 
reg clk, reset;
 
assign addr_o = addr;
assign data_o_o = data_o;
wire [15:0] addr;
wire [7:0] data_o, data_i;
wire oe, we;
always
        #5 clk = ~clk;
 
MC6809_cpu cpu(
        .cpu_clk(clk),
        .cpu_reset(reset),
        .cpu_we_o(we),
        .cpu_oe_o(oe),
        .cpu_addr_o(addr),
        .cpu_data_i(data_i),
        .cpu_data_o(data_o)
        );
 
memory imem(addr, !oe, !we, data_i, data_o);
 
initial
        begin
                $dumpvars;
                clk = 0;
                reset = 1;
                #0
                #46
                reset = 0;
                #111500
                $finish;
        end
 
endmodule
 
module memory(
        input wire [15:0] addr,
        input wire oe,
        input wire we,
        output wire [7:0] data_o,
        input wire [7:0] data_i
        );
 
reg [7:0] mem[65535:0];
reg [7:0] latecheddata;
wire [7:0] mem0, mem1, mem2, mem3;
 
assign mem0 = mem[0];
assign mem1 = mem[1];
assign mem2 = mem[2];
assign mem3 = mem[3];
 
assign data_o = latecheddata;
always @(negedge oe)
        latecheddata <= mem[addr];
 
always @(negedge we)
        begin
                mem[addr] <= data_i;
                $display("W %04x = %02x %t", addr, data_i, $time);
        end
 
always @(negedge oe)
        begin
                $display("R %04x = %02x %t", addr, mem[addr], $time);
        end
`define READTESTBIN
integer i;
initial
        begin
`ifdef READTESTBIN
/*
                $readmemh("test09.hex", mem);//instructions_test.hex", mem);
                $display("instructions_test.hex read");
                mem[16'hfffe] = 8'h00; // setup reset
                mem[16'hffff] = 8'h00;
*/
                $readmemh("monitor.hex", mem);
                $display("monitor.hex read");
                for (i = 0; i < 7168; i=i+1)// move monitor to its new location
                        begin
                                mem[16'he400+i] = mem[i];
                                mem[i] = 8'h0;
                        end
 
`else
                for (i = 0; i < 65536; i=i+1)
                        mem[i] = 8'ha5;
 
                mem[16'h1000] = 8'h8e; // ldx #$100
                mem[16'h1001] = 8'h01; // 
                mem[16'h1002] = 8'h00; // 
 
                mem[16'h1003] = 8'hbf; // stx $102              
                mem[16'h1004] = 8'h01; // 
                mem[16'h1005] = 8'h02; // 
 
                mem[16'h1006] = 8'h0f; // clr $10
                mem[16'h1007] = 8'h10; // 
 
                mem[16'h1008] = 8'h7f; // clr $1234
                mem[16'h1009] = 8'h12; // 
                mem[16'h100a] = 8'h34; // 
 
                mem[16'h100b] = 8'h0c; // inc $10
                mem[16'h100c] = 8'h10; // 
 
                mem[16'h100d] = 8'h7c; // inc $1234
                mem[16'h100e] = 8'h12; // 
                mem[16'h100f] = 8'h34; // 
 
                mem[16'h1010] = 8'h0a; // dec $10
                mem[16'h1011] = 8'h10; // 
 
                mem[16'h1012] = 8'h7a; // dec $1234
                mem[16'h1013] = 8'h12; // 
                mem[16'h1014] = 8'h34; // 
 
                mem[16'h1015] = 8'h20; // bra *
                mem[16'h1016] = 8'hfe; // 
 
 
 
/*
// test indexed store
                mem[16'h1000] = 8'h86; // lda #$02
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'h9e; // ldx $00 (direct)
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'ha7; // lda ,x
                mem[16'h1005] = 8'b10000100; // ofs0
                mem[16'h1006] = 8'ha7; // lda ,x+
                mem[16'h1007] = 8'b10000000; //
 
 
                mem[16'h1008] = 8'ha7; // lda ,x++
                mem[16'h1009] = 8'b10000001; //
                mem[16'h100a] = 8'ha6; // lda ,-x
                mem[16'h100b] = 8'b10000010; //
 
                mem[16'h100c] = 8'ha7; // lda ,--x
                mem[16'h100d] = 8'b10000011; //
 
                mem[16'h100e] = 8'ha7; // lda 0,x ofs 5
                mem[16'h100f] = 8'h00; //
 
                mem[16'h1010] = 8'ha7; // lda 0,x ofs 8
                mem[16'h1011] = 8'b10001000; //
                mem[16'h1012] = 8'h00; //
 
                mem[16'h1013] = 8'ha7; // lda 0,x ofs 16
                mem[16'h1014] = 8'b10001001; //
                mem[16'h1015] = 8'h00; //
                mem[16'h1016] = 8'h00; //
*/
 
/* test indexed load
                mem[16'h1000] = 8'h86; // lda #$02
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'h9e; // ldx $00 (direct)
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'ha6; // lda ,x
                mem[16'h1005] = 8'b10000100; // ofs0
                mem[16'h1006] = 8'ha6; // lda ,x+
                mem[16'h1007] = 8'b10000000; //
 
 
                mem[16'h1008] = 8'ha6; // lda ,x++
                mem[16'h1009] = 8'b10000001; //
                mem[16'h100a] = 8'ha6; // lda ,-x
                mem[16'h100b] = 8'b10000010; //
 
                mem[16'h100c] = 8'ha6; // lda ,--x
                mem[16'h100d] = 8'b10000011; //
 
                mem[16'h100e] = 8'ha6; // lda 0,x ofs 5
                mem[16'h100f] = 8'h00; //
 
                mem[16'h1010] = 8'ha6; // lda 0,x ofs 8
                mem[16'h1011] = 8'b10001000; //
                mem[16'h1012] = 8'h00; //
 
                mem[16'h1013] = 8'ha6; // lda 0,x ofs 16
                mem[16'h1014] = 8'b10001001; //
                mem[16'h1015] = 8'h00; //
                mem[16'h1016] = 8'h00; //
*/
 
/* test extended
                mem[16'h1000] = 8'h86; // ldb #$fe
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'hc6; // lda #$0
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'h97; // inca
                mem[16'h1005] = 8'h00; // sta $0000
                mem[16'h1006] = 8'hd7; //
                mem[16'h1007] = 8'h01; //
 
 
                mem[16'h1008] = 8'hb6; // lda $0000
                mem[16'h1009] = 8'h00; //
                mem[16'h100a] = 8'h00; //
 
                mem[16'h100b] = 8'h26; // bne$.-5
                mem[16'h100c] = 8'hf7; //
 
                mem[16'h100d] = 8'h5c; // incb
 
                mem[16'h100e] = 8'hf7; // stb $0001
                mem[16'h100f] = 8'h00; //
                mem[16'h1010] = 8'h01; //
 
                mem[16'h1011] = 8'h20; // bra
                mem[16'h1012] = 8'hec; // $.-18
*/
                mem[16'hfff0] = 8'h20; // reset
                mem[16'hfff1] = 8'h00;
                mem[16'hfff2] = 8'h20; // reset
                mem[16'hfff3] = 8'h02;
                mem[16'hfff4] = 8'h20; // reset
                mem[16'hfff5] = 8'h04;
                mem[16'hfff6] = 8'h20; // reset
                mem[16'hfff7] = 8'h06;
                mem[16'hfff8] = 8'h20; // reset
                mem[16'hfff9] = 8'h08;
                mem[16'hfffa] = 8'h20; // reset
                mem[16'hfffb] = 8'h0a;
                mem[16'hfffc] = 8'h20; // reset
                mem[16'hfffd] = 8'h0c;
                mem[16'hfffe] = 8'h10; // reset
                mem[16'hffff] = 8'h00;
`endif
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	ale500	`/* MC6809/HD6309 Compatible core`
2			`* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com`
3			`*`
4			`* Distributed under the terms of the Lesser GPL`
5			`*/`
6	4	ale500	`timescale 1ns/1ns
7
8			`module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);`
9
10			`reg clk, reset;`
11
12			`assign addr_o = addr;`
13			`assign data_o_o = data_o;`
14			`wire [15:0] addr;`
15			`wire [7:0] data_o, data_i;`
16			`wire oe, we;`
17			`always`
18			`#5 clk = ~clk;`
19
20			`MC6809_cpu cpu(`
21			`.cpu_clk(clk),`
22			`.cpu_reset(reset),`
23			`.cpu_we_o(we),`
24			`.cpu_oe_o(oe),`
25			`.cpu_addr_o(addr),`
26			`.cpu_data_i(data_i),`
27			`.cpu_data_o(data_o)`
28			`);`
29
30			`memory imem(addr, !oe, !we, data_i, data_o);`
31	2	ale500
32			`initial`
33			`begin`
34	4	ale500	`$dumpvars;`
35			`clk = 0;`
36			`reset = 1;`
37			`#0`
38			`#46`
39			`reset = 0;`
40	12	ale500	`#111500`
41	4	ale500	`$finish;`
42			`end`
43
44			`endmodule`
45
46	2	ale500	`module memory(`
47			`input wire [15:0] addr,`
48			`input wire oe,`
49			`input wire we,`
50			`output wire [7:0] data_o,`
51			`input wire [7:0] data_i`
52			`);`
53
54			`reg [7:0] mem[65535:0];`
55			`reg [7:0] latecheddata;`
56			`wire [7:0] mem0, mem1, mem2, mem3;`
57
58			`assign mem0 = mem[0];`
59			`assign mem1 = mem[1];`
60			`assign mem2 = mem[2];`
61			`assign mem3 = mem[3];`
62
63	4	ale500	`assign data_o = latecheddata;`
64			`always @(negedge oe)`
65	2	ale500	`latecheddata <= mem[addr];`
66
67	4	ale500	`always @(negedge we)`
68			`begin`
69	2	ale500	`mem[addr] <= data_i;`
70			`$display("W %04x = %02x %t", addr, data_i, $time);`
71			`end`
72
73			`always @(negedge oe)`
74			`begin`
75			`$display("R %04x = %02x %t", addr, mem[addr], $time);`
76			`end`
77	12	ale500	`define READTESTBIN
78	2	ale500	`integer i;`
79			`initial`
80			`begin`
81			`ifdef READTESTBIN
82	14	ale500	`/*`
83	12	ale500	`$readmemh("test09.hex", mem);//instructions_test.hex", mem);`
84	2	ale500	`$display("instructions_test.hex read");`
85	12	ale500	`mem[16'hfffe] = 8'h00; // setup reset`
86	13	ale500	`mem[16'hffff] = 8'h00;`
87	14	ale500	`*/`
88			`$readmemh("monitor.hex", mem);`
89			`$display("monitor.hex read");`
90			`for (i = 0; i < 7168; i=i+1)// move monitor to its new location`
91			`begin`
92			`mem[16'he400+i] = mem[i];`
93			`mem[i] = 8'h0;`
94			`end`
95
96	2	ale500	`else
97			`for (i = 0; i < 65536; i=i+1)`
98			`mem[i] = 8'ha5;`
99	10	ale500
100			`mem[16'h1000] = 8'h8e; // ldx #$100`
101			`mem[16'h1001] = 8'h01; //`
102			`mem[16'h1002] = 8'h00; //`
103
104	11	ale500	`mem[16'h1003] = 8'hbf; // stx $102`
105	10	ale500	`mem[16'h1004] = 8'h01; //`
106			`mem[16'h1005] = 8'h02; //`
107
108	11	ale500	`mem[16'h1006] = 8'h0f; // clr $10`
109			`mem[16'h1007] = 8'h10; //`
110
111			`mem[16'h1008] = 8'h7f; // clr $1234`
112			`mem[16'h1009] = 8'h12; //`
113			`mem[16'h100a] = 8'h34; //`
114	10	ale500
115	11	ale500	`mem[16'h100b] = 8'h0c; // inc $10`
116			`mem[16'h100c] = 8'h10; //`
117
118			`mem[16'h100d] = 8'h7c; // inc $1234`
119			`mem[16'h100e] = 8'h12; //`
120			`mem[16'h100f] = 8'h34; //`
121	10	ale500
122	11	ale500	`mem[16'h1010] = 8'h0a; // dec $10`
123			`mem[16'h1011] = 8'h10; //`
124	2	ale500
125	11	ale500	`mem[16'h1012] = 8'h7a; // dec $1234`
126			`mem[16'h1013] = 8'h12; //`
127			`mem[16'h1014] = 8'h34; //`
128
129			`mem[16'h1015] = 8'h20; // bra *`
130			`mem[16'h1016] = 8'hfe; //`
131	2	ale500
132
133	11	ale500
134	2	ale500	`/*`
135			`// test indexed store`
136	4	ale500	`mem[16'h1000] = 8'h86; // lda #$02`
137	2	ale500	`mem[16'h1001] = 8'h02; //`
138			`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
139			`mem[16'h1003] = 8'h00; //`
140
141			`mem[16'h1004] = 8'ha7; // lda ,x`
142			`mem[16'h1005] = 8'b10000100; // ofs0`
143			`mem[16'h1006] = 8'ha7; // lda ,x+`
144			`mem[16'h1007] = 8'b10000000; //`
145
146
147			`mem[16'h1008] = 8'ha7; // lda ,x++`
148			`mem[16'h1009] = 8'b10000001; //`
149			`mem[16'h100a] = 8'ha6; // lda ,-x`
150			`mem[16'h100b] = 8'b10000010; //`
151
152			`mem[16'h100c] = 8'ha7; // lda ,--x`
153			`mem[16'h100d] = 8'b10000011; //`
154
155			`mem[16'h100e] = 8'ha7; // lda 0,x ofs 5`
156			`mem[16'h100f] = 8'h00; //`
157
158			`mem[16'h1010] = 8'ha7; // lda 0,x ofs 8`
159			`mem[16'h1011] = 8'b10001000; //`
160			`mem[16'h1012] = 8'h00; //`
161
162			`mem[16'h1013] = 8'ha7; // lda 0,x ofs 16`
163			`mem[16'h1014] = 8'b10001001; //`
164			`mem[16'h1015] = 8'h00; //`
165			`mem[16'h1016] = 8'h00; //`
166			`*/`
167
168			`/* test indexed load`
169			`mem[16'h1000] = 8'h86; // lda #$02`
170			`mem[16'h1001] = 8'h02; //`
171			`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
172			`mem[16'h1003] = 8'h00; //`
173
174			`mem[16'h1004] = 8'ha6; // lda ,x`
175			`mem[16'h1005] = 8'b10000100; // ofs0`
176			`mem[16'h1006] = 8'ha6; // lda ,x+`
177			`mem[16'h1007] = 8'b10000000; //`
178
179
180			`mem[16'h1008] = 8'ha6; // lda ,x++`
181			`mem[16'h1009] = 8'b10000001; //`
182			`mem[16'h100a] = 8'ha6; // lda ,-x`
183			`mem[16'h100b] = 8'b10000010; //`
184
185			`mem[16'h100c] = 8'ha6; // lda ,--x`
186			`mem[16'h100d] = 8'b10000011; //`
187
188			`mem[16'h100e] = 8'ha6; // lda 0,x ofs 5`
189			`mem[16'h100f] = 8'h00; //`
190
191			`mem[16'h1010] = 8'ha6; // lda 0,x ofs 8`
192			`mem[16'h1011] = 8'b10001000; //`
193			`mem[16'h1012] = 8'h00; //`
194
195			`mem[16'h1013] = 8'ha6; // lda 0,x ofs 16`
196			`mem[16'h1014] = 8'b10001001; //`
197			`mem[16'h1015] = 8'h00; //`
198			`mem[16'h1016] = 8'h00; //`
199			`*/`
200
201	10	ale500	`/* test extended`
202	4	ale500	`mem[16'h1000] = 8'h86; // ldb #$fe`
203			`mem[16'h1001] = 8'h02; //`
204			`mem[16'h1002] = 8'hc6; // lda #$0`
205	2	ale500	`mem[16'h1003] = 8'h00; //`
206
207	4	ale500	`mem[16'h1004] = 8'h97; // inca`
208			`mem[16'h1005] = 8'h00; // sta $0000`
209			`mem[16'h1006] = 8'hd7; //`
210			`mem[16'h1007] = 8'h01; //`
211	2	ale500
212
213			`mem[16'h1008] = 8'hb6; // lda $0000`
214			`mem[16'h1009] = 8'h00; //`
215			`mem[16'h100a] = 8'h00; //`
216
217			`mem[16'h100b] = 8'h26; // bne$.-5`
218			`mem[16'h100c] = 8'hf7; //`
219
220			`mem[16'h100d] = 8'h5c; // incb`
221
222			`mem[16'h100e] = 8'hf7; // stb $0001`
223			`mem[16'h100f] = 8'h00; //`
224			`mem[16'h1010] = 8'h01; //`
225
226			`mem[16'h1011] = 8'h20; // bra`
227			`mem[16'h1012] = 8'hec; // $.-18`
228	10	ale500	`*/`
229	2	ale500	`mem[16'hfff0] = 8'h20; // reset`
230			`mem[16'hfff1] = 8'h00;`
231			`mem[16'hfff2] = 8'h20; // reset`
232			`mem[16'hfff3] = 8'h02;`
233			`mem[16'hfff4] = 8'h20; // reset`
234			`mem[16'hfff5] = 8'h04;`
235			`mem[16'hfff6] = 8'h20; // reset`
236			`mem[16'hfff7] = 8'h06;`
237			`mem[16'hfff8] = 8'h20; // reset`
238			`mem[16'hfff9] = 8'h08;`
239			`mem[16'hfffa] = 8'h20; // reset`
240			`mem[16'hfffb] = 8'h0a;`
241			`mem[16'hfffc] = 8'h20; // reset`
242			`mem[16'hfffd] = 8'h0c;`
243			`mem[16'hfffe] = 8'h10; // reset`
244			`mem[16'hffff] = 8'h00;`
245			`endif
246			`end`
247
248			`endmodule`

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[/] [6809_6309_compatible_core/] [trunk/] [sim/] [tb.v] - Blame information for rev 14