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[/] [6809_6309_compatible_core/] [trunk/] [sim/] [tb_irq.v] - Blame information for rev 19

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/* MC6809/HD6309 Compatible core
 * (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
 *
 * Distributed under the terms of the Lesser GPL
 */
`timescale 1ns/1ns
 
module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);
 
reg clk, reset, firq, nmi,irq;
 
assign addr_o = addr;
assign data_o_o = data_o;
wire [15:0] addr;
wire [7:0] data_o, data_i;
wire oe, we;
always
        #5 clk = ~clk;
 
MC6809_cpu cpu(
        .cpu_clk(clk),
        .cpu_reset(reset),
        .cpu_we_o(we),
        .cpu_oe_o(oe),
        .cpu_addr_o(addr),
        .cpu_data_i(data_i),
        .cpu_data_o(data_o),
    .cpu_irq_n(irq),
    .cpu_firq_n(firq),
    .cpu_nmi_n(nmi)
        );
 
memory imem(addr, !oe, !we, data_i, data_o);
 
initial
        begin
                $dumpvars;
                clk = 0;
                reset = 1;
        irq = 1;
        firq = 1;
        nmi = 1;
                #0
                #46
                reset = 0;
        #500
        nmi = 0;
        #22
        nmi = 1;
        #1000
        firq = 0;
        #22
        firq = 1;
        #1000
 
                #10000
                $finish;
        end
 
endmodule
 
module memory(
        input wire [15:0] addr,
        input wire oe,
        input wire we,
        output wire [7:0] data_o,
        input wire [7:0] data_i
        );
 
reg [7:0] mem[65535:0];
reg [7:0] latecheddata;
wire [7:0] mem0, mem1, mem2, mem3;
 
assign mem0 = mem[0];
assign mem1 = mem[1];
assign mem2 = mem[2];
assign mem3 = mem[3];
 
assign data_o = latecheddata;
always @(negedge oe)
        latecheddata <= mem[addr];
 
always @(negedge we)
        begin
                mem[addr] <= data_i;
                $display("W %04x = %02x %t", addr, data_i, $time);
        end
 
always @(negedge oe)
        begin
                $display("R %04x = %02x %t", addr, mem[addr], $time);
        end
`define READTESTBIN
integer i;
initial
        begin
`ifdef READTESTBIN
 
                $readmemh("instructions_test.hex", mem);
                $display("instructions_test.hex read");
                mem[16'hfffe] = 8'h00; // setup reset
                mem[16'hffff] = 8'h00;
                mem[16'hfffc] = 8'h00; // nmi
                mem[16'hfffd] = 8'h71;
                mem[16'hfffa] = 8'h00; // swi
                mem[16'hfffb] = 8'h71;
                mem[16'hfff8] = 8'h00; // irq
                mem[16'hfff9] = 8'h71;
        mem[16'hfff6] = 8'h00; // firq
                mem[16'hfff7] = 8'h71;
/*
                $readmemh("monitor.hex", mem);
                $display("monitor.hex read");
                for (i = 0; i < 7168; i=i+1)// move monitor to its new location
                        begin
                                mem[16'he400+i] = mem[i];
                                mem[i] = 8'h0;
                        end
*/
`else
                for (i = 0; i < 65536; i=i+1)
                        mem[i] = 8'ha5;
 
                mem[16'h1000] = 8'h8e; // ldx #$100
                mem[16'h1001] = 8'h01; // 
                mem[16'h1002] = 8'h00; // 
 
                mem[16'h1003] = 8'hbf; // stx $102              
                mem[16'h1004] = 8'h01; // 
                mem[16'h1005] = 8'h02; // 
 
                mem[16'h1006] = 8'h0f; // clr $10
                mem[16'h1007] = 8'h10; // 
 
                mem[16'h1008] = 8'h7f; // clr $1234
                mem[16'h1009] = 8'h12; // 
                mem[16'h100a] = 8'h34; // 
 
                mem[16'h100b] = 8'h0c; // inc $10
                mem[16'h100c] = 8'h10; // 
 
                mem[16'h100d] = 8'h7c; // inc $1234
                mem[16'h100e] = 8'h12; // 
                mem[16'h100f] = 8'h34; // 
 
                mem[16'h1010] = 8'h0a; // dec $10
                mem[16'h1011] = 8'h10; // 
 
                mem[16'h1012] = 8'h7a; // dec $1234
                mem[16'h1013] = 8'h12; // 
                mem[16'h1014] = 8'h34; // 
 
                mem[16'h1015] = 8'h20; // bra *
                mem[16'h1016] = 8'hfe; // 
 
 
 
/*
// test indexed store
                mem[16'h1000] = 8'h86; // lda #$02
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'h9e; // ldx $00 (direct)
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'ha7; // lda ,x
                mem[16'h1005] = 8'b10000100; // ofs0
                mem[16'h1006] = 8'ha7; // lda ,x+
                mem[16'h1007] = 8'b10000000; //
 
 
                mem[16'h1008] = 8'ha7; // lda ,x++
                mem[16'h1009] = 8'b10000001; //
                mem[16'h100a] = 8'ha6; // lda ,-x
                mem[16'h100b] = 8'b10000010; //
 
                mem[16'h100c] = 8'ha7; // lda ,--x
                mem[16'h100d] = 8'b10000011; //
 
                mem[16'h100e] = 8'ha7; // lda 0,x ofs 5
                mem[16'h100f] = 8'h00; //
 
                mem[16'h1010] = 8'ha7; // lda 0,x ofs 8
                mem[16'h1011] = 8'b10001000; //
                mem[16'h1012] = 8'h00; //
 
                mem[16'h1013] = 8'ha7; // lda 0,x ofs 16
                mem[16'h1014] = 8'b10001001; //
                mem[16'h1015] = 8'h00; //
                mem[16'h1016] = 8'h00; //
*/
 
/* test indexed load
                mem[16'h1000] = 8'h86; // lda #$02
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'h9e; // ldx $00 (direct)
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'ha6; // lda ,x
                mem[16'h1005] = 8'b10000100; // ofs0
                mem[16'h1006] = 8'ha6; // lda ,x+
                mem[16'h1007] = 8'b10000000; //
 
 
                mem[16'h1008] = 8'ha6; // lda ,x++
                mem[16'h1009] = 8'b10000001; //
                mem[16'h100a] = 8'ha6; // lda ,-x
                mem[16'h100b] = 8'b10000010; //
 
                mem[16'h100c] = 8'ha6; // lda ,--x
                mem[16'h100d] = 8'b10000011; //
 
                mem[16'h100e] = 8'ha6; // lda 0,x ofs 5
                mem[16'h100f] = 8'h00; //
 
                mem[16'h1010] = 8'ha6; // lda 0,x ofs 8
                mem[16'h1011] = 8'b10001000; //
                mem[16'h1012] = 8'h00; //
 
                mem[16'h1013] = 8'ha6; // lda 0,x ofs 16
                mem[16'h1014] = 8'b10001001; //
                mem[16'h1015] = 8'h00; //
                mem[16'h1016] = 8'h00; //
*/
 
/* test extended
                mem[16'h1000] = 8'h86; // ldb #$fe
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'hc6; // lda #$0
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'h97; // inca
                mem[16'h1005] = 8'h00; // sta $0000
                mem[16'h1006] = 8'hd7; //
                mem[16'h1007] = 8'h01; //
 
 
                mem[16'h1008] = 8'hb6; // lda $0000
                mem[16'h1009] = 8'h00; //
                mem[16'h100a] = 8'h00; //
 
                mem[16'h100b] = 8'h26; // bne$.-5
                mem[16'h100c] = 8'hf7; //
 
                mem[16'h100d] = 8'h5c; // incb
 
                mem[16'h100e] = 8'hf7; // stb $0001
                mem[16'h100f] = 8'h00; //
                mem[16'h1010] = 8'h01; //
 
                mem[16'h1011] = 8'h20; // bra
                mem[16'h1012] = 8'hec; // $.-18
*/
                mem[16'hfff0] = 8'h20; // reset
                mem[16'hfff1] = 8'h00;
                mem[16'hfff2] = 8'h20; // reset
                mem[16'hfff3] = 8'h02;
                mem[16'hfff4] = 8'h20; // reset
                mem[16'hfff5] = 8'h04;
                mem[16'hfff6] = 8'h20; // reset
                mem[16'hfff7] = 8'h06;
                mem[16'hfff8] = 8'h20; // reset
                mem[16'hfff9] = 8'h08;
                mem[16'hfffa] = 8'h20; // reset
                mem[16'hfffb] = 8'h0a;
                mem[16'hfffc] = 8'h20; // reset
                mem[16'hfffd] = 8'h0c;
                mem[16'hfffe] = 8'h10; // reset
                mem[16'hffff] = 8'h00;
`endif
        end
 
endmodule

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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [sim/] [tb_irq.v] - Blame information for rev 19

Line No.	Rev	Author	Line
1	19	ale500	`/* MC6809/HD6309 Compatible core`
2			`* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com`
3			`*`
4			`* Distributed under the terms of the Lesser GPL`
5			`*/`
6			`timescale 1ns/1ns
7
8			`module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);`
9
10			`reg clk, reset, firq, nmi,irq;`
11
12			`assign addr_o = addr;`
13			`assign data_o_o = data_o;`
14			`wire [15:0] addr;`
15			`wire [7:0] data_o, data_i;`
16			`wire oe, we;`
17			`always`
18			`#5 clk = ~clk;`
19
20			`MC6809_cpu cpu(`
21			`.cpu_clk(clk),`
22			`.cpu_reset(reset),`
23			`.cpu_we_o(we),`
24			`.cpu_oe_o(oe),`
25			`.cpu_addr_o(addr),`
26			`.cpu_data_i(data_i),`
27			`.cpu_data_o(data_o),`
28			`.cpu_irq_n(irq),`
29			`.cpu_firq_n(firq),`
30			`.cpu_nmi_n(nmi)`
31			`);`
32
33			`memory imem(addr, !oe, !we, data_i, data_o);`
34
35			`initial`
36			`begin`
37			`$dumpvars;`
38			`clk = 0;`
39			`reset = 1;`
40			`irq = 1;`
41			`firq = 1;`
42			`nmi = 1;`
43			`#0`
44			`#46`
45			`reset = 0;`
46			`#500`
47			`nmi = 0;`
48			`#22`
49			`nmi = 1;`
50			`#1000`
51			`firq = 0;`
52			`#22`
53			`firq = 1;`
54			`#1000`
55
56			`#10000`
57			`$finish;`
58			`end`
59
60			`endmodule`
61
62			`module memory(`
63			`input wire [15:0] addr,`
64			`input wire oe,`
65			`input wire we,`
66			`output wire [7:0] data_o,`
67			`input wire [7:0] data_i`
68			`);`
69
70			`reg [7:0] mem[65535:0];`
71			`reg [7:0] latecheddata;`
72			`wire [7:0] mem0, mem1, mem2, mem3;`
73
74			`assign mem0 = mem[0];`
75			`assign mem1 = mem[1];`
76			`assign mem2 = mem[2];`
77			`assign mem3 = mem[3];`
78
79			`assign data_o = latecheddata;`
80			`always @(negedge oe)`
81			`latecheddata <= mem[addr];`
82
83			`always @(negedge we)`
84			`begin`
85			`mem[addr] <= data_i;`
86			`$display("W %04x = %02x %t", addr, data_i, $time);`
87			`end`
88
89			`always @(negedge oe)`
90			`begin`
91			`$display("R %04x = %02x %t", addr, mem[addr], $time);`
92			`end`
93			`define READTESTBIN
94			`integer i;`
95			`initial`
96			`begin`
97			`ifdef READTESTBIN
98
99			`$readmemh("instructions_test.hex", mem);`
100			`$display("instructions_test.hex read");`
101			`mem[16'hfffe] = 8'h00; // setup reset`
102			`mem[16'hffff] = 8'h00;`
103			`mem[16'hfffc] = 8'h00; // nmi`
104			`mem[16'hfffd] = 8'h71;`
105			`mem[16'hfffa] = 8'h00; // swi`
106			`mem[16'hfffb] = 8'h71;`
107			`mem[16'hfff8] = 8'h00; // irq`
108			`mem[16'hfff9] = 8'h71;`
109			`mem[16'hfff6] = 8'h00; // firq`
110			`mem[16'hfff7] = 8'h71;`
111			`/*`
112			`$readmemh("monitor.hex", mem);`
113			`$display("monitor.hex read");`
114			`for (i = 0; i < 7168; i=i+1)// move monitor to its new location`
115			`begin`
116			`mem[16'he400+i] = mem[i];`
117			`mem[i] = 8'h0;`
118			`end`
119			`*/`
120			`else
121			`for (i = 0; i < 65536; i=i+1)`
122			`mem[i] = 8'ha5;`
123
124			`mem[16'h1000] = 8'h8e; // ldx #$100`
125			`mem[16'h1001] = 8'h01; //`
126			`mem[16'h1002] = 8'h00; //`
127
128			`mem[16'h1003] = 8'hbf; // stx $102`
129			`mem[16'h1004] = 8'h01; //`
130			`mem[16'h1005] = 8'h02; //`
131
132			`mem[16'h1006] = 8'h0f; // clr $10`
133			`mem[16'h1007] = 8'h10; //`
134
135			`mem[16'h1008] = 8'h7f; // clr $1234`
136			`mem[16'h1009] = 8'h12; //`
137			`mem[16'h100a] = 8'h34; //`
138
139			`mem[16'h100b] = 8'h0c; // inc $10`
140			`mem[16'h100c] = 8'h10; //`
141
142			`mem[16'h100d] = 8'h7c; // inc $1234`
143			`mem[16'h100e] = 8'h12; //`
144			`mem[16'h100f] = 8'h34; //`
145
146			`mem[16'h1010] = 8'h0a; // dec $10`
147			`mem[16'h1011] = 8'h10; //`
148
149			`mem[16'h1012] = 8'h7a; // dec $1234`
150			`mem[16'h1013] = 8'h12; //`
151			`mem[16'h1014] = 8'h34; //`
152
153			`mem[16'h1015] = 8'h20; // bra *`
154			`mem[16'h1016] = 8'hfe; //`
155
156
157
158			`/*`
159			`// test indexed store`
160			`mem[16'h1000] = 8'h86; // lda #$02`
161			`mem[16'h1001] = 8'h02; //`
162			`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
163			`mem[16'h1003] = 8'h00; //`
164
165			`mem[16'h1004] = 8'ha7; // lda ,x`
166			`mem[16'h1005] = 8'b10000100; // ofs0`
167			`mem[16'h1006] = 8'ha7; // lda ,x+`
168			`mem[16'h1007] = 8'b10000000; //`
169
170
171			`mem[16'h1008] = 8'ha7; // lda ,x++`
172			`mem[16'h1009] = 8'b10000001; //`
173			`mem[16'h100a] = 8'ha6; // lda ,-x`
174			`mem[16'h100b] = 8'b10000010; //`
175
176			`mem[16'h100c] = 8'ha7; // lda ,--x`
177			`mem[16'h100d] = 8'b10000011; //`
178
179			`mem[16'h100e] = 8'ha7; // lda 0,x ofs 5`
180			`mem[16'h100f] = 8'h00; //`
181
182			`mem[16'h1010] = 8'ha7; // lda 0,x ofs 8`
183			`mem[16'h1011] = 8'b10001000; //`
184			`mem[16'h1012] = 8'h00; //`
185
186			`mem[16'h1013] = 8'ha7; // lda 0,x ofs 16`
187			`mem[16'h1014] = 8'b10001001; //`
188			`mem[16'h1015] = 8'h00; //`
189			`mem[16'h1016] = 8'h00; //`
190			`*/`
191
192			`/* test indexed load`
193			`mem[16'h1000] = 8'h86; // lda #$02`
194			`mem[16'h1001] = 8'h02; //`
195			`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
196			`mem[16'h1003] = 8'h00; //`
197
198			`mem[16'h1004] = 8'ha6; // lda ,x`
199			`mem[16'h1005] = 8'b10000100; // ofs0`
200			`mem[16'h1006] = 8'ha6; // lda ,x+`
201			`mem[16'h1007] = 8'b10000000; //`
202
203
204			`mem[16'h1008] = 8'ha6; // lda ,x++`
205			`mem[16'h1009] = 8'b10000001; //`
206			`mem[16'h100a] = 8'ha6; // lda ,-x`
207			`mem[16'h100b] = 8'b10000010; //`
208
209			`mem[16'h100c] = 8'ha6; // lda ,--x`
210			`mem[16'h100d] = 8'b10000011; //`
211
212			`mem[16'h100e] = 8'ha6; // lda 0,x ofs 5`
213			`mem[16'h100f] = 8'h00; //`
214
215			`mem[16'h1010] = 8'ha6; // lda 0,x ofs 8`
216			`mem[16'h1011] = 8'b10001000; //`
217			`mem[16'h1012] = 8'h00; //`
218
219			`mem[16'h1013] = 8'ha6; // lda 0,x ofs 16`
220			`mem[16'h1014] = 8'b10001001; //`
221			`mem[16'h1015] = 8'h00; //`
222			`mem[16'h1016] = 8'h00; //`
223			`*/`
224
225			`/* test extended`
226			`mem[16'h1000] = 8'h86; // ldb #$fe`
227			`mem[16'h1001] = 8'h02; //`
228			`mem[16'h1002] = 8'hc6; // lda #$0`
229			`mem[16'h1003] = 8'h00; //`
230
231			`mem[16'h1004] = 8'h97; // inca`
232			`mem[16'h1005] = 8'h00; // sta $0000`
233			`mem[16'h1006] = 8'hd7; //`
234			`mem[16'h1007] = 8'h01; //`
235
236
237			`mem[16'h1008] = 8'hb6; // lda $0000`
238			`mem[16'h1009] = 8'h00; //`
239			`mem[16'h100a] = 8'h00; //`
240
241			`mem[16'h100b] = 8'h26; // bne$.-5`
242			`mem[16'h100c] = 8'hf7; //`
243
244			`mem[16'h100d] = 8'h5c; // incb`
245
246			`mem[16'h100e] = 8'hf7; // stb $0001`
247			`mem[16'h100f] = 8'h00; //`
248			`mem[16'h1010] = 8'h01; //`
249
250			`mem[16'h1011] = 8'h20; // bra`
251			`mem[16'h1012] = 8'hec; // $.-18`
252			`*/`
253			`mem[16'hfff0] = 8'h20; // reset`
254			`mem[16'hfff1] = 8'h00;`
255			`mem[16'hfff2] = 8'h20; // reset`
256			`mem[16'hfff3] = 8'h02;`
257			`mem[16'hfff4] = 8'h20; // reset`
258			`mem[16'hfff5] = 8'h04;`
259			`mem[16'hfff6] = 8'h20; // reset`
260			`mem[16'hfff7] = 8'h06;`
261			`mem[16'hfff8] = 8'h20; // reset`
262			`mem[16'hfff9] = 8'h08;`
263			`mem[16'hfffa] = 8'h20; // reset`
264			`mem[16'hfffb] = 8'h0a;`
265			`mem[16'hfffc] = 8'h20; // reset`
266			`mem[16'hfffd] = 8'h0c;`
267			`mem[16'hfffe] = 8'h10; // reset`
268			`mem[16'hffff] = 8'h00;`
269			`endif
270			`end`
271
272			`endmodule`