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#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013
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#install: C:\lscc\diamond\3.1_x64\synpbase
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#OS: Windows 7 6.1
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#Hostname: ALE-PC
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#Implementation: P6809
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$ Start of Compile
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#Wed Jul 02 14:52:21 2014
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Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
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@N:: Running Verilog Compiler in System Verilog mode
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@N:: Running Verilog Compiler in Multiple File Compilation Unit mode
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"
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@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"
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Verilog syntax check successful!
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Selecting top level module CC3_top
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":62:7:62:12|Synthesizing module logic8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":85:7:85:12|Synthesizing module arith8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":158:7:158:12|Synthesizing module shift8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":198:7:198:10|Synthesizing module alu8
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@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":241:12:241:13|No assignment to n8
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@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":241:20:241:21|No assignment to z8
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@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":302:0:302:5|Pruning register regq8[7:0]
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":129:7:129:13|Synthesizing module arith16
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":326:7:326:11|Synthesizing module alu16
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@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h
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@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":147:7:147:15|Synthesizing module decode_op
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":275:7:275:15|Synthesizing module decode_ea
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":301:7:301:16|Synthesizing module decode_alu
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":374:7:374:20|Synthesizing module test_condition
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":455:6:455:13|Ignoring system task $display
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@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1104:0:1104:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":69:11:69:23|No assignment to wire alu8_o_result
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@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:20|No assignment to wire alu8_o_CCR
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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112 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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114 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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115 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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116 |
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@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit next_mem_state[1] is always 0, optimizing ...
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118 |
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@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Register bit next_mem_state[2] is always 0, optimizing ...
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119 |
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@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bit 1 of k_mem_dest[1:0]
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122 |
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123 |
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@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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126 |
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@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO
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128 |
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129 |
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":8:7:8:12|Synthesizing module bios2k
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@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom
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134 |
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135 |
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k
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@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
|
138 |
|
|
|
139 |
|
|
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext
|
140 |
|
|
|
141 |
|
|
@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display
|
142 |
|
|
@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":167:6:167:11|System task $write is not supported yet
|
143 |
|
|
@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet
|
144 |
|
|
@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
145 |
|
|
@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
|
146 |
|
|
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
|
147 |
|
|
|
148 |
|
|
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
|
149 |
|
|
|
150 |
|
|
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
|
151 |
|
|
|
152 |
|
|
@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.
|
153 |
|
|
@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element greenr.
|
154 |
|
|
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top
|
155 |
|
|
|
156 |
|
|
@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2
|
157 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o
|
158 |
|
|
|
159 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in
|
160 |
|
|
|
161 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
|
162 |
|
|
|
163 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:23:44:29|No assignment to wire cpu1_we
|
164 |
|
|
|
165 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe
|
166 |
|
|
|
167 |
|
|
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
168 |
|
|
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
169 |
|
|
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
170 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
|
171 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
|
172 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
|
173 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
|
174 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
|
175 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
|
176 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
|
177 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
|
178 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
|
179 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
|
180 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
|
181 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
|
182 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
|
183 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
|
184 |
|
|
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":324:0:324:5|Pruning register bits 5 to 3 of next_push_state[5:0]
|
185 |
|
|
|
186 |
|
|
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
|
187 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":378:18:378:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
188 |
|
|
|
189 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":303:18:303:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
|
190 |
|
|
|
191 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":276:18:276:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
|
192 |
|
|
|
193 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
194 |
|
|
|
195 |
|
|
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
|
196 |
|
|
|
197 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
|
198 |
|
|
@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
|
199 |
|
|
|
200 |
|
|
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":199:12:199:17|Input clk_in is unused
|
201 |
|
|
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":160:18:160:21|Input b_in is unused
|
202 |
|
|
@END
|
203 |
|
|
|
204 |
|
|
At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 100MB)
|
205 |
|
|
|
206 |
|
|
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
|
207 |
|
|
# Wed Jul 02 14:52:24 2014
|
208 |
|
|
|
209 |
|
|
###########################################################]
|
210 |
|
|
Premap Report
|
211 |
|
|
|
212 |
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 800R, Built Nov 18 2013 10:58:25
|
213 |
|
|
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
214 |
|
|
Product Version I-2013.09L
|
215 |
|
|
|
216 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
217 |
|
|
|
218 |
|
|
@L: C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_scck.rpt
|
219 |
|
|
Printing clock summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_scck.rpt" file
|
220 |
|
|
@N: MF248 |Running in 64-bit mode.
|
221 |
|
|
@N: MF666 |Clock conversion enabled
|
222 |
|
|
|
223 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
|
224 |
|
|
|
225 |
|
|
|
226 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
|
227 |
|
|
|
228 |
|
|
|
229 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)
|
233 |
|
|
|
234 |
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
235 |
|
|
|
236 |
|
|
|
237 |
|
|
Clock Summary
|
238 |
|
|
**************
|
239 |
|
|
|
240 |
|
|
Start Requested Requested Clock Clock
|
241 |
|
|
Clock Frequency Period Type Group
|
242 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
243 |
|
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0
|
244 |
|
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0
|
245 |
|
|
CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0
|
246 |
|
|
======================================================================================================================
|
247 |
|
|
|
248 |
|
|
@W: MT529 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
249 |
|
|
|
250 |
|
|
Pre-mapping successful!
|
251 |
|
|
|
252 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 81MB peak: 146MB)
|
253 |
|
|
|
254 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
255 |
|
|
# Wed Jul 02 14:52:26 2014
|
256 |
|
|
|
257 |
|
|
###########################################################]
|
258 |
|
|
Map & Optimize Report
|
259 |
|
|
|
260 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25
|
261 |
|
|
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
262 |
|
|
Product Version I-2013.09L
|
263 |
|
|
|
264 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
265 |
|
|
|
266 |
|
|
@N: MF248 |Running in 64-bit mode.
|
267 |
|
|
@N: MF666 |Clock conversion enabled
|
268 |
|
|
|
269 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
270 |
|
|
|
271 |
|
|
|
272 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
273 |
|
|
|
274 |
|
|
|
275 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
|
276 |
|
|
|
277 |
|
|
|
278 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
|
279 |
|
|
|
280 |
|
|
|
281 |
|
|
|
282 |
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
Available hyper_sources - for debug and ip models
|
286 |
|
|
None Found
|
287 |
|
|
|
288 |
|
|
@N: MT206 |Auto Constrain mode is enabled
|
289 |
|
|
|
290 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
|
291 |
|
|
|
292 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
293 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
294 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
295 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
|
296 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
297 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
298 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
299 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
300 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
301 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
302 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
303 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
304 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
305 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
306 |
|
|
|
307 |
|
|
Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 176MB peak: 176MB)
|
308 |
|
|
|
309 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
310 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
311 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
312 |
|
|
|
313 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 179MB)
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 165MB peak: 183MB)
|
318 |
|
|
|
319 |
|
|
@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]
|
320 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register IY[15:0] pushed in.
|
321 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register IX[15:0] pushed in.
|
322 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register DP[7:0] pushed in.
|
323 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.
|
324 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register eflag pushed in.
|
325 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register fflag pushed in.
|
326 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register hflag pushed in.
|
327 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register intff pushed in.
|
328 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register nff pushed in.
|
329 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register zff pushed in.
|
330 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register vff pushed in.
|
331 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register cff pushed in.
|
332 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register PC[15:0] pushed in.
|
333 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.
|
334 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Register k_write_pc pushed in.
|
335 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Register k_inc_pc pushed in.
|
336 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":35:0:35:5|Register ra_in[15:0] pushed in.
|
337 |
|
|
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
338 |
|
|
|
339 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 167MB peak: 183MB)
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 168MB peak: 183MB)
|
343 |
|
|
|
344 |
|
|
|
345 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 167MB peak: 183MB)
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 167MB peak: 183MB)
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 211MB peak: 241MB)
|
352 |
|
|
|
353 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
354 |
|
|
------------------------------------------------------------
|
355 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
356 |
|
|
------------------------------------------------------------
|
357 |
|
|
1 0h:00m:16s -5.65ns 2081 / 584
|
358 |
|
|
2 0h:00m:16s -5.65ns 2081 / 584
|
359 |
|
|
3 0h:00m:16s -5.65ns 2081 / 584
|
360 |
|
|
------------------------------------------------------------
|
361 |
|
|
|
362 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[3]" with 66 loads replicated 3 times to improve timing
|
363 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[2]" with 58 loads replicated 2 times to improve timing
|
364 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[7]" with 27 loads replicated 2 times to improve timing
|
365 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[4]" with 19 loads replicated 2 times to improve timing
|
366 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[3]" with 19 loads replicated 2 times to improve timing
|
367 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[2]" with 17 loads replicated 2 times to improve timing
|
368 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[0]" with 53 loads replicated 2 times to improve timing
|
369 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[6]" with 49 loads replicated 3 times to improve timing
|
370 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[7]" with 40 loads replicated 2 times to improve timing
|
371 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[4]" with 37 loads replicated 2 times to improve timing
|
372 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[5]" with 36 loads replicated 2 times to improve timing
|
373 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[5]" with 25 loads replicated 2 times to improve timing
|
374 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[6]" with 22 loads replicated 2 times to improve timing
|
375 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_opcode[1]" with 53 loads replicated 3 times to improve timing
|
376 |
|
|
Timing driven replication report
|
377 |
|
|
Added 31 Registers via timing driven replication
|
378 |
|
|
Added 0 LUTs via timing driven replication
|
379 |
|
|
|
380 |
|
|
@N: FX271 :|Instance "cpu0.regs.IY_pipe_4" with 16 loads replicated 2 times to improve timing
|
381 |
|
|
@N: FX271 :|Instance "cpu0.regs.IX_pipe_4" with 16 loads replicated 2 times to improve timing
|
382 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[1]" with 28 loads replicated 1 times to improve timing
|
383 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[7]" with 30 loads replicated 1 times to improve timing
|
384 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[2]" with 23 loads replicated 2 times to improve timing
|
385 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[0]" with 22 loads replicated 1 times to improve timing
|
386 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[0]" with 19 loads replicated 2 times to improve timing
|
387 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_postbyte[1]" with 18 loads replicated 1 times to improve timing
|
388 |
|
|
Added 12 Registers via timing driven replication
|
389 |
|
|
Added 0 LUTs via timing driven replication
|
390 |
|
|
|
391 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[3]" with 9 loads replicated 1 times to improve timing
|
392 |
|
|
@N: FX271 :|Instance "cpu0.regs.IX_pipe_1" with 16 loads replicated 2 times to improve timing
|
393 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.state[3]" with 61 loads replicated 2 times to improve timing
|
394 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":324:0:324:5|Instance "cpu0.k_ind_ea[6]" with 37 loads replicated 3 times to improve timing
|
395 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":35:0:35:5|Instance "cpu0.alu.rop_in[1]" with 59 loads replicated 2 times to improve timing
|
396 |
|
|
Added 10 Registers via timing driven replication
|
397 |
|
|
Added 2 LUTs via timing driven replication
|
398 |
|
|
|
399 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
400 |
|
|
------------------------------------------------------------
|
401 |
|
|
1 0h:00m:18s -2.91ns 2131 / 637
|
402 |
|
|
2 0h:00m:18s -2.91ns 2133 / 637
|
403 |
|
|
3 0h:00m:18s -3.31ns 2134 / 637
|
404 |
|
|
4 0h:00m:18s -2.91ns 2133 / 637
|
405 |
|
|
5 0h:00m:18s -2.91ns 2134 / 637
|
406 |
|
|
------------------------------------------------------------
|
407 |
|
|
|
408 |
|
|
@N: FX271 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":64:10:64:33|Instance "textctrl.vsync_cnt_2_sqmuxa_i_0_o3" with 44 loads replicated 1 times to improve timing
|
409 |
|
|
Added 0 Registers via timing driven replication
|
410 |
|
|
Added 1 LUTs via timing driven replication
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
414 |
|
|
------------------------------------------------------------
|
415 |
|
|
1 0h:00m:18s -2.95ns 2131 / 637
|
416 |
|
|
------------------------------------------------------------
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 183MB peak: 241MB)
|
420 |
|
|
|
421 |
|
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
422 |
|
|
|
423 |
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 185MB peak: 241MB)
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
428 |
|
|
|
429 |
|
|
1 non-gated/non-generated clock tree(s) driving 653 clock pin(s) of sequential element(s)
|
430 |
|
|
|
431 |
|
|
310 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
432 |
|
|
|
433 |
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
434 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
435 |
|
|
---------------------------------------------------------------------------------------
|
436 |
|
|
@K:CKID0001 clk40_i port 653 cpu_clk
|
437 |
|
|
=======================================================================================
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
441 |
|
|
|
442 |
|
|
Writing Analyst data base C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809.srm
|
443 |
|
|
|
444 |
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:20s; Memory used current: 186MB peak: 241MB)
|
445 |
|
|
|
446 |
|
|
Writing EDIF Netlist and constraint files
|
447 |
|
|
@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotated
|
448 |
|
|
I-2013.09L
|
449 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
450 |
|
|
|
451 |
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 191MB peak: 241MB)
|
452 |
|
|
|
453 |
|
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 13.64ns. Please declare a user-defined clock on object "p:clk40_i"
|
454 |
|
|
|
455 |
|
|
Found clock CC3_top|cpu_clk_derived_clock with period 13.64ns
|
456 |
|
|
|
457 |
|
|
|
458 |
|
|
##### START OF TIMING REPORT #####[
|
459 |
|
|
# Timing Report written on Wed Jul 02 14:52:48 2014
|
460 |
|
|
#
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
Top view: CC3_top
|
464 |
|
|
Requested Frequency: 73.3 MHz
|
465 |
|
|
Wire load mode: top
|
466 |
|
|
Paths requested: 5
|
467 |
|
|
Constraint File(s):
|
468 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
469 |
|
|
|
470 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
471 |
|
|
|
472 |
|
|
|
473 |
|
|
|
474 |
|
|
Performance Summary
|
475 |
|
|
*******************
|
476 |
|
|
|
477 |
|
|
|
478 |
|
|
Worst slack in design: -2.407
|
479 |
|
|
|
480 |
|
|
Requested Estimated Requested Estimated Clock Clock
|
481 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
482 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
483 |
|
|
CC3_top|clk40_i 73.3 MHz 62.3 MHz 13.639 16.046 -2.407 inferred Autoconstr_clkgroup_0
|
484 |
|
|
=========================================================================================================================
|
485 |
|
|
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
|
490 |
|
|
Clock Relationships
|
491 |
|
|
*******************
|
492 |
|
|
|
493 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
494 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
495 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
496 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
497 |
|
|
CC3_top|clk40_i CC3_top|clk40_i | 13.639 -2.407 | No paths - | No paths - | No paths -
|
498 |
|
|
=========================================================================================================================
|
499 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
500 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
501 |
|
|
|
502 |
|
|
|
503 |
|
|
|
504 |
|
|
Interface Information
|
505 |
|
|
*********************
|
506 |
|
|
|
507 |
|
|
No IO constraint found
|
508 |
|
|
|
509 |
|
|
|
510 |
|
|
|
511 |
|
|
====================================
|
512 |
|
|
Detailed Report for Clock: CC3_top|clk40_i
|
513 |
|
|
====================================
|
514 |
|
|
|
515 |
|
|
|
516 |
|
|
|
517 |
|
|
Starting Points with Worst Slack
|
518 |
|
|
********************************
|
519 |
|
|
|
520 |
|
|
Starting Arrival
|
521 |
|
|
Instance Reference Type Pin Net Time Slack
|
522 |
|
|
Clock
|
523 |
|
|
-------------------------------------------------------------------------------------------------------------
|
524 |
|
|
cpu0.regs.IX_pipe_4_fast CC3_top|clk40_i FD1P3AX Q IX_0_sqmuxaf_fast 1.108 -2.407
|
525 |
|
|
cpu0.regs.IX_pipe_77 CC3_top|clk40_i FD1P3AX Q left_1f_0[0] 0.972 -2.271
|
526 |
|
|
cpu0.regs.IX_pipe_78 CC3_top|clk40_i FD1P3AX Q ea_reg_postf_0[0] 0.972 -2.271
|
527 |
|
|
cpu0.k_ind_ea_fast[1] CC3_top|clk40_i FD1P3AX Q k_ind_ea_fast[1] 1.180 -2.166
|
528 |
|
|
cpu0.k_ind_ea_fast[0] CC3_top|clk40_i FD1P3AX Q k_ind_ea_fast[0] 1.148 -2.134
|
529 |
|
|
cpu0.regs.IY_pipe_4_fast CC3_top|clk40_i FD1P3AX Q IY_1_sqmuxaf_fast 1.148 -2.096
|
530 |
|
|
cpu0.k_ind_ea_fast[2] CC3_top|clk40_i FD1P3AX Q k_ind_ea_fast[2] 1.044 -2.030
|
531 |
|
|
cpu0.regs.IX_pipe_4_rep1 CC3_top|clk40_i FD1P3AX Q IX_0_sqmuxaf_rep1 1.180 -1.985
|
532 |
|
|
cpu0.regs.IY_pipe_4_rep1 CC3_top|clk40_i FD1P3AX Q IY_1_sqmuxaf_rep1 1.180 -1.985
|
533 |
|
|
cpu0.regs.IX_pipe_67 CC3_top|clk40_i FD1P3AX Q left_1f_0[2] 0.972 -1.920
|
534 |
|
|
=============================================================================================================
|
535 |
|
|
|
536 |
|
|
|
537 |
|
|
Ending Points with Worst Slack
|
538 |
|
|
******************************
|
539 |
|
|
|
540 |
|
|
Starting Required
|
541 |
|
|
Instance Reference Type Pin Net Time Slack
|
542 |
|
|
Clock
|
543 |
|
|
----------------------------------------------------------------------------------------------
|
544 |
|
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_lm[13] 13.728 -2.407
|
545 |
|
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_lm[13] 13.728 -2.407
|
546 |
|
|
cpu0.regs.SS[7] CC3_top|clk40_i FD1P3AX D SS_lm[7] 13.728 -1.555
|
547 |
|
|
cpu0.regs.SU[7] CC3_top|clk40_i FD1P3AX D SU_lm[7] 13.728 -1.555
|
548 |
|
|
cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_lm[10] 13.728 -1.553
|
549 |
|
|
cpu0.regs.SU[10] CC3_top|clk40_i FD1P3AX D SU_lm[10] 13.728 -1.553
|
550 |
|
|
cpu0.regs.SS[9] CC3_top|clk40_i FD1P3AX D SS_lm[9] 13.728 -1.299
|
551 |
|
|
cpu0.regs.SU[9] CC3_top|clk40_i FD1P3AX D SU_lm[9] 13.728 -1.299
|
552 |
|
|
cpu0.regs.SS[6] CC3_top|clk40_i FD1P3AX D SS_lm[6] 13.728 -1.204
|
553 |
|
|
cpu0.regs.SU[6] CC3_top|clk40_i FD1P3AX D SU_lm[6] 13.728 -1.204
|
554 |
|
|
==============================================================================================
|
555 |
|
|
|
556 |
|
|
|
557 |
|
|
|
558 |
|
|
Worst Path Information
|
559 |
|
|
***********************
|
560 |
|
|
|
561 |
|
|
|
562 |
|
|
Path information for path number 1:
|
563 |
|
|
Requested Period: 13.639
|
564 |
|
|
- Setup time: -0.089
|
565 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
566 |
|
|
= Required time: 13.728
|
567 |
|
|
|
568 |
|
|
- Propagation time: 16.134
|
569 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
570 |
|
|
= Slack (critical) : -2.407
|
571 |
|
|
|
572 |
|
|
Number of logic level(s): 20
|
573 |
|
|
Starting point: cpu0.regs.IX_pipe_4_fast / Q
|
574 |
|
|
Ending point: cpu0.regs.SS[13] / D
|
575 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
576 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
577 |
|
|
|
578 |
|
|
Instance / Net Pin Pin Arrival No. of
|
579 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
580 |
|
|
--------------------------------------------------------------------------------------------------------
|
581 |
|
|
cpu0.regs.IX_pipe_4_fast FD1P3AX Q Out 1.108 1.108 -
|
582 |
|
|
IX_0_sqmuxaf_fast Net - - - - 3
|
583 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 A In 0.000 1.108 -
|
584 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 2.125 -
|
585 |
|
|
N_631 Net - - - - 1
|
586 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 2.125 -
|
587 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.277 -
|
588 |
|
|
IX[0] Net - - - - 3
|
589 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.277 -
|
590 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.294 -
|
591 |
|
|
ea_reg_3_am[0] Net - - - - 1
|
592 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.294 -
|
593 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.716 -
|
594 |
|
|
ea_reg[0] Net - - - - 5
|
595 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.716 -
|
596 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.805 -
|
597 |
|
|
N_72 Net - - - - 2
|
598 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.805 -
|
599 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.350 -
|
600 |
|
|
eamem_addr_o_cry_0 Net - - - - 1
|
601 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.350 -
|
602 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.492 -
|
603 |
|
|
eamem_addr_o_cry_2 Net - - - - 1
|
604 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.492 -
|
605 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.635 -
|
606 |
|
|
eamem_addr_o_cry_4 Net - - - - 1
|
607 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.635 -
|
608 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.778 -
|
609 |
|
|
eamem_addr_o_cry_6 Net - - - - 1
|
610 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.778 -
|
611 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.921 -
|
612 |
|
|
eamem_addr_o_cry_8 Net - - - - 1
|
613 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.921 -
|
614 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 8.064 -
|
615 |
|
|
eamem_addr_o_cry_10 Net - - - - 1
|
616 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 8.064 -
|
617 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.207 -
|
618 |
|
|
eamem_addr_o_cry_12 Net - - - - 1
|
619 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.207 -
|
620 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.931 -
|
621 |
|
|
regs_o_eamem_addr[13] Net - - - - 4
|
622 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.931 -
|
623 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.948 -
|
624 |
|
|
datamux_o_dest_6[13] Net - - - - 1
|
625 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.948 -
|
626 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.965 -
|
627 |
|
|
datamux_o_dest_am[13] Net - - - - 1
|
628 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.965 -
|
629 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.251 -
|
630 |
|
|
datamux_o_dest[13] Net - - - - 2
|
631 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.251 -
|
632 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.484 -
|
633 |
|
|
left_1[13] Net - - - - 6
|
634 |
|
|
cpu0.regs.SS_16_0[13] ORCALUT4 B In 0.000 13.484 -
|
635 |
|
|
cpu0.regs.SS_16_0[13] ORCALUT4 Z Out 1.017 14.501 -
|
636 |
|
|
N_258 Net - - - - 1
|
637 |
|
|
cpu0.regs.SS_16[13] ORCALUT4 A In 0.000 14.501 -
|
638 |
|
|
cpu0.regs.SS_16[13] ORCALUT4 Z Out 1.017 15.518 -
|
639 |
|
|
SS_16[13] Net - - - - 1
|
640 |
|
|
cpu0.regs.SS_lm_0[13] ORCALUT4 A In 0.000 15.518 -
|
641 |
|
|
cpu0.regs.SS_lm_0[13] ORCALUT4 Z Out 0.617 16.134 -
|
642 |
|
|
SS_lm[13] Net - - - - 1
|
643 |
|
|
cpu0.regs.SS[13] FD1P3AX D In 0.000 16.134 -
|
644 |
|
|
========================================================================================================
|
645 |
|
|
|
646 |
|
|
|
647 |
|
|
Path information for path number 2:
|
648 |
|
|
Requested Period: 13.639
|
649 |
|
|
- Setup time: -0.089
|
650 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
651 |
|
|
= Required time: 13.728
|
652 |
|
|
|
653 |
|
|
- Propagation time: 16.134
|
654 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
655 |
|
|
= Slack (critical) : -2.407
|
656 |
|
|
|
657 |
|
|
Number of logic level(s): 20
|
658 |
|
|
Starting point: cpu0.regs.IX_pipe_4_fast / Q
|
659 |
|
|
Ending point: cpu0.regs.SU[13] / D
|
660 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
661 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
662 |
|
|
|
663 |
|
|
Instance / Net Pin Pin Arrival No. of
|
664 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
665 |
|
|
--------------------------------------------------------------------------------------------------------
|
666 |
|
|
cpu0.regs.IX_pipe_4_fast FD1P3AX Q Out 1.108 1.108 -
|
667 |
|
|
IX_0_sqmuxaf_fast Net - - - - 3
|
668 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 A In 0.000 1.108 -
|
669 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 2.125 -
|
670 |
|
|
N_631 Net - - - - 1
|
671 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 2.125 -
|
672 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.277 -
|
673 |
|
|
IX[0] Net - - - - 3
|
674 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.277 -
|
675 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.294 -
|
676 |
|
|
ea_reg_3_am[0] Net - - - - 1
|
677 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.294 -
|
678 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.716 -
|
679 |
|
|
ea_reg[0] Net - - - - 5
|
680 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.716 -
|
681 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.805 -
|
682 |
|
|
N_72 Net - - - - 2
|
683 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.805 -
|
684 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.350 -
|
685 |
|
|
eamem_addr_o_cry_0 Net - - - - 1
|
686 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.350 -
|
687 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.492 -
|
688 |
|
|
eamem_addr_o_cry_2 Net - - - - 1
|
689 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.492 -
|
690 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.635 -
|
691 |
|
|
eamem_addr_o_cry_4 Net - - - - 1
|
692 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.635 -
|
693 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.778 -
|
694 |
|
|
eamem_addr_o_cry_6 Net - - - - 1
|
695 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.778 -
|
696 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.921 -
|
697 |
|
|
eamem_addr_o_cry_8 Net - - - - 1
|
698 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.921 -
|
699 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 8.064 -
|
700 |
|
|
eamem_addr_o_cry_10 Net - - - - 1
|
701 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 8.064 -
|
702 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.207 -
|
703 |
|
|
eamem_addr_o_cry_12 Net - - - - 1
|
704 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.207 -
|
705 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.931 -
|
706 |
|
|
regs_o_eamem_addr[13] Net - - - - 4
|
707 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.931 -
|
708 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.948 -
|
709 |
|
|
datamux_o_dest_6[13] Net - - - - 1
|
710 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.948 -
|
711 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.965 -
|
712 |
|
|
datamux_o_dest_am[13] Net - - - - 1
|
713 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.965 -
|
714 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.251 -
|
715 |
|
|
datamux_o_dest[13] Net - - - - 2
|
716 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.251 -
|
717 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.484 -
|
718 |
|
|
left_1[13] Net - - - - 6
|
719 |
|
|
cpu0.regs.SU_16_0[13] ORCALUT4 B In 0.000 13.484 -
|
720 |
|
|
cpu0.regs.SU_16_0[13] ORCALUT4 Z Out 1.017 14.501 -
|
721 |
|
|
N_294 Net - - - - 1
|
722 |
|
|
cpu0.regs.SU_16[13] ORCALUT4 A In 0.000 14.501 -
|
723 |
|
|
cpu0.regs.SU_16[13] ORCALUT4 Z Out 1.017 15.518 -
|
724 |
|
|
SU_16[13] Net - - - - 1
|
725 |
|
|
cpu0.regs.SU_lm_0[13] ORCALUT4 A In 0.000 15.518 -
|
726 |
|
|
cpu0.regs.SU_lm_0[13] ORCALUT4 Z Out 0.617 16.134 -
|
727 |
|
|
SU_lm[13] Net - - - - 1
|
728 |
|
|
cpu0.regs.SU[13] FD1P3AX D In 0.000 16.134 -
|
729 |
|
|
========================================================================================================
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
Path information for path number 3:
|
733 |
|
|
Requested Period: 13.639
|
734 |
|
|
- Setup time: -0.089
|
735 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
736 |
|
|
= Required time: 13.728
|
737 |
|
|
|
738 |
|
|
- Propagation time: 15.999
|
739 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
740 |
|
|
= Slack (non-critical) : -2.271
|
741 |
|
|
|
742 |
|
|
Number of logic level(s): 20
|
743 |
|
|
Starting point: cpu0.regs.IX_pipe_77 / Q
|
744 |
|
|
Ending point: cpu0.regs.SS[13] / D
|
745 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
746 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
747 |
|
|
|
748 |
|
|
Instance / Net Pin Pin Arrival No. of
|
749 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
750 |
|
|
--------------------------------------------------------------------------------------------------------
|
751 |
|
|
cpu0.regs.IX_pipe_77 FD1P3AX Q Out 0.972 0.972 -
|
752 |
|
|
left_1f_0[0] Net - - - - 1
|
753 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 C In 0.000 0.972 -
|
754 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 1.989 -
|
755 |
|
|
N_631 Net - - - - 1
|
756 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 1.989 -
|
757 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.141 -
|
758 |
|
|
IX[0] Net - - - - 3
|
759 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.141 -
|
760 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.158 -
|
761 |
|
|
ea_reg_3_am[0] Net - - - - 1
|
762 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.158 -
|
763 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.580 -
|
764 |
|
|
ea_reg[0] Net - - - - 5
|
765 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.580 -
|
766 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.669 -
|
767 |
|
|
N_72 Net - - - - 2
|
768 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.669 -
|
769 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.214 -
|
770 |
|
|
eamem_addr_o_cry_0 Net - - - - 1
|
771 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.214 -
|
772 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.356 -
|
773 |
|
|
eamem_addr_o_cry_2 Net - - - - 1
|
774 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.356 -
|
775 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.499 -
|
776 |
|
|
eamem_addr_o_cry_4 Net - - - - 1
|
777 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.499 -
|
778 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.642 -
|
779 |
|
|
eamem_addr_o_cry_6 Net - - - - 1
|
780 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.642 -
|
781 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.785 -
|
782 |
|
|
eamem_addr_o_cry_8 Net - - - - 1
|
783 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.785 -
|
784 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 7.928 -
|
785 |
|
|
eamem_addr_o_cry_10 Net - - - - 1
|
786 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 7.928 -
|
787 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.070 -
|
788 |
|
|
eamem_addr_o_cry_12 Net - - - - 1
|
789 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.070 -
|
790 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.796 -
|
791 |
|
|
regs_o_eamem_addr[13] Net - - - - 4
|
792 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.796 -
|
793 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.812 -
|
794 |
|
|
datamux_o_dest_6[13] Net - - - - 1
|
795 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.812 -
|
796 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.829 -
|
797 |
|
|
datamux_o_dest_am[13] Net - - - - 1
|
798 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.829 -
|
799 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.115 -
|
800 |
|
|
datamux_o_dest[13] Net - - - - 2
|
801 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.115 -
|
802 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.348 -
|
803 |
|
|
left_1[13] Net - - - - 6
|
804 |
|
|
cpu0.regs.SS_16_0[13] ORCALUT4 B In 0.000 13.348 -
|
805 |
|
|
cpu0.regs.SS_16_0[13] ORCALUT4 Z Out 1.017 14.365 -
|
806 |
|
|
N_258 Net - - - - 1
|
807 |
|
|
cpu0.regs.SS_16[13] ORCALUT4 A In 0.000 14.365 -
|
808 |
|
|
cpu0.regs.SS_16[13] ORCALUT4 Z Out 1.017 15.382 -
|
809 |
|
|
SS_16[13] Net - - - - 1
|
810 |
|
|
cpu0.regs.SS_lm_0[13] ORCALUT4 A In 0.000 15.382 -
|
811 |
|
|
cpu0.regs.SS_lm_0[13] ORCALUT4 Z Out 0.617 15.999 -
|
812 |
|
|
SS_lm[13] Net - - - - 1
|
813 |
|
|
cpu0.regs.SS[13] FD1P3AX D In 0.000 15.999 -
|
814 |
|
|
========================================================================================================
|
815 |
|
|
|
816 |
|
|
|
817 |
|
|
Path information for path number 4:
|
818 |
|
|
Requested Period: 13.639
|
819 |
|
|
- Setup time: -0.089
|
820 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
821 |
|
|
= Required time: 13.728
|
822 |
|
|
|
823 |
|
|
- Propagation time: 15.999
|
824 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
825 |
|
|
= Slack (non-critical) : -2.271
|
826 |
|
|
|
827 |
|
|
Number of logic level(s): 20
|
828 |
|
|
Starting point: cpu0.regs.IX_pipe_78 / Q
|
829 |
|
|
Ending point: cpu0.regs.SS[13] / D
|
830 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
831 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
832 |
|
|
|
833 |
|
|
Instance / Net Pin Pin Arrival No. of
|
834 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
835 |
|
|
--------------------------------------------------------------------------------------------------------
|
836 |
|
|
cpu0.regs.IX_pipe_78 FD1P3AX Q Out 0.972 0.972 -
|
837 |
|
|
ea_reg_postf_0[0] Net - - - - 1
|
838 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 B In 0.000 0.972 -
|
839 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 1.989 -
|
840 |
|
|
N_631 Net - - - - 1
|
841 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 1.989 -
|
842 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.141 -
|
843 |
|
|
IX[0] Net - - - - 3
|
844 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.141 -
|
845 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.158 -
|
846 |
|
|
ea_reg_3_am[0] Net - - - - 1
|
847 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.158 -
|
848 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.580 -
|
849 |
|
|
ea_reg[0] Net - - - - 5
|
850 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.580 -
|
851 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.669 -
|
852 |
|
|
N_72 Net - - - - 2
|
853 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.669 -
|
854 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.214 -
|
855 |
|
|
eamem_addr_o_cry_0 Net - - - - 1
|
856 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.214 -
|
857 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.356 -
|
858 |
|
|
eamem_addr_o_cry_2 Net - - - - 1
|
859 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.356 -
|
860 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.499 -
|
861 |
|
|
eamem_addr_o_cry_4 Net - - - - 1
|
862 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.499 -
|
863 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.642 -
|
864 |
|
|
eamem_addr_o_cry_6 Net - - - - 1
|
865 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.642 -
|
866 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.785 -
|
867 |
|
|
eamem_addr_o_cry_8 Net - - - - 1
|
868 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.785 -
|
869 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 7.928 -
|
870 |
|
|
eamem_addr_o_cry_10 Net - - - - 1
|
871 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 7.928 -
|
872 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.070 -
|
873 |
|
|
eamem_addr_o_cry_12 Net - - - - 1
|
874 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.070 -
|
875 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.796 -
|
876 |
|
|
regs_o_eamem_addr[13] Net - - - - 4
|
877 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.796 -
|
878 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.812 -
|
879 |
|
|
datamux_o_dest_6[13] Net - - - - 1
|
880 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.812 -
|
881 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.829 -
|
882 |
|
|
datamux_o_dest_am[13] Net - - - - 1
|
883 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.829 -
|
884 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.115 -
|
885 |
|
|
datamux_o_dest[13] Net - - - - 2
|
886 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.115 -
|
887 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.348 -
|
888 |
|
|
left_1[13] Net - - - - 6
|
889 |
|
|
cpu0.regs.SS_16_0[13] ORCALUT4 B In 0.000 13.348 -
|
890 |
|
|
cpu0.regs.SS_16_0[13] ORCALUT4 Z Out 1.017 14.365 -
|
891 |
|
|
N_258 Net - - - - 1
|
892 |
|
|
cpu0.regs.SS_16[13] ORCALUT4 A In 0.000 14.365 -
|
893 |
|
|
cpu0.regs.SS_16[13] ORCALUT4 Z Out 1.017 15.382 -
|
894 |
|
|
SS_16[13] Net - - - - 1
|
895 |
|
|
cpu0.regs.SS_lm_0[13] ORCALUT4 A In 0.000 15.382 -
|
896 |
|
|
cpu0.regs.SS_lm_0[13] ORCALUT4 Z Out 0.617 15.999 -
|
897 |
|
|
SS_lm[13] Net - - - - 1
|
898 |
|
|
cpu0.regs.SS[13] FD1P3AX D In 0.000 15.999 -
|
899 |
|
|
========================================================================================================
|
900 |
|
|
|
901 |
|
|
|
902 |
|
|
Path information for path number 5:
|
903 |
|
|
Requested Period: 13.639
|
904 |
|
|
- Setup time: -0.089
|
905 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
906 |
|
|
= Required time: 13.728
|
907 |
|
|
|
908 |
|
|
- Propagation time: 15.999
|
909 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
910 |
|
|
= Slack (non-critical) : -2.271
|
911 |
|
|
|
912 |
|
|
Number of logic level(s): 20
|
913 |
|
|
Starting point: cpu0.regs.IX_pipe_77 / Q
|
914 |
|
|
Ending point: cpu0.regs.SU[13] / D
|
915 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
916 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
917 |
|
|
|
918 |
|
|
Instance / Net Pin Pin Arrival No. of
|
919 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
920 |
|
|
--------------------------------------------------------------------------------------------------------
|
921 |
|
|
cpu0.regs.IX_pipe_77 FD1P3AX Q Out 0.972 0.972 -
|
922 |
|
|
left_1f_0[0] Net - - - - 1
|
923 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 C In 0.000 0.972 -
|
924 |
|
|
cpu0.regs.IX_10_0[0] ORCALUT4 Z Out 1.017 1.989 -
|
925 |
|
|
N_631 Net - - - - 1
|
926 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 B In 0.000 1.989 -
|
927 |
|
|
cpu0.regs.IX_10[0] ORCALUT4 Z Out 1.153 3.141 -
|
928 |
|
|
IX[0] Net - - - - 3
|
929 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 B In 0.000 3.141 -
|
930 |
|
|
cpu0.regs.ea.ea_reg_3_am[0] ORCALUT4 Z Out 1.017 4.158 -
|
931 |
|
|
ea_reg_3_am[0] Net - - - - 1
|
932 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX BLUT In 0.000 4.158 -
|
933 |
|
|
cpu0.regs.ea.ea_reg_3[0] PFUMX Z Out 0.422 4.580 -
|
934 |
|
|
ea_reg[0] Net - - - - 5
|
935 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 A In 0.000 4.580 -
|
936 |
|
|
cpu0.regs.ea.un1_pc_0[0] ORCALUT4 Z Out 1.089 5.669 -
|
937 |
|
|
N_72 Net - - - - 2
|
938 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D C1 In 0.000 5.669 -
|
939 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_0_0 CCU2D COUT Out 1.545 7.214 -
|
940 |
|
|
eamem_addr_o_cry_0 Net - - - - 1
|
941 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D CIN In 0.000 7.214 -
|
942 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_1_0 CCU2D COUT Out 0.143 7.356 -
|
943 |
|
|
eamem_addr_o_cry_2 Net - - - - 1
|
944 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D CIN In 0.000 7.356 -
|
945 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_3_0 CCU2D COUT Out 0.143 7.499 -
|
946 |
|
|
eamem_addr_o_cry_4 Net - - - - 1
|
947 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D CIN In 0.000 7.499 -
|
948 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_5_0 CCU2D COUT Out 0.143 7.642 -
|
949 |
|
|
eamem_addr_o_cry_6 Net - - - - 1
|
950 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D CIN In 0.000 7.642 -
|
951 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_7_0 CCU2D COUT Out 0.143 7.785 -
|
952 |
|
|
eamem_addr_o_cry_8 Net - - - - 1
|
953 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D CIN In 0.000 7.785 -
|
954 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_9_0 CCU2D COUT Out 0.143 7.928 -
|
955 |
|
|
eamem_addr_o_cry_10 Net - - - - 1
|
956 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D CIN In 0.000 7.928 -
|
957 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_11_0 CCU2D COUT Out 0.143 8.070 -
|
958 |
|
|
eamem_addr_o_cry_12 Net - - - - 1
|
959 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D CIN In 0.000 8.070 -
|
960 |
|
|
cpu0.regs.ea.eamem_addr_o_cry_13_0 CCU2D S0 Out 1.725 9.796 -
|
961 |
|
|
regs_o_eamem_addr[13] Net - - - - 4
|
962 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 D In 0.000 9.796 -
|
963 |
|
|
cpu0.regs.ea.datamux_o_dest_6[13] ORCALUT4 Z Out 1.017 10.812 -
|
964 |
|
|
datamux_o_dest_6[13] Net - - - - 1
|
965 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 B In 0.000 10.812 -
|
966 |
|
|
cpu0.regs.ea.datamux_o_dest_am[13] ORCALUT4 Z Out 1.017 11.829 -
|
967 |
|
|
datamux_o_dest_am[13] Net - - - - 1
|
968 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX BLUT In 0.000 11.829 -
|
969 |
|
|
cpu0.regs.ea.datamux_o_dest[13] PFUMX Z Out 0.286 12.115 -
|
970 |
|
|
datamux_o_dest[13] Net - - - - 2
|
971 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 B In 0.000 12.115 -
|
972 |
|
|
cpu0.regs.path_left_data_RNIRO271[13] ORCALUT4 Z Out 1.233 13.348 -
|
973 |
|
|
left_1[13] Net - - - - 6
|
974 |
|
|
cpu0.regs.SU_16_0[13] ORCALUT4 B In 0.000 13.348 -
|
975 |
|
|
cpu0.regs.SU_16_0[13] ORCALUT4 Z Out 1.017 14.365 -
|
976 |
|
|
N_294 Net - - - - 1
|
977 |
|
|
cpu0.regs.SU_16[13] ORCALUT4 A In 0.000 14.365 -
|
978 |
|
|
cpu0.regs.SU_16[13] ORCALUT4 Z Out 1.017 15.382 -
|
979 |
|
|
SU_16[13] Net - - - - 1
|
980 |
|
|
cpu0.regs.SU_lm_0[13] ORCALUT4 A In 0.000 15.382 -
|
981 |
|
|
cpu0.regs.SU_lm_0[13] ORCALUT4 Z Out 0.617 15.999 -
|
982 |
|
|
SU_lm[13] Net - - - - 1
|
983 |
|
|
cpu0.regs.SU[13] FD1P3AX D In 0.000 15.999 -
|
984 |
|
|
========================================================================================================
|
985 |
|
|
|
986 |
|
|
|
987 |
|
|
|
988 |
|
|
##### END OF TIMING REPORT #####]
|
989 |
|
|
|
990 |
|
|
---------------------------------------
|
991 |
|
|
Resource Usage Report
|
992 |
|
|
Part: lcmxo2_7000he-4
|
993 |
|
|
|
994 |
|
|
Register bits: 637 of 6864 (9%)
|
995 |
|
|
PIC Latch: 0
|
996 |
|
|
I/O cells: 69
|
997 |
|
|
Block Rams : 10 of 26 (38%)
|
998 |
|
|
|
999 |
|
|
|
1000 |
|
|
Details:
|
1001 |
|
|
BB: 8
|
1002 |
|
|
CCU2D: 181
|
1003 |
|
|
DP8KC: 10
|
1004 |
|
|
FD1P3AX: 580
|
1005 |
|
|
FD1P3DX: 8
|
1006 |
|
|
FD1S3AX: 37
|
1007 |
|
|
FD1S3IX: 2
|
1008 |
|
|
GSR: 1
|
1009 |
|
|
IB: 1
|
1010 |
|
|
INV: 3
|
1011 |
|
|
L6MUX21: 20
|
1012 |
|
|
OB: 60
|
1013 |
|
|
OFS1P3DX: 9
|
1014 |
|
|
OFS1P3IX: 1
|
1015 |
|
|
ORCALUT4: 2122
|
1016 |
|
|
PFUMX: 255
|
1017 |
|
|
PUR: 1
|
1018 |
|
|
VHI: 14
|
1019 |
|
|
VLO: 20
|
1020 |
|
|
Mapper successful!
|
1021 |
|
|
|
1022 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 61MB peak: 241MB)
|
1023 |
|
|
|
1024 |
|
|
Process took 0h:00m:21s realtime, 0h:00m:21s cputime
|
1025 |
|
|
# Wed Jul 02 14:52:48 2014
|
1026 |
|
|
|
1027 |
|
|
###########################################################]
|