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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Sun Dec 29 07:16:27 2013
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@N:: Running Verilog Compiler in System Verilog mode
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@N:: Running Verilog Compiler in Multiple File Compilation Unit mode
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
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@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
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Verilog syntax check successful!
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":13:7:13:11|Synthesizing module alu16
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":493:0:493:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":213:0:213:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":108:7:108:15|Synthesizing module decode_op
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":236:7:236:15|Synthesizing module decode_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":262:7:262:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":334:7:334:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":390:6:390:13|Ignoring system task $display
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":946:0:946:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_pull_reg_write -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_postbyte0[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_new_pc[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit k_mem_dest[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit next_mem_state[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
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@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Pruning register bits 5 to 2 of next_push_state[5:0]
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":338:18:338:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":264:18:264:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":237:18:237:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
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@END
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Dec 29 07:16:28 2013
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###########################################################]
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Premap Report
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
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Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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Product Version G-2012.09L-SP1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
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| 134 |
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|
|
| 135 |
|
|
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_scck.rpt
|
| 136 |
|
|
Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_scck.rpt" file
|
| 137 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 138 |
|
|
@N: MF666 |Clock conversion enabled
|
| 139 |
|
|
|
| 140 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 93MB peak: 94MB)
|
| 141 |
|
|
|
| 142 |
|
|
|
| 143 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)
|
| 144 |
|
|
|
| 145 |
|
|
|
| 146 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
|
| 147 |
|
|
|
| 148 |
|
|
|
| 149 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)
|
| 150 |
|
|
|
| 151 |
|
|
|
| 152 |
|
|
|
| 153 |
|
|
Clock Summary
|
| 154 |
|
|
**************
|
| 155 |
|
|
|
| 156 |
|
|
Start Requested Requested Clock Clock
|
| 157 |
|
|
Clock Frequency Period Type Group
|
| 158 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
| 159 |
|
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0
|
| 160 |
|
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Autoconstr_clkgroup_0
|
| 161 |
|
|
======================================================================================================================
|
| 162 |
|
|
|
| 163 |
|
|
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
| 164 |
|
|
|
| 165 |
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
| 166 |
|
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
| 167 |
|
|
|
| 168 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 135MB)
|
| 169 |
|
|
|
| 170 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 171 |
|
|
# Sun Dec 29 07:16:30 2013
|
| 172 |
|
|
|
| 173 |
|
|
###########################################################]
|
| 174 |
|
|
Map & Optimize Report
|
| 175 |
|
|
|
| 176 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
| 177 |
|
|
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
| 178 |
|
|
Product Version G-2012.09L-SP1
|
| 179 |
|
|
|
| 180 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 181 |
|
|
|
| 182 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 183 |
|
|
@N: MF666 |Clock conversion enabled
|
| 184 |
|
|
|
| 185 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 186 |
|
|
|
| 187 |
|
|
|
| 188 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
| 189 |
|
|
|
| 190 |
|
|
|
| 191 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
|
| 192 |
|
|
|
| 193 |
|
|
|
| 194 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
|
| 195 |
|
|
|
| 196 |
|
|
|
| 197 |
|
|
|
| 198 |
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)
|
| 199 |
|
|
|
| 200 |
|
|
|
| 201 |
|
|
Available hyper_sources - for debug and ip models
|
| 202 |
|
|
None Found
|
| 203 |
|
|
|
| 204 |
|
|
@N: MT206 |Auto Constrain mode is enabled
|
| 205 |
|
|
|
| 206 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)
|
| 207 |
|
|
|
| 208 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Found counter in view:work.MC6809_cpu(verilog) inst k_cpu_addr[15:0]
|
| 209 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 210 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 211 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 212 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Found counter in view:work.regblock(verilog) inst PC[15:0]
|
| 213 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_clear_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 214 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_set_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 215 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 216 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 217 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 218 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Removing sequential instance regs.fflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 219 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Removing sequential instance regs.intff in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 220 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Removing sequential instance regs.eflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 221 |
|
|
|
| 222 |
|
|
Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 161MB peak: 161MB)
|
| 223 |
|
|
|
| 224 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 225 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 226 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 227 |
|
|
|
| 228 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 163MB)
|
| 229 |
|
|
|
| 230 |
|
|
|
| 231 |
|
|
|
| 232 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 149MB peak: 163MB)
|
| 233 |
|
|
|
| 234 |
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":106:2:106:6|Pipelining module un1_ea_reg[15:0]
|
| 235 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_ind_ea[7:0] pushed in.
|
| 236 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register DP[7:0] pushed in.
|
| 237 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.
|
| 238 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_new_pc[15:0] pushed in.
|
| 239 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.
|
| 240 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register vff pushed in.
|
| 241 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register zff pushed in.
|
| 242 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register nff pushed in.
|
| 243 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register hflag pushed in.
|
| 244 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_memhi[7:0] pushed in.
|
| 245 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register reg_z_in pushed in.
|
| 246 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register reg_n_in pushed in.
|
| 247 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_ealo[7:0] pushed in.
|
| 248 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_eahi[7:0] pushed in.
|
| 249 |
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":180:19:180:32|Pipelining module daa_lnm9
|
| 250 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.
|
| 251 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.
|
| 252 |
|
|
@N: MF169 :|Register NoName pushed in.
|
| 253 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Register k_memlo[7:0] pushed in.
|
| 254 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":170:0:170:5|Register DP[7:0] pushed in.
|
| 255 |
|
|
|
| 256 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 163MB)
|
| 257 |
|
|
|
| 258 |
|
|
|
| 259 |
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 157MB peak: 163MB)
|
| 260 |
|
|
|
| 261 |
|
|
|
| 262 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 156MB peak: 163MB)
|
| 263 |
|
|
|
| 264 |
|
|
|
| 265 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 155MB peak: 163MB)
|
| 266 |
|
|
|
| 267 |
|
|
|
| 268 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 231MB peak: 234MB)
|
| 269 |
|
|
|
| 270 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 271 |
|
|
------------------------------------------------------------
|
| 272 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 273 |
|
|
------------------------------------------------------------
|
| 274 |
|
|
1 0h:00m:14s -7.90ns 1868 / 545
|
| 275 |
|
|
2 0h:00m:14s -7.58ns 1868 / 545
|
| 276 |
|
|
3 0h:00m:14s -7.58ns 1869 / 545
|
| 277 |
|
|
------------------------------------------------------------
|
| 278 |
|
|
|
| 279 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[3]" with 7 loads replicated 1 times to improve timing
|
| 280 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[2]" with 6 loads replicated 1 times to improve timing
|
| 281 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[1]" with 6 loads replicated 1 times to improve timing
|
| 282 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[4]" with 5 loads replicated 1 times to improve timing
|
| 283 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[3]" with 53 loads replicated 3 times to improve timing
|
| 284 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[0]" with 51 loads replicated 2 times to improve timing
|
| 285 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[7]" with 45 loads replicated 2 times to improve timing
|
| 286 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[6]" with 31 loads replicated 2 times to improve timing
|
| 287 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[2]" with 57 loads replicated 3 times to improve timing
|
| 288 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[4]" with 26 loads replicated 2 times to improve timing
|
| 289 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[5]" with 26 loads replicated 2 times to improve timing
|
| 290 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_opcode[1]" with 44 loads replicated 2 times to improve timing
|
| 291 |
|
|
Timing driven replication report
|
| 292 |
|
|
Added 22 Registers via timing driven replication
|
| 293 |
|
|
Added 3 LUTs via timing driven replication
|
| 294 |
|
|
|
| 295 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[6]" with 6 loads replicated 1 times to improve timing
|
| 296 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[7]" with 6 loads replicated 1 times to improve timing
|
| 297 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[5]" with 7 loads replicated 1 times to improve timing
|
| 298 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_pp_active_reg[0]" with 9 loads replicated 1 times to improve timing
|
| 299 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_p2_valid" with 23 loads replicated 1 times to improve timing
|
| 300 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[7]" with 19 loads replicated 1 times to improve timing
|
| 301 |
|
|
Added 6 Registers via timing driven replication
|
| 302 |
|
|
Added 3 LUTs via timing driven replication
|
| 303 |
|
|
|
| 304 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[0]" with 17 loads replicated 1 times to improve timing
|
| 305 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[6]" with 14 loads replicated 1 times to improve timing
|
| 306 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[3]" with 14 loads replicated 1 times to improve timing
|
| 307 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_postbyte0[2]" with 13 loads replicated 1 times to improve timing
|
| 308 |
|
|
@N: FX271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":272:0:272:5|Instance "cpu0.k_p3_valid" with 12 loads replicated 1 times to improve timing
|
| 309 |
|
|
Added 5 Registers via timing driven replication
|
| 310 |
|
|
Added 1 LUTs via timing driven replication
|
| 311 |
|
|
|
| 312 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 313 |
|
|
------------------------------------------------------------
|
| 314 |
|
|
1 0h:00m:16s -5.90ns 1913 / 578
|
| 315 |
|
|
2 0h:00m:16s -5.90ns 1914 / 578
|
| 316 |
|
|
------------------------------------------------------------
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
|
| 320 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 321 |
|
|
------------------------------------------------------------
|
| 322 |
|
|
1 0h:00m:16s -5.90ns 1917 / 578
|
| 323 |
|
|
------------------------------------------------------------
|
| 324 |
|
|
|
| 325 |
|
|
|
| 326 |
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 169MB peak: 234MB)
|
| 327 |
|
|
|
| 328 |
|
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
| 329 |
|
|
|
| 330 |
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 171MB peak: 234MB)
|
| 331 |
|
|
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
| 335 |
|
|
|
| 336 |
|
|
1 non-gated/non-generated clock tree(s) driving 582 clock pin(s) of sequential element(s)
|
| 337 |
|
|
|
| 338 |
|
|
292 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
| 339 |
|
|
|
| 340 |
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
| 341 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
| 342 |
|
|
---------------------------------------------------------------------------------------
|
| 343 |
|
|
@K:CKID0001 clk40_i port 582 cpu_clk
|
| 344 |
|
|
=======================================================================================
|
| 345 |
|
|
===== Gated/Generated Clocks =====
|
| 346 |
|
|
************** None **************
|
| 347 |
|
|
----------------------------------
|
| 348 |
|
|
==================================
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
| 352 |
|
|
|
| 353 |
|
|
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809.srm
|
| 354 |
|
|
|
| 355 |
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 173MB peak: 234MB)
|
| 356 |
|
|
|
| 357 |
|
|
Writing EDIF Netlist and constraint files
|
| 358 |
|
|
G-2012.09L-SP1
|
| 359 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
| 360 |
|
|
|
| 361 |
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 177MB peak: 234MB)
|
| 362 |
|
|
|
| 363 |
|
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 18.92ns. Please declare a user-defined clock on object "p:clk40_i"
|
| 364 |
|
|
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
##### START OF TIMING REPORT #####[
|
| 368 |
|
|
# Timing Report written on Sun Dec 29 07:16:49 2013
|
| 369 |
|
|
#
|
| 370 |
|
|
|
| 371 |
|
|
|
| 372 |
|
|
Top view: CC3_top
|
| 373 |
|
|
Requested Frequency: 52.8 MHz
|
| 374 |
|
|
Wire load mode: top
|
| 375 |
|
|
Paths requested: 5
|
| 376 |
|
|
Constraint File(s):
|
| 377 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
| 378 |
|
|
|
| 379 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
| 380 |
|
|
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
|
|
Performance Summary
|
| 384 |
|
|
*******************
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
Worst slack in design: -3.066
|
| 388 |
|
|
|
| 389 |
|
|
Requested Estimated Requested Estimated Clock Clock
|
| 390 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 391 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
| 392 |
|
|
CC3_top|clk40_i 52.8 MHz 45.5 MHz 18.924 21.989 -3.066 inferred Autoconstr_clkgroup_0
|
| 393 |
|
|
=========================================================================================================================
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
|
| 398 |
|
|
|
| 399 |
|
|
Clock Relationships
|
| 400 |
|
|
*******************
|
| 401 |
|
|
|
| 402 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
| 403 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
| 404 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
| 405 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
| 406 |
|
|
CC3_top|clk40_i CC3_top|clk40_i | 18.924 -3.066 | No paths - | No paths - | No paths -
|
| 407 |
|
|
=========================================================================================================================
|
| 408 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 409 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 410 |
|
|
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
Interface Information
|
| 414 |
|
|
*********************
|
| 415 |
|
|
|
| 416 |
|
|
No IO constraint found
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
====================================
|
| 421 |
|
|
Detailed Report for Clock: CC3_top|clk40_i
|
| 422 |
|
|
====================================
|
| 423 |
|
|
|
| 424 |
|
|
|
| 425 |
|
|
|
| 426 |
|
|
Starting Points with Worst Slack
|
| 427 |
|
|
********************************
|
| 428 |
|
|
|
| 429 |
|
|
Starting Arrival
|
| 430 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 431 |
|
|
Clock
|
| 432 |
|
|
---------------------------------------------------------------------------------------------------------
|
| 433 |
|
|
cpu0.k_opcode_fast[0] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[0] 1.188 -3.066
|
| 434 |
|
|
cpu0.k_opcode_3_rep1 CC3_top|clk40_i FD1P3AX Q k_opcode_3_rep1 1.180 -3.058
|
| 435 |
|
|
cpu0.k_opcode_2_rep1 CC3_top|clk40_i FD1P3AX Q k_opcode_2_rep1 1.148 -3.026
|
| 436 |
|
|
cpu0.k_opcode_fast[7] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[7] 1.204 -2.772
|
| 437 |
|
|
cpu0.k_opcode_fast[1] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[1] 1.188 -2.756
|
| 438 |
|
|
cpu0.k_opcode_fast[3] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[3] 1.188 -2.756
|
| 439 |
|
|
cpu0.k_opcode_fast[5] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[5] 1.148 -2.716
|
| 440 |
|
|
cpu0.k_opcode_fast[6] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[6] 1.148 -2.716
|
| 441 |
|
|
cpu0.k_opcode_fast[2] CC3_top|clk40_i FD1P3AX Q k_opcode_fast[2] 1.108 -2.675
|
| 442 |
|
|
cpu0.k_opcode_2_rep2 CC3_top|clk40_i FD1P3AX Q k_opcode_2_rep2 1.244 -2.575
|
| 443 |
|
|
=========================================================================================================
|
| 444 |
|
|
|
| 445 |
|
|
|
| 446 |
|
|
Ending Points with Worst Slack
|
| 447 |
|
|
******************************
|
| 448 |
|
|
|
| 449 |
|
|
Starting Required
|
| 450 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 451 |
|
|
Clock
|
| 452 |
|
|
--------------------------------------------------------------------------------------------------
|
| 453 |
|
|
cpu0.alu.regq16_pipe CC3_top|clk40_i FD1P3AX D N_712 19.012 -3.066
|
| 454 |
|
|
cpu0.alu.regq16_pipe_11 CC3_top|clk40_i FD1P3AX D N_711 19.012 -2.923
|
| 455 |
|
|
cpu0.alu.regq16_pipe_22 CC3_top|clk40_i FD1P3AX D N_710 19.012 -2.923
|
| 456 |
|
|
cpu0.alu.regq16_pipe_33 CC3_top|clk40_i FD1P3AX D N_709 19.012 -2.780
|
| 457 |
|
|
cpu0.alu.regq16_pipe_44 CC3_top|clk40_i FD1P3AX D N_708 19.012 -2.780
|
| 458 |
|
|
cpu0.alu.regq16_pipe_55 CC3_top|clk40_i FD1P3AX D N_707 19.012 -2.638
|
| 459 |
|
|
cpu0.alu.regq16_pipe_66 CC3_top|clk40_i FD1P3AX D N_706 19.012 -2.638
|
| 460 |
|
|
cpu0.alu.regq16_pipe_97 CC3_top|clk40_i FD1P3AX D N_703 19.386 -2.592
|
| 461 |
|
|
cpu0.regs.cff CC3_top|clk40_i FD1P3AX D N_27_i 19.012 -2.567
|
| 462 |
|
|
cpu0.alu.regq16_pipe_88 CC3_top|clk40_i FD1P3AX D N_704 19.012 -2.567
|
| 463 |
|
|
==================================================================================================
|
| 464 |
|
|
|
| 465 |
|
|
|
| 466 |
|
|
|
| 467 |
|
|
Worst Path Information
|
| 468 |
|
|
***********************
|
| 469 |
|
|
|
| 470 |
|
|
|
| 471 |
|
|
Path information for path number 1:
|
| 472 |
|
|
Requested Period: 18.924
|
| 473 |
|
|
- Setup time: -0.089
|
| 474 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 475 |
|
|
= Required time: 19.012
|
| 476 |
|
|
|
| 477 |
|
|
- Propagation time: 22.078
|
| 478 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 479 |
|
|
= Slack (critical) : -3.066
|
| 480 |
|
|
|
| 481 |
|
|
Number of logic level(s): 21
|
| 482 |
|
|
Starting point: cpu0.k_opcode_fast[0] / Q
|
| 483 |
|
|
Ending point: cpu0.alu.regq16_pipe / D
|
| 484 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 485 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 486 |
|
|
|
| 487 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 488 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 489 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
| 490 |
|
|
cpu0.k_opcode_fast[0] FD1P3AX Q Out 1.188 1.188 -
|
| 491 |
|
|
k_opcode_fast[0] Net - - - - 6
|
| 492 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 C In 0.000 1.188 -
|
| 493 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.205 -
|
| 494 |
|
|
N_83 Net - - - - 1
|
| 495 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.205 -
|
| 496 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.221 -
|
| 497 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1
|
| 498 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.221 -
|
| 499 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.454 -
|
| 500 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6
|
| 501 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.454 -
|
| 502 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.543 -
|
| 503 |
|
|
datamux_m2 Net - - - - 2
|
| 504 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.543 -
|
| 505 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.560 -
|
| 506 |
|
|
datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1
|
| 507 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.560 -
|
| 508 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.901 -
|
| 509 |
|
|
datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24
|
| 510 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.901 -
|
| 511 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.989 -
|
| 512 |
|
|
datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2
|
| 513 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.989 -
|
| 514 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 10.006 -
|
| 515 |
|
|
datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1
|
| 516 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 10.006 -
|
| 517 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.323 -
|
| 518 |
|
|
datamux_o_alu_in_left_path_data[0] Net - - - - 18
|
| 519 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.323 -
|
| 520 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.867 -
|
| 521 |
|
|
mul16_w_madd_0_cry_0 Net - - - - 1
|
| 522 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.867 -
|
| 523 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.489 -
|
| 524 |
|
|
mul16_w_madd_0[2] Net - - - - 2
|
| 525 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.489 -
|
| 526 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 16.033 -
|
| 527 |
|
|
mul16_w_madd_4_cry_0 Net - - - - 1
|
| 528 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 16.033 -
|
| 529 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.654 -
|
| 530 |
|
|
mul16_w_madd Net - - - - 2
|
| 531 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.654 -
|
| 532 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.198 -
|
| 533 |
|
|
mul16_w_madd_cry_0 Net - - - - 1
|
| 534 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.198 -
|
| 535 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.341 -
|
| 536 |
|
|
mul16_w_madd_cry_2 Net - - - - 1
|
| 537 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.341 -
|
| 538 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.484 -
|
| 539 |
|
|
mul16_w_madd_cry_4 Net - - - - 1
|
| 540 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.484 -
|
| 541 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.627 -
|
| 542 |
|
|
mul16_w_madd_cry_6 Net - - - - 1
|
| 543 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.627 -
|
| 544 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.770 -
|
| 545 |
|
|
mul16_w_madd_cry_8 Net - - - - 1
|
| 546 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.770 -
|
| 547 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.913 -
|
| 548 |
|
|
mul16_w_madd_cry_10 Net - - - - 1
|
| 549 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.913 -
|
| 550 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.462 -
|
| 551 |
|
|
mul16_w[15] Net - - - - 1
|
| 552 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.462 -
|
| 553 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.078 -
|
| 554 |
|
|
N_712 Net - - - - 1
|
| 555 |
|
|
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.078 -
|
| 556 |
|
|
======================================================================================================================
|
| 557 |
|
|
|
| 558 |
|
|
|
| 559 |
|
|
Path information for path number 2:
|
| 560 |
|
|
Requested Period: 18.924
|
| 561 |
|
|
- Setup time: -0.089
|
| 562 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 563 |
|
|
= Required time: 19.012
|
| 564 |
|
|
|
| 565 |
|
|
- Propagation time: 22.070
|
| 566 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 567 |
|
|
= Slack (non-critical) : -3.058
|
| 568 |
|
|
|
| 569 |
|
|
Number of logic level(s): 21
|
| 570 |
|
|
Starting point: cpu0.k_opcode_3_rep1 / Q
|
| 571 |
|
|
Ending point: cpu0.alu.regq16_pipe / D
|
| 572 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 573 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 574 |
|
|
|
| 575 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 576 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 577 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
| 578 |
|
|
cpu0.k_opcode_3_rep1 FD1P3AX Q Out 1.180 1.180 -
|
| 579 |
|
|
k_opcode_3_rep1 Net - - - - 5
|
| 580 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 B In 0.000 1.180 -
|
| 581 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.197 -
|
| 582 |
|
|
N_83 Net - - - - 1
|
| 583 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.197 -
|
| 584 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.213 -
|
| 585 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1
|
| 586 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.213 -
|
| 587 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.446 -
|
| 588 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6
|
| 589 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.446 -
|
| 590 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.535 -
|
| 591 |
|
|
datamux_m2 Net - - - - 2
|
| 592 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.535 -
|
| 593 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.552 -
|
| 594 |
|
|
datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1
|
| 595 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.552 -
|
| 596 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.893 -
|
| 597 |
|
|
datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24
|
| 598 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.893 -
|
| 599 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.981 -
|
| 600 |
|
|
datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2
|
| 601 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.981 -
|
| 602 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 9.998 -
|
| 603 |
|
|
datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1
|
| 604 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 9.998 -
|
| 605 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.315 -
|
| 606 |
|
|
datamux_o_alu_in_left_path_data[0] Net - - - - 18
|
| 607 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.315 -
|
| 608 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.860 -
|
| 609 |
|
|
mul16_w_madd_0_cry_0 Net - - - - 1
|
| 610 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.860 -
|
| 611 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.480 -
|
| 612 |
|
|
mul16_w_madd_0[2] Net - - - - 2
|
| 613 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.480 -
|
| 614 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 16.025 -
|
| 615 |
|
|
mul16_w_madd_4_cry_0 Net - - - - 1
|
| 616 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 16.025 -
|
| 617 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.646 -
|
| 618 |
|
|
mul16_w_madd Net - - - - 2
|
| 619 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.646 -
|
| 620 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.191 -
|
| 621 |
|
|
mul16_w_madd_cry_0 Net - - - - 1
|
| 622 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.191 -
|
| 623 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.333 -
|
| 624 |
|
|
mul16_w_madd_cry_2 Net - - - - 1
|
| 625 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.333 -
|
| 626 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.476 -
|
| 627 |
|
|
mul16_w_madd_cry_4 Net - - - - 1
|
| 628 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.476 -
|
| 629 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.619 -
|
| 630 |
|
|
mul16_w_madd_cry_6 Net - - - - 1
|
| 631 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.619 -
|
| 632 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.762 -
|
| 633 |
|
|
mul16_w_madd_cry_8 Net - - - - 1
|
| 634 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.762 -
|
| 635 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.904 -
|
| 636 |
|
|
mul16_w_madd_cry_10 Net - - - - 1
|
| 637 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.904 -
|
| 638 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.453 -
|
| 639 |
|
|
mul16_w[15] Net - - - - 1
|
| 640 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.453 -
|
| 641 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.070 -
|
| 642 |
|
|
N_712 Net - - - - 1
|
| 643 |
|
|
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.070 -
|
| 644 |
|
|
======================================================================================================================
|
| 645 |
|
|
|
| 646 |
|
|
|
| 647 |
|
|
Path information for path number 3:
|
| 648 |
|
|
Requested Period: 18.924
|
| 649 |
|
|
- Setup time: -0.089
|
| 650 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 651 |
|
|
= Required time: 19.012
|
| 652 |
|
|
|
| 653 |
|
|
- Propagation time: 22.038
|
| 654 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 655 |
|
|
= Slack (non-critical) : -3.026
|
| 656 |
|
|
|
| 657 |
|
|
Number of logic level(s): 21
|
| 658 |
|
|
Starting point: cpu0.k_opcode_2_rep1 / Q
|
| 659 |
|
|
Ending point: cpu0.alu.regq16_pipe / D
|
| 660 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 661 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 662 |
|
|
|
| 663 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 664 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 665 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
| 666 |
|
|
cpu0.k_opcode_2_rep1 FD1P3AX Q Out 1.148 1.148 -
|
| 667 |
|
|
k_opcode_2_rep1 Net - - - - 4
|
| 668 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 A In 0.000 1.148 -
|
| 669 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.165 -
|
| 670 |
|
|
N_83 Net - - - - 1
|
| 671 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.165 -
|
| 672 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.181 -
|
| 673 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1
|
| 674 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.181 -
|
| 675 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.414 -
|
| 676 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6
|
| 677 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.414 -
|
| 678 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.503 -
|
| 679 |
|
|
datamux_m2 Net - - - - 2
|
| 680 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.503 -
|
| 681 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.520 -
|
| 682 |
|
|
datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1
|
| 683 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.520 -
|
| 684 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.861 -
|
| 685 |
|
|
datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24
|
| 686 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.861 -
|
| 687 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.949 -
|
| 688 |
|
|
datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2
|
| 689 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.949 -
|
| 690 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 9.966 -
|
| 691 |
|
|
datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1
|
| 692 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 9.966 -
|
| 693 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.283 -
|
| 694 |
|
|
datamux_o_alu_in_left_path_data[0] Net - - - - 18
|
| 695 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.283 -
|
| 696 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.828 -
|
| 697 |
|
|
mul16_w_madd_0_cry_0 Net - - - - 1
|
| 698 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.828 -
|
| 699 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.448 -
|
| 700 |
|
|
mul16_w_madd_0[2] Net - - - - 2
|
| 701 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.448 -
|
| 702 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 15.993 -
|
| 703 |
|
|
mul16_w_madd_4_cry_0 Net - - - - 1
|
| 704 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 15.993 -
|
| 705 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.614 -
|
| 706 |
|
|
mul16_w_madd Net - - - - 2
|
| 707 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.614 -
|
| 708 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.159 -
|
| 709 |
|
|
mul16_w_madd_cry_0 Net - - - - 1
|
| 710 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.159 -
|
| 711 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.301 -
|
| 712 |
|
|
mul16_w_madd_cry_2 Net - - - - 1
|
| 713 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.301 -
|
| 714 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.444 -
|
| 715 |
|
|
mul16_w_madd_cry_4 Net - - - - 1
|
| 716 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.444 -
|
| 717 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.587 -
|
| 718 |
|
|
mul16_w_madd_cry_6 Net - - - - 1
|
| 719 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.587 -
|
| 720 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.730 -
|
| 721 |
|
|
mul16_w_madd_cry_8 Net - - - - 1
|
| 722 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.730 -
|
| 723 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.872 -
|
| 724 |
|
|
mul16_w_madd_cry_10 Net - - - - 1
|
| 725 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.872 -
|
| 726 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.422 -
|
| 727 |
|
|
mul16_w[15] Net - - - - 1
|
| 728 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.422 -
|
| 729 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.038 -
|
| 730 |
|
|
N_712 Net - - - - 1
|
| 731 |
|
|
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.038 -
|
| 732 |
|
|
======================================================================================================================
|
| 733 |
|
|
|
| 734 |
|
|
|
| 735 |
|
|
Path information for path number 4:
|
| 736 |
|
|
Requested Period: 18.924
|
| 737 |
|
|
- Setup time: -0.089
|
| 738 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 739 |
|
|
= Required time: 19.012
|
| 740 |
|
|
|
| 741 |
|
|
- Propagation time: 22.006
|
| 742 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 743 |
|
|
= Slack (non-critical) : -2.994
|
| 744 |
|
|
|
| 745 |
|
|
Number of logic level(s): 21
|
| 746 |
|
|
Starting point: cpu0.k_opcode_fast[0] / Q
|
| 747 |
|
|
Ending point: cpu0.alu.regq16_pipe / D
|
| 748 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 749 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 750 |
|
|
|
| 751 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 752 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 753 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
| 754 |
|
|
cpu0.k_opcode_fast[0] FD1P3AX Q Out 1.188 1.188 -
|
| 755 |
|
|
k_opcode_fast[0] Net - - - - 6
|
| 756 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 C In 0.000 1.188 -
|
| 757 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.205 -
|
| 758 |
|
|
N_83 Net - - - - 1
|
| 759 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.205 -
|
| 760 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.221 -
|
| 761 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1
|
| 762 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.221 -
|
| 763 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.454 -
|
| 764 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6
|
| 765 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.454 -
|
| 766 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.543 -
|
| 767 |
|
|
datamux_m2 Net - - - - 2
|
| 768 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.543 -
|
| 769 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.560 -
|
| 770 |
|
|
datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1
|
| 771 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.560 -
|
| 772 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.901 -
|
| 773 |
|
|
datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24
|
| 774 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_1_1[0] ORCALUT4 A In 0.000 7.901 -
|
| 775 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_1_1[0] ORCALUT4 Z Out 1.017 8.917 -
|
| 776 |
|
|
datamux_o_alu_in_left_path_data_0_1_1[0] Net - - - - 1
|
| 777 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 B In 0.000 8.917 -
|
| 778 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 9.934 -
|
| 779 |
|
|
datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1
|
| 780 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 9.934 -
|
| 781 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.251 -
|
| 782 |
|
|
datamux_o_alu_in_left_path_data[0] Net - - - - 18
|
| 783 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.251 -
|
| 784 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.796 -
|
| 785 |
|
|
mul16_w_madd_0_cry_0 Net - - - - 1
|
| 786 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.796 -
|
| 787 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 14.416 -
|
| 788 |
|
|
mul16_w_madd_0[2] Net - - - - 2
|
| 789 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D C1 In 0.000 14.416 -
|
| 790 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 15.961 -
|
| 791 |
|
|
mul16_w_madd_4_cry_0 Net - - - - 1
|
| 792 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 15.961 -
|
| 793 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 17.582 -
|
| 794 |
|
|
mul16_w_madd Net - - - - 2
|
| 795 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 17.582 -
|
| 796 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 19.127 -
|
| 797 |
|
|
mul16_w_madd_cry_0 Net - - - - 1
|
| 798 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 19.127 -
|
| 799 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 19.269 -
|
| 800 |
|
|
mul16_w_madd_cry_2 Net - - - - 1
|
| 801 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 19.269 -
|
| 802 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 0.143 19.412 -
|
| 803 |
|
|
mul16_w_madd_cry_4 Net - - - - 1
|
| 804 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.412 -
|
| 805 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.555 -
|
| 806 |
|
|
mul16_w_madd_cry_6 Net - - - - 1
|
| 807 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.555 -
|
| 808 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.698 -
|
| 809 |
|
|
mul16_w_madd_cry_8 Net - - - - 1
|
| 810 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.698 -
|
| 811 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.840 -
|
| 812 |
|
|
mul16_w_madd_cry_10 Net - - - - 1
|
| 813 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.840 -
|
| 814 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.390 -
|
| 815 |
|
|
mul16_w[15] Net - - - - 1
|
| 816 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.390 -
|
| 817 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.006 -
|
| 818 |
|
|
N_712 Net - - - - 1
|
| 819 |
|
|
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.006 -
|
| 820 |
|
|
======================================================================================================================
|
| 821 |
|
|
|
| 822 |
|
|
|
| 823 |
|
|
Path information for path number 5:
|
| 824 |
|
|
Requested Period: 18.924
|
| 825 |
|
|
- Setup time: -0.089
|
| 826 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 827 |
|
|
= Required time: 19.012
|
| 828 |
|
|
|
| 829 |
|
|
- Propagation time: 22.006
|
| 830 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 831 |
|
|
= Slack (non-critical) : -2.994
|
| 832 |
|
|
|
| 833 |
|
|
Number of logic level(s): 21
|
| 834 |
|
|
Starting point: cpu0.k_opcode_fast[0] / Q
|
| 835 |
|
|
Ending point: cpu0.alu.regq16_pipe / D
|
| 836 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 837 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 838 |
|
|
|
| 839 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 840 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 841 |
|
|
----------------------------------------------------------------------------------------------------------------------
|
| 842 |
|
|
cpu0.k_opcode_fast[0] FD1P3AX Q Out 1.188 1.188 -
|
| 843 |
|
|
k_opcode_fast[0] Net - - - - 6
|
| 844 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 C In 0.000 1.188 -
|
| 845 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_o2 ORCALUT4 Z Out 1.017 2.205 -
|
| 846 |
|
|
N_83 Net - - - - 1
|
| 847 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 A In 0.000 2.205 -
|
| 848 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2_x0 ORCALUT4 Z Out 1.017 3.221 -
|
| 849 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2_x0 Net - - - - 1
|
| 850 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 A In 0.000 3.221 -
|
| 851 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_0_2 ORCALUT4 Z Out 1.233 4.454 -
|
| 852 |
|
|
un1_dest_reg_2_sqmuxa_1_1_0_2 Net - - - - 6
|
| 853 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 D In 0.000 4.454 -
|
| 854 |
|
|
cpu0.alu.datamux_m2 ORCALUT4 Z Out 1.089 5.543 -
|
| 855 |
|
|
datamux_m2 Net - - - - 2
|
| 856 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 A In 0.000 5.543 -
|
| 857 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0_sx[0] ORCALUT4 Z Out 1.017 6.560 -
|
| 858 |
|
|
datamux_o_alu_in_left_path_data_a0_0_sx[0] Net - - - - 1
|
| 859 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 A In 0.000 6.560 -
|
| 860 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a0_0[0] ORCALUT4 Z Out 1.341 7.901 -
|
| 861 |
|
|
datamux_o_alu_in_left_path_data_a1_0[0] Net - - - - 24
|
| 862 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 A In 0.000 7.901 -
|
| 863 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_a1_0[0] ORCALUT4 Z Out 1.089 8.989 -
|
| 864 |
|
|
datamux_o_alu_in_left_path_data_a1_0_0[0] Net - - - - 2
|
| 865 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 C In 0.000 8.989 -
|
| 866 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0_sx[0] ORCALUT4 Z Out 1.017 10.006 -
|
| 867 |
|
|
datamux_o_alu_in_left_path_data_0_sx[0] Net - - - - 1
|
| 868 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 B In 0.000 10.006 -
|
| 869 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data_0[0] ORCALUT4 Z Out 1.317 11.323 -
|
| 870 |
|
|
datamux_o_alu_in_left_path_data[0] Net - - - - 18
|
| 871 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D C1 In 0.000 11.323 -
|
| 872 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 12.867 -
|
| 873 |
|
|
mul16_w_madd_0_cry_0 Net - - - - 1
|
| 874 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D CIN In 0.000 12.867 -
|
| 875 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D COUT Out 0.143 13.010 -
|
| 876 |
|
|
mul16_w_madd_0_cry_2 Net - - - - 1
|
| 877 |
|
|
cpu0.alu.mul16_w_madd_0_cry_3_0 CCU2D CIN In 0.000 13.010 -
|
| 878 |
|
|
cpu0.alu.mul16_w_madd_0_cry_3_0 CCU2D COUT Out 0.143 13.153 -
|
| 879 |
|
|
mul16_w_madd_0_cry_4 Net - - - - 1
|
| 880 |
|
|
cpu0.alu.mul16_w_madd_0_cry_5_0 CCU2D CIN In 0.000 13.153 -
|
| 881 |
|
|
cpu0.alu.mul16_w_madd_0_cry_5_0 CCU2D S0 Out 1.621 14.774 -
|
| 882 |
|
|
mul16_w_madd_0[6] Net - - - - 2
|
| 883 |
|
|
cpu0.alu.mul16_w_madd_5_cry_2_0 CCU2D B1 In 0.000 14.774 -
|
| 884 |
|
|
cpu0.alu.mul16_w_madd_5_cry_2_0 CCU2D COUT Out 1.544 16.319 -
|
| 885 |
|
|
mul16_w_madd_5_cry_2 Net - - - - 1
|
| 886 |
|
|
cpu0.alu.mul16_w_madd_5_cry_3_0 CCU2D CIN In 0.000 16.319 -
|
| 887 |
|
|
cpu0.alu.mul16_w_madd_5_cry_3_0 CCU2D S1 Out 1.549 17.868 -
|
| 888 |
|
|
mul16_w_madd_5[8] Net - - - - 1
|
| 889 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D A1 In 0.000 17.868 -
|
| 890 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D COUT Out 1.544 19.412 -
|
| 891 |
|
|
mul16_w_madd_cry_4 Net - - - - 1
|
| 892 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D CIN In 0.000 19.412 -
|
| 893 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 19.555 -
|
| 894 |
|
|
mul16_w_madd_cry_6 Net - - - - 1
|
| 895 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D CIN In 0.000 19.555 -
|
| 896 |
|
|
cpu0.alu.mul16_w_madd_cry_7_0 CCU2D COUT Out 0.143 19.698 -
|
| 897 |
|
|
mul16_w_madd_cry_8 Net - - - - 1
|
| 898 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 19.698 -
|
| 899 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 19.840 -
|
| 900 |
|
|
mul16_w_madd_cry_10 Net - - - - 1
|
| 901 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 19.840 -
|
| 902 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D S0 Out 1.549 21.390 -
|
| 903 |
|
|
mul16_w[15] Net - - - - 1
|
| 904 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 C In 0.000 21.390 -
|
| 905 |
|
|
cpu0.alu.regq16_pipe_RNO ORCALUT4 Z Out 0.617 22.006 -
|
| 906 |
|
|
N_712 Net - - - - 1
|
| 907 |
|
|
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 22.006 -
|
| 908 |
|
|
======================================================================================================================
|
| 909 |
|
|
|
| 910 |
|
|
|
| 911 |
|
|
|
| 912 |
|
|
##### END OF TIMING REPORT #####]
|
| 913 |
|
|
|
| 914 |
|
|
---------------------------------------
|
| 915 |
|
|
Resource Usage Report
|
| 916 |
|
|
Part: lcmxo2_7000he-4
|
| 917 |
|
|
|
| 918 |
|
|
Register bits: 578 of 6864 (8%)
|
| 919 |
|
|
PIC Latch: 0
|
| 920 |
|
|
I/O cells: 49
|
| 921 |
|
|
Block Rams : 2 of 26 (7%)
|
| 922 |
|
|
|
| 923 |
|
|
|
| 924 |
|
|
Details:
|
| 925 |
|
|
CCU2D: 162
|
| 926 |
|
|
DP8KC: 2
|
| 927 |
|
|
FD1P3AX: 558
|
| 928 |
|
|
FD1P3DX: 6
|
| 929 |
|
|
FD1P3IX: 1
|
| 930 |
|
|
FD1P3JX: 4
|
| 931 |
|
|
FD1S3AX: 1
|
| 932 |
|
|
GSR: 1
|
| 933 |
|
|
IB: 1
|
| 934 |
|
|
INV: 5
|
| 935 |
|
|
L6MUX21: 10
|
| 936 |
|
|
OB: 48
|
| 937 |
|
|
OFS1P3DX: 8
|
| 938 |
|
|
ORCALUT4: 1908
|
| 939 |
|
|
PFUMX: 181
|
| 940 |
|
|
PUR: 1
|
| 941 |
|
|
VHI: 4
|
| 942 |
|
|
VLO: 10
|
| 943 |
|
|
Mapper successful!
|
| 944 |
|
|
|
| 945 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 45MB peak: 234MB)
|
| 946 |
|
|
|
| 947 |
|
|
Process took 0h:00m:18s realtime, 0h:00m:18s cputime
|
| 948 |
|
|
# Sun Dec 29 07:16:49 2013
|
| 949 |
|
|
|
| 950 |
|
|
###########################################################]
|
