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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Blame information for rev 9

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Line No. Rev Author Line
1 9 ale500 
 
2 
Loading design for application trce from file P6809_P6809.ncd.
3 
Design name: CC3_top
4 
NCD version: 3.2
5 
Vendor:      LATTICE
6 
Device:      LCMXO2-7000HE
7 
Package:     TQFP144
8 
Performance: 4
9 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
10 
Package Status:                     Final          Version 1.36
11 
Performance Hardware Data Status:   Final)         Version 23.4
12 
Setup and Hold Report
13 
 
14 
--------------------------------------------------------------------------------
15 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
16 
Mon Jan  6 06:55:04 2014
17 
 
18 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
19 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
20 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
21 
Copyright (c) 2001 Agere Systems   All rights reserved.
22 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
23 
 
24 
Report Information
25 
------------------
26 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
27 
Design file:     P6809_P6809.ncd
28 
Preference file: P6809_P6809.prf
29 
Device,speed:    LCMXO2-7000HE,4
30 
Report level:    verbose report, limited to 10 items per preference
31 
--------------------------------------------------------------------------------
32 
 
33 
BLOCK ASYNCPATHS
34 
BLOCK RESETPATHS
35 
--------------------------------------------------------------------------------
36 
 
37 
 
38 
 
39 
================================================================================
40 
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
41 
            4096 items scored, 0 timing errors detected.
42 
--------------------------------------------------------------------------------
43 
 
44 
 
45 
Passed: The following path meets requirements by 1.054ns
46 
 
47 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
48 
 
49 
   Source:         FF         Q              cpu0/alu/rb_in[1]  (from cpu_clkgen +)
50 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
51 
 
52 
   Delay:              23.780ns  (42.8% logic, 57.2% route), 19 logic levels.
53 
 
54 
 Constraint Details:
55 
 
56 
     23.780ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 meets
57 
     25.000ns delay constraint less
58 
      0.000ns skew and
59 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.054ns
60 
 
61 
 Physical Path Details:
62 
 
63 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
64 
 
65 
   Name    Fanout   Delay (ns)          Site               Resource
66 
REG_DEL     ---     0.452    R12C13B.CLK to     R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
67 
ROUTE        26     1.735     R12C13B.Q1 to     R10C14B.A0 cpu0/alu/rb_in[1]
68 
C0TOFCO_DE  ---     1.023     R10C14B.A0 to    R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
69 
ROUTE         1     0.000    R10C14B.FCO to    R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
70 
FCITOF1_DE  ---     0.643    R10C14C.FCI to     R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
71 
ROUTE         1     1.385     R10C14C.F1 to     R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
72 
CTOF_DEL    ---     0.495     R11C17C.D0 to     R11C17C.F0 cpu0/alu/SLICE_1151
73 
ROUTE         1     1.675     R11C17C.F0 to     R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
74 
C1TOFCO_DE  ---     0.889     R11C21C.C1 to    R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
75 
ROUTE         1     0.000    R11C21C.FCO to    R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
76 
FCITOF0_DE  ---     0.585    R11C21D.FCI to     R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
77 
ROUTE         1     1.705     R11C21D.F0 to      R7C15D.C0 cpu0/alu/alu16/a16/N_2261
78 
CTOF_DEL    ---     0.495      R7C15D.C0 to      R7C15D.F0 cpu0/alu/alu16/SLICE_1209
79 
ROUTE         1     0.958      R7C15D.F0 to      R9C15A.D1 cpu0/alu/alu16/arith_q[5]
80 
CTOOFX_DEL  ---     0.721      R9C15A.D1 to    R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
81 
ROUTE         2     1.285    R9C15A.OFX0 to      R9C22B.C1 cpu0/alu/q16_out[5]
82 
CTOOFX_DEL  ---     0.721      R9C22B.C1 to    R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
83 
ROUTE         2     1.392    R9C22B.OFX0 to     R11C20D.D0 cpu0/datamux_o_dest[5]
84 
CTOF_DEL    ---     0.495     R11C20D.D0 to     R11C20D.F0 cpu0/regs/SLICE_890
85 
ROUTE         9     0.798     R11C20D.F0 to      R9C20D.C1 cpu0/regs/left_1[5]
86 
CTOF_DEL    ---     0.495      R9C20D.C1 to      R9C20D.F1 cpu0/regs/SLICE_1124
87 
ROUTE         1     0.958      R9C20D.F1 to      R8C18A.D1 cpu0/regs/N_284
88 
CTOF_DEL    ---     0.495      R8C18A.D1 to      R8C18A.F1 cpu0/regs/SLICE_900
89 
ROUTE         1     0.626      R8C18A.F1 to      R8C18A.D0 cpu0/regs/SU_16[5]
90 
CTOF_DEL    ---     0.495      R8C18A.D0 to      R8C18A.F0 cpu0/regs/SLICE_900
91 
ROUTE         1     1.079      R8C18A.F0 to     R10C18D.C1 cpu0/regs/SU_210_i1_mux
92 
C1TOFCO_DE  ---     0.889     R10C18D.C1 to    R10C18D.FCO cpu0/regs/SLICE_69
93 
ROUTE         1     0.000    R10C18D.FCO to    R10C19A.FCI cpu0/regs/SU_cry[5]
94 
FCITOFCO_D  ---     0.162    R10C19A.FCI to    R10C19A.FCO cpu0/regs/SLICE_68
95 
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI cpu0/regs/SU_cry[7]
96 
FCITOFCO_D  ---     0.162    R10C19B.FCI to    R10C19B.FCO cpu0/regs/SLICE_67
97 
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI cpu0/regs/SU_cry[9]
98 
FCITOFCO_D  ---     0.162    R10C19C.FCI to    R10C19C.FCO cpu0/regs/SLICE_66
99 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
100 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
101 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
102 
FCITOF1_DE  ---     0.643    R10C20A.FCI to     R10C20A.F1 cpu0/regs/SLICE_64
103 
ROUTE         1     0.000     R10C20A.F1 to    R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
104 
                  --------
105 
                   23.780   (42.8% logic, 57.2% route), 19 logic levels.
106 
 
107 
 Clock Skew Details:
108 
 
109 
      Source Clock Path clk40_i to cpu0/SLICE_229:
110 
 
111 
   Name    Fanout   Delay (ns)          Site               Resource
112 
ROUTE       290     2.399       27.PADDI to    R12C13B.CLK cpu_clkgen
113 
                  --------
114 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
115 
 
116 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
117 
 
118 
   Name    Fanout   Delay (ns)          Site               Resource
119 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
120 
                  --------
121 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
122 
 
123 
 
124 
Passed: The following path meets requirements by 1.057ns
125 
 
126 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
127 
 
128 
   Source:         FF         Q              cpu0/alu/rb_in[8]  (from cpu_clkgen +)
129 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
130 
 
131 
   Delay:              23.777ns  (42.5% logic, 57.5% route), 18 logic levels.
132 
 
133 
 Constraint Details:
134 
 
135 
     23.777ns physical path delay cpu0/SLICE_232 to cpu0/regs/SLICE_64 meets
136 
     25.000ns delay constraint less
137 
      0.000ns skew and
138 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.057ns
139 
 
140 
 Physical Path Details:
141 
 
142 
      Data path cpu0/SLICE_232 to cpu0/regs/SLICE_64:
143 
 
144 
   Name    Fanout   Delay (ns)          Site               Resource
145 
REG_DEL     ---     0.452    R14C16C.CLK to     R14C16C.Q0 cpu0/SLICE_232 (from cpu_clkgen)
146 
ROUTE         6     1.156     R14C16C.Q0 to     R12C15A.C1 cpu0/alu/rb_in[8]
147 
CTOF_DEL    ---     0.495     R12C15A.C1 to     R12C15A.F1 SLICE_394
148 
ROUTE         1     1.299     R12C15A.F1 to     R10C15A.A1 cpu0/alu/alu16/a16/rb_in_i[8]
149 
C1TOFCO_DE  ---     0.889     R10C15A.A1 to    R10C15A.FCO cpu0/alu/alu16/a16/SLICE_95
150 
ROUTE         1     0.000    R10C15A.FCO to    R10C15B.FCI cpu0/alu/alu16/a16/un8_q_out_cry_8
151 
FCITOF1_DE  ---     0.643    R10C15B.FCI to     R10C15B.F1 cpu0/alu/alu16/a16/SLICE_94
152 
ROUTE         1     0.986     R10C15B.F1 to     R11C15D.A0 cpu0/alu/alu16/a16/un8_q_out[10]
153 
CTOF_DEL    ---     0.495     R11C15D.A0 to     R11C15D.F0 cpu0/alu/SLICE_1213
154 
ROUTE         1     1.675     R11C15D.F0 to     R11C22B.C1 cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0
155 
C1TOFCO_DE  ---     0.889     R11C22B.C1 to    R11C22B.FCO cpu0/alu/alu16/a16/SLICE_112
156 
ROUTE         1     0.000    R11C22B.FCO to    R11C22C.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
157 
FCITOF0_DE  ---     0.585    R11C22C.FCI to     R11C22C.F0 cpu0/alu/alu16/a16/SLICE_111
158 
ROUTE         1     1.072     R11C22C.F0 to      R7C22D.D0 cpu0/alu/alu16/a16/N_2324
159 
CTOF_DEL    ---     0.495      R7C22D.D0 to      R7C22D.F0 cpu0/alu/alu16/SLICE_986
160 
ROUTE         1     0.436      R7C22D.F0 to      R7C22D.C1 cpu0/alu/alu16/arith_q[11]
161 
CTOF_DEL    ---     0.495      R7C22D.C1 to      R7C22D.F1 cpu0/alu/alu16/SLICE_986
162 
ROUTE         1     0.958      R7C22D.F1 to     R10C22C.D1 cpu0/alu/alu16/N_2298
163 
CTOF_DEL    ---     0.495     R10C22C.D1 to     R10C22C.F1 cpu0/alu/alu16/SLICE_1001
164 
ROUTE         2     1.032     R10C22C.F1 to     R12C22D.B1 cpu0/alu/q16_out[11]
165 
CTOF_DEL    ---     0.495     R12C22D.B1 to     R12C22D.F1 cpu0/alu/SLICE_1236
166 
ROUTE         2     0.635     R12C22D.F1 to     R12C22A.D1 cpu0/datamux_o_dest[11]
167 
CTOF_DEL    ---     0.495     R12C22A.D1 to     R12C22A.F1 cpu0/regs/SLICE_941
168 
ROUTE         6     1.479     R12C22A.F1 to     R14C19C.D0 cpu0/regs/left_1[11]
169 
CTOF_DEL    ---     0.495     R14C19C.D0 to     R14C19C.F0 cpu0/regs/SLICE_1193
170 
ROUTE         1     1.035     R14C19C.F0 to     R12C19D.D1 cpu0/regs/N_290
171 
CTOF_DEL    ---     0.495     R12C19D.D1 to     R12C19D.F1 cpu0/regs/SLICE_914
172 
ROUTE         1     0.436     R12C19D.F1 to     R12C19D.C0 cpu0/regs/SU_16[11]
173 
CTOF_DEL    ---     0.495     R12C19D.C0 to     R12C19D.F0 cpu0/regs/SLICE_914
174 
ROUTE         1     1.476     R12C19D.F0 to     R10C19C.C1 cpu0/regs/SU_216_i1_mux
175 
C1TOFCO_DE  ---     0.889     R10C19C.C1 to    R10C19C.FCO cpu0/regs/SLICE_66
176 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
177 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
178 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
179 
FCITOF1_DE  ---     0.643    R10C20A.FCI to     R10C20A.F1 cpu0/regs/SLICE_64
180 
ROUTE         1     0.000     R10C20A.F1 to    R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
181 
                  --------
182 
                   23.777   (42.5% logic, 57.5% route), 18 logic levels.
183 
 
184 
 Clock Skew Details:
185 
 
186 
      Source Clock Path clk40_i to cpu0/SLICE_232:
187 
 
188 
   Name    Fanout   Delay (ns)          Site               Resource
189 
ROUTE       290     2.399       27.PADDI to    R14C16C.CLK cpu_clkgen
190 
                  --------
191 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
192 
 
193 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
194 
 
195 
   Name    Fanout   Delay (ns)          Site               Resource
196 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
197 
                  --------
198 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
199 
 
200 
 
201 
Passed: The following path meets requirements by 1.091ns
202 
 
203 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
204 
 
205 
   Source:         FF         Q              cpu0/k_postbyte[4]  (from cpu_clkgen +)
206 
   Destination:    FF         Data in        cpu0/k_cpu_addr[10]  (to cpu_clkgen +)
207 
 
208 
   Delay:              23.743ns  (33.5% logic, 66.5% route), 18 logic levels.
209 
 
210 
 Constraint Details:
211 
 
212 
     23.743ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_201 meets
213 
     25.000ns delay constraint less
214 
      0.000ns skew and
215 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.091ns
216 
 
217 
 Physical Path Details:
218 
 
219 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_201:
220 
 
221 
   Name    Fanout   Delay (ns)          Site               Resource
222 
REG_DEL     ---     0.452    R14C26D.CLK to     R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
223 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
224 
CTOF_DEL    ---     0.495     R14C25D.B1 to     R14C25D.F1 cpu0/dec_op/SLICE_1032
225 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
226 
CTOF_DEL    ---     0.495     R12C26B.A1 to     R12C26B.F1 cpu0/dec_op/SLICE_743
227 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
228 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
229 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
230 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
231 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
232 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
233 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
234 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
235 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
236 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
237 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
238 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
239 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
240 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
241 
ROUTE        33     1.338     R12C24B.F0 to     R10C24A.A1 cpu0/un1_state_122
242 
C1TOFCO_DE  ---     0.889     R10C24A.A1 to    R10C24A.FCO cpu0/SLICE_36
243 
ROUTE         1     0.000    R10C24A.FCO to    R10C24B.FCI cpu0/un1_k_cpu_addr_1_cry_0
244 
FCITOFCO_D  ---     0.162    R10C24B.FCI to    R10C24B.FCO cpu0/SLICE_195
245 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
246 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
247 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
248 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
249 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
250 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
251 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
252 
FCITOF1_DE  ---     0.643    R10C25B.FCI to     R10C25B.F1 cpu0/SLICE_191
253 
ROUTE         1     1.498     R10C25B.F1 to     R12C28C.A0 cpu0/un1_k_cpu_addr_1_cry_9_0_S1
254 
CTOF_DEL    ---     0.495     R12C28C.A0 to     R12C28C.F0 cpu0/SLICE_1059
255 
ROUTE         1     0.958     R12C28C.F0 to     R11C26A.D0 cpu0/regs/ea/un1_k_cpu_addr_1_m[10]
256 
CTOF_DEL    ---     0.495     R11C26A.D0 to     R11C26A.F0 cpu0/SLICE_201
257 
ROUTE         1     0.000     R11C26A.F0 to    R11C26A.DI0 cpu0/k_cpu_addr_28[10] (to cpu_clkgen)
258 
                  --------
259 
                   23.743   (33.5% logic, 66.5% route), 18 logic levels.
260 
 
261 
 Clock Skew Details:
262 
 
263 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
264 
 
265 
   Name    Fanout   Delay (ns)          Site               Resource
266 
ROUTE       290     2.399       27.PADDI to    R14C26D.CLK cpu_clkgen
267 
                  --------
268 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
269 
 
270 
      Destination Clock Path clk40_i to cpu0/SLICE_201:
271 
 
272 
   Name    Fanout   Delay (ns)          Site               Resource
273 
ROUTE       290     2.399       27.PADDI to    R11C26A.CLK cpu_clkgen
274 
                  --------
275 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
276 
 
277 
 
278 
Passed: The following path meets requirements by 1.094ns
279 
 
280 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
281 
 
282 
   Source:         FF         Q              cpu0/k_postbyte[4]  (from cpu_clkgen +)
283 
   Destination:    FF         Data in        cpu0/k_cpu_addr[14]  (to cpu_clkgen +)
284 
 
285 
   Delay:              23.740ns  (34.9% logic, 65.1% route), 20 logic levels.
286 
 
287 
 Constraint Details:
288 
 
289 
     23.740ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_203 meets
290 
     25.000ns delay constraint less
291 
      0.000ns skew and
292 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.094ns
293 
 
294 
 Physical Path Details:
295 
 
296 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_203:
297 
 
298 
   Name    Fanout   Delay (ns)          Site               Resource
299 
REG_DEL     ---     0.452    R14C26D.CLK to     R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
300 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
301 
CTOF_DEL    ---     0.495     R14C25D.B1 to     R14C25D.F1 cpu0/dec_op/SLICE_1032
302 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
303 
CTOF_DEL    ---     0.495     R12C26B.A1 to     R12C26B.F1 cpu0/dec_op/SLICE_743
304 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
305 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
306 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
307 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
308 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
309 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
310 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
311 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
312 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
313 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
314 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
315 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
316 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
317 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
318 
ROUTE        33     1.338     R12C24B.F0 to     R10C24A.A1 cpu0/un1_state_122
319 
C1TOFCO_DE  ---     0.889     R10C24A.A1 to    R10C24A.FCO cpu0/SLICE_36
320 
ROUTE         1     0.000    R10C24A.FCO to    R10C24B.FCI cpu0/un1_k_cpu_addr_1_cry_0
321 
FCITOFCO_D  ---     0.162    R10C24B.FCI to    R10C24B.FCO cpu0/SLICE_195
322 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
323 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
324 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
325 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
326 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
327 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
328 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
329 
FCITOFCO_D  ---     0.162    R10C25B.FCI to    R10C25B.FCO cpu0/SLICE_191
330 
ROUTE         1     0.000    R10C25B.FCO to    R10C25C.FCI cpu0/un1_k_cpu_addr_1_cry_10
331 
FCITOFCO_D  ---     0.162    R10C25C.FCI to    R10C25C.FCO cpu0/SLICE_190
332 
ROUTE         1     0.000    R10C25C.FCO to    R10C25D.FCI cpu0/un1_k_cpu_addr_1_cry_12
333 
FCITOF1_DE  ---     0.643    R10C25D.FCI to     R10C25D.F1 cpu0/SLICE_189
334 
ROUTE         1     1.385     R10C25D.F1 to     R12C28A.D0 cpu0/un1_k_cpu_addr_1_cry_13_0_S1
335 
CTOF_DEL    ---     0.495     R12C28A.D0 to     R12C28A.F0 cpu0/SLICE_1246
336 
ROUTE         1     0.744     R12C28A.F0 to     R12C27A.C0 cpu0/alu/un1_k_cpu_addr_1_m[14]
337 
CTOF_DEL    ---     0.495     R12C27A.C0 to     R12C27A.F0 cpu0/SLICE_203
338 
ROUTE         1     0.000     R12C27A.F0 to    R12C27A.DI0 cpu0/k_cpu_addr_28[14] (to cpu_clkgen)
339 
                  --------
340 
                   23.740   (34.9% logic, 65.1% route), 20 logic levels.
341 
 
342 
 Clock Skew Details:
343 
 
344 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
345 
 
346 
   Name    Fanout   Delay (ns)          Site               Resource
347 
ROUTE       290     2.399       27.PADDI to    R14C26D.CLK cpu_clkgen
348 
                  --------
349 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
350 
 
351 
      Destination Clock Path clk40_i to cpu0/SLICE_203:
352 
 
353 
   Name    Fanout   Delay (ns)          Site               Resource
354 
ROUTE       290     2.399       27.PADDI to    R12C27A.CLK cpu_clkgen
355 
                  --------
356 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
357 
 
358 
 
359 
Passed: The following path meets requirements by 1.111ns
360 
 
361 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
362 
 
363 
   Source:         FF         Q              cpu0/alu/ra_in[0]  (from cpu_clkgen +)
364 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
365 
 
366 
   Delay:              23.723ns  (42.1% logic, 57.9% route), 19 logic levels.
367 
 
368 
 Constraint Details:
369 
 
370 
     23.723ns physical path delay cpu0/SLICE_217 to cpu0/regs/SLICE_64 meets
371 
     25.000ns delay constraint less
372 
      0.000ns skew and
373 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.111ns
374 
 
375 
 Physical Path Details:
376 
 
377 
      Data path cpu0/SLICE_217 to cpu0/regs/SLICE_64:
378 
 
379 
   Name    Fanout   Delay (ns)          Site               Resource
380 
REG_DEL     ---     0.452    R12C15D.CLK to     R12C15D.Q0 cpu0/SLICE_217 (from cpu_clkgen)
381 
ROUTE        27     2.790     R12C15D.Q0 to      R6C24A.A1 cpu0/alu/ra_in[0]
382 
C1TOFCO_DE  ---     0.889      R6C24A.A1 to     R6C24A.FCO cpu0/alu/alu8/a8/SLICE_172
383 
ROUTE         1     0.000     R6C24A.FCO to     R6C24B.FCI cpu0/alu/alu8/a8/q_out_1_cry_0
384 
FCITOF1_DE  ---     0.643     R6C24B.FCI to      R6C24B.F1 cpu0/alu/alu8/a8/SLICE_171
385 
ROUTE         1     1.506      R6C24B.F1 to      R6C22B.C1 cpu0/alu/alu8/a8/q_out_1[2]
386 
C1TOFCO_DE  ---     0.889      R6C22B.C1 to     R6C22B.FCO cpu0/alu/alu8/a8/SLICE_181
387 
ROUTE         1     0.000     R6C22B.FCO to     R6C22C.FCI cpu0/alu/alu8/a8/q_out_1_0_cry_2
388 
FCITOFCO_D  ---     0.162     R6C22C.FCI to     R6C22C.FCO cpu0/alu/alu8/a8/SLICE_180
389 
ROUTE         1     0.000     R6C22C.FCO to     R6C22D.FCI cpu0/alu/alu8/a8/q_out_1_0_cry_4
390 
FCITOF1_DE  ---     0.643     R6C22D.FCI to      R6C22D.F1 cpu0/alu/alu8/a8/SLICE_179
391 
ROUTE         1     2.080      R6C22D.F1 to     R11C17B.C1 cpu0/alu/alu8/a8/N_2393
392 
CTOF_DEL    ---     0.495     R11C17B.C1 to     R11C17B.F1 cpu0/alu/SLICE_1204
393 
ROUTE         1     1.385     R11C17B.F1 to     R12C14C.D0 cpu0/alu/alu8/arith_q[6]
394 
CTOOFX_DEL  ---     0.721     R12C14C.D0 to   R12C14C.OFX0 cpu0/alu/alu8/q_out_4[6]/SLICE_560
395 
ROUTE         1     0.000   R12C14C.OFX0 to    R12C14C.FXB cpu0/alu/alu8/N_159
396 
FXTOOFX_DE  ---     0.241    R12C14C.FXB to   R12C14C.OFX1 cpu0/alu/alu8/q_out_4[6]/SLICE_560
397 
ROUTE         2     1.505   R12C14C.OFX1 to     R12C22C.A1 cpu0/alu/q8_out[6]
398 
CTOOFX_DEL  ---     0.721     R12C22C.A1 to   R12C22C.OFX0 cpu0/alu/alu16/datamux_o_dest[6]/SLICE_541
399 
ROUTE         2     0.772   R12C22C.OFX0 to     R12C21A.C0 cpu0/datamux_o_dest[6]
400 
CTOF_DEL    ---     0.495     R12C21A.C0 to     R12C21A.F0 cpu0/regs/SLICE_889
401 
ROUTE         9     1.224     R12C21A.F0 to     R12C17A.C1 cpu0/regs/left_1[6]
402 
CTOF_DEL    ---     0.495     R12C17A.C1 to     R12C17A.F1 cpu0/regs/SLICE_1125
403 
ROUTE         1     0.958     R12C17A.F1 to     R10C17B.D1 cpu0/regs/N_285
404 
CTOF_DEL    ---     0.495     R10C17B.D1 to     R10C17B.F1 cpu0/regs/SLICE_901
405 
ROUTE         1     0.436     R10C17B.F1 to     R10C17B.C0 cpu0/regs/SU_16[6]
406 
CTOF_DEL    ---     0.495     R10C17B.C0 to     R10C17B.F0 cpu0/regs/SLICE_901
407 
ROUTE         1     1.079     R10C17B.F0 to     R10C19A.C0 cpu0/regs/SU_211_i1_mux
408 
C0TOFCO_DE  ---     1.023     R10C19A.C0 to    R10C19A.FCO cpu0/regs/SLICE_68
409 
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI cpu0/regs/SU_cry[7]
410 
FCITOFCO_D  ---     0.162    R10C19B.FCI to    R10C19B.FCO cpu0/regs/SLICE_67
411 
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI cpu0/regs/SU_cry[9]
412 
FCITOFCO_D  ---     0.162    R10C19C.FCI to    R10C19C.FCO cpu0/regs/SLICE_66
413 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
414 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
415 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
416 
FCITOF1_DE  ---     0.643    R10C20A.FCI to     R10C20A.F1 cpu0/regs/SLICE_64
417 
ROUTE         1     0.000     R10C20A.F1 to    R10C20A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
418 
                  --------
419 
                   23.723   (42.1% logic, 57.9% route), 19 logic levels.
420 
 
421 
 Clock Skew Details:
422 
 
423 
      Source Clock Path clk40_i to cpu0/SLICE_217:
424 
 
425 
   Name    Fanout   Delay (ns)          Site               Resource
426 
ROUTE       290     2.399       27.PADDI to    R12C15D.CLK cpu_clkgen
427 
                  --------
428 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
429 
 
430 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
431 
 
432 
   Name    Fanout   Delay (ns)          Site               Resource
433 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
434 
                  --------
435 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
436 
 
437 
 
438 
Passed: The following path meets requirements by 1.112ns
439 
 
440 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
441 
 
442 
   Source:         FF         Q              cpu0/alu/rb_in[1]  (from cpu_clkgen +)
443 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)
444 
 
445 
   Delay:              23.722ns  (42.7% logic, 57.3% route), 19 logic levels.
446 
 
447 
 Constraint Details:
448 
 
449 
     23.722ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 meets
450 
     25.000ns delay constraint less
451 
      0.000ns skew and
452 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.112ns
453 
 
454 
 Physical Path Details:
455 
 
456 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
457 
 
458 
   Name    Fanout   Delay (ns)          Site               Resource
459 
REG_DEL     ---     0.452    R12C13B.CLK to     R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
460 
ROUTE        26     1.735     R12C13B.Q1 to     R10C14B.A0 cpu0/alu/rb_in[1]
461 
C0TOFCO_DE  ---     1.023     R10C14B.A0 to    R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
462 
ROUTE         1     0.000    R10C14B.FCO to    R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
463 
FCITOF1_DE  ---     0.643    R10C14C.FCI to     R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
464 
ROUTE         1     1.385     R10C14C.F1 to     R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
465 
CTOF_DEL    ---     0.495     R11C17C.D0 to     R11C17C.F0 cpu0/alu/SLICE_1151
466 
ROUTE         1     1.675     R11C17C.F0 to     R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
467 
C1TOFCO_DE  ---     0.889     R11C21C.C1 to    R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
468 
ROUTE         1     0.000    R11C21C.FCO to    R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
469 
FCITOF0_DE  ---     0.585    R11C21D.FCI to     R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
470 
ROUTE         1     1.705     R11C21D.F0 to      R7C15D.C0 cpu0/alu/alu16/a16/N_2261
471 
CTOF_DEL    ---     0.495      R7C15D.C0 to      R7C15D.F0 cpu0/alu/alu16/SLICE_1209
472 
ROUTE         1     0.958      R7C15D.F0 to      R9C15A.D1 cpu0/alu/alu16/arith_q[5]
473 
CTOOFX_DEL  ---     0.721      R9C15A.D1 to    R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
474 
ROUTE         2     1.285    R9C15A.OFX0 to      R9C22B.C1 cpu0/alu/q16_out[5]
475 
CTOOFX_DEL  ---     0.721      R9C22B.C1 to    R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
476 
ROUTE         2     1.392    R9C22B.OFX0 to     R11C20D.D0 cpu0/datamux_o_dest[5]
477 
CTOF_DEL    ---     0.495     R11C20D.D0 to     R11C20D.F0 cpu0/regs/SLICE_890
478 
ROUTE         9     0.798     R11C20D.F0 to      R9C20D.C1 cpu0/regs/left_1[5]
479 
CTOF_DEL    ---     0.495      R9C20D.C1 to      R9C20D.F1 cpu0/regs/SLICE_1124
480 
ROUTE         1     0.958      R9C20D.F1 to      R8C18A.D1 cpu0/regs/N_284
481 
CTOF_DEL    ---     0.495      R8C18A.D1 to      R8C18A.F1 cpu0/regs/SLICE_900
482 
ROUTE         1     0.626      R8C18A.F1 to      R8C18A.D0 cpu0/regs/SU_16[5]
483 
CTOF_DEL    ---     0.495      R8C18A.D0 to      R8C18A.F0 cpu0/regs/SLICE_900
484 
ROUTE         1     1.079      R8C18A.F0 to     R10C18D.C1 cpu0/regs/SU_210_i1_mux
485 
C1TOFCO_DE  ---     0.889     R10C18D.C1 to    R10C18D.FCO cpu0/regs/SLICE_69
486 
ROUTE         1     0.000    R10C18D.FCO to    R10C19A.FCI cpu0/regs/SU_cry[5]
487 
FCITOFCO_D  ---     0.162    R10C19A.FCI to    R10C19A.FCO cpu0/regs/SLICE_68
488 
ROUTE         1     0.000    R10C19A.FCO to    R10C19B.FCI cpu0/regs/SU_cry[7]
489 
FCITOFCO_D  ---     0.162    R10C19B.FCI to    R10C19B.FCO cpu0/regs/SLICE_67
490 
ROUTE         1     0.000    R10C19B.FCO to    R10C19C.FCI cpu0/regs/SU_cry[9]
491 
FCITOFCO_D  ---     0.162    R10C19C.FCI to    R10C19C.FCO cpu0/regs/SLICE_66
492 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
493 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
494 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
495 
FCITOF0_DE  ---     0.585    R10C20A.FCI to     R10C20A.F0 cpu0/regs/SLICE_64
496 
ROUTE         1     0.000     R10C20A.F0 to    R10C20A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
497 
                  --------
498 
                   23.722   (42.7% logic, 57.3% route), 19 logic levels.
499 
 
500 
 Clock Skew Details:
501 
 
502 
      Source Clock Path clk40_i to cpu0/SLICE_229:
503 
 
504 
   Name    Fanout   Delay (ns)          Site               Resource
505 
ROUTE       290     2.399       27.PADDI to    R12C13B.CLK cpu_clkgen
506 
                  --------
507 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
508 
 
509 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
510 
 
511 
   Name    Fanout   Delay (ns)          Site               Resource
512 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
513 
                  --------
514 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
515 
 
516 
 
517 
Passed: The following path meets requirements by 1.112ns
518 
 
519 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
520 
 
521 
   Source:         FF         Q              cpu0/k_postbyte[4]  (from cpu_clkgen +)
522 
   Destination:    FF         Data in        cpu0/k_cpu_addr[10]  (to cpu_clkgen +)
523 
 
524 
   Delay:              23.722ns  (33.4% logic, 66.6% route), 17 logic levels.
525 
 
526 
 Constraint Details:
527 
 
528 
     23.722ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_201 meets
529 
     25.000ns delay constraint less
530 
      0.000ns skew and
531 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.112ns
532 
 
533 
 Physical Path Details:
534 
 
535 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_201:
536 
 
537 
   Name    Fanout   Delay (ns)          Site               Resource
538 
REG_DEL     ---     0.452    R14C26D.CLK to     R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
539 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
540 
CTOF_DEL    ---     0.495     R14C25D.B1 to     R14C25D.F1 cpu0/dec_op/SLICE_1032
541 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
542 
CTOF_DEL    ---     0.495     R12C26B.A1 to     R12C26B.F1 cpu0/dec_op/SLICE_743
543 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
544 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
545 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
546 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
547 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
548 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
549 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
550 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
551 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
552 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
553 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
554 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
555 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
556 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
557 
ROUTE        33     1.345     R12C24B.F0 to     R10C24B.A0 cpu0/un1_state_122
558 
C0TOFCO_DE  ---     1.023     R10C24B.A0 to    R10C24B.FCO cpu0/SLICE_195
559 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
560 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
561 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
562 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
563 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
564 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
565 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
566 
FCITOF1_DE  ---     0.643    R10C25B.FCI to     R10C25B.F1 cpu0/SLICE_191
567 
ROUTE         1     1.498     R10C25B.F1 to     R12C28C.A0 cpu0/un1_k_cpu_addr_1_cry_9_0_S1
568 
CTOF_DEL    ---     0.495     R12C28C.A0 to     R12C28C.F0 cpu0/SLICE_1059
569 
ROUTE         1     0.958     R12C28C.F0 to     R11C26A.D0 cpu0/regs/ea/un1_k_cpu_addr_1_m[10]
570 
CTOF_DEL    ---     0.495     R11C26A.D0 to     R11C26A.F0 cpu0/SLICE_201
571 
ROUTE         1     0.000     R11C26A.F0 to    R11C26A.DI0 cpu0/k_cpu_addr_28[10] (to cpu_clkgen)
572 
                  --------
573 
                   23.722   (33.4% logic, 66.6% route), 17 logic levels.
574 
 
575 
 Clock Skew Details:
576 
 
577 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
578 
 
579 
   Name    Fanout   Delay (ns)          Site               Resource
580 
ROUTE       290     2.399       27.PADDI to    R14C26D.CLK cpu_clkgen
581 
                  --------
582 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
583 
 
584 
      Destination Clock Path clk40_i to cpu0/SLICE_201:
585 
 
586 
   Name    Fanout   Delay (ns)          Site               Resource
587 
ROUTE       290     2.399       27.PADDI to    R11C26A.CLK cpu_clkgen
588 
                  --------
589 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
590 
 
591 
 
592 
Passed: The following path meets requirements by 1.115ns
593 
 
594 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
595 
 
596 
   Source:         FF         Q              cpu0/alu/rb_in[8]  (from cpu_clkgen +)
597 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)
598 
 
599 
   Delay:              23.719ns  (42.3% logic, 57.7% route), 18 logic levels.
600 
 
601 
 Constraint Details:
602 
 
603 
     23.719ns physical path delay cpu0/SLICE_232 to cpu0/regs/SLICE_64 meets
604 
     25.000ns delay constraint less
605 
      0.000ns skew and
606 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.115ns
607 
 
608 
 Physical Path Details:
609 
 
610 
      Data path cpu0/SLICE_232 to cpu0/regs/SLICE_64:
611 
 
612 
   Name    Fanout   Delay (ns)          Site               Resource
613 
REG_DEL     ---     0.452    R14C16C.CLK to     R14C16C.Q0 cpu0/SLICE_232 (from cpu_clkgen)
614 
ROUTE         6     1.156     R14C16C.Q0 to     R12C15A.C1 cpu0/alu/rb_in[8]
615 
CTOF_DEL    ---     0.495     R12C15A.C1 to     R12C15A.F1 SLICE_394
616 
ROUTE         1     1.299     R12C15A.F1 to     R10C15A.A1 cpu0/alu/alu16/a16/rb_in_i[8]
617 
C1TOFCO_DE  ---     0.889     R10C15A.A1 to    R10C15A.FCO cpu0/alu/alu16/a16/SLICE_95
618 
ROUTE         1     0.000    R10C15A.FCO to    R10C15B.FCI cpu0/alu/alu16/a16/un8_q_out_cry_8
619 
FCITOF1_DE  ---     0.643    R10C15B.FCI to     R10C15B.F1 cpu0/alu/alu16/a16/SLICE_94
620 
ROUTE         1     0.986     R10C15B.F1 to     R11C15D.A0 cpu0/alu/alu16/a16/un8_q_out[10]
621 
CTOF_DEL    ---     0.495     R11C15D.A0 to     R11C15D.F0 cpu0/alu/SLICE_1213
622 
ROUTE         1     1.675     R11C15D.F0 to     R11C22B.C1 cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0
623 
C1TOFCO_DE  ---     0.889     R11C22B.C1 to    R11C22B.FCO cpu0/alu/alu16/a16/SLICE_112
624 
ROUTE         1     0.000    R11C22B.FCO to    R11C22C.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
625 
FCITOF0_DE  ---     0.585    R11C22C.FCI to     R11C22C.F0 cpu0/alu/alu16/a16/SLICE_111
626 
ROUTE         1     1.072     R11C22C.F0 to      R7C22D.D0 cpu0/alu/alu16/a16/N_2324
627 
CTOF_DEL    ---     0.495      R7C22D.D0 to      R7C22D.F0 cpu0/alu/alu16/SLICE_986
628 
ROUTE         1     0.436      R7C22D.F0 to      R7C22D.C1 cpu0/alu/alu16/arith_q[11]
629 
CTOF_DEL    ---     0.495      R7C22D.C1 to      R7C22D.F1 cpu0/alu/alu16/SLICE_986
630 
ROUTE         1     0.958      R7C22D.F1 to     R10C22C.D1 cpu0/alu/alu16/N_2298
631 
CTOF_DEL    ---     0.495     R10C22C.D1 to     R10C22C.F1 cpu0/alu/alu16/SLICE_1001
632 
ROUTE         2     1.032     R10C22C.F1 to     R12C22D.B1 cpu0/alu/q16_out[11]
633 
CTOF_DEL    ---     0.495     R12C22D.B1 to     R12C22D.F1 cpu0/alu/SLICE_1236
634 
ROUTE         2     0.635     R12C22D.F1 to     R12C22A.D1 cpu0/datamux_o_dest[11]
635 
CTOF_DEL    ---     0.495     R12C22A.D1 to     R12C22A.F1 cpu0/regs/SLICE_941
636 
ROUTE         6     1.479     R12C22A.F1 to     R14C19C.D0 cpu0/regs/left_1[11]
637 
CTOF_DEL    ---     0.495     R14C19C.D0 to     R14C19C.F0 cpu0/regs/SLICE_1193
638 
ROUTE         1     1.035     R14C19C.F0 to     R12C19D.D1 cpu0/regs/N_290
639 
CTOF_DEL    ---     0.495     R12C19D.D1 to     R12C19D.F1 cpu0/regs/SLICE_914
640 
ROUTE         1     0.436     R12C19D.F1 to     R12C19D.C0 cpu0/regs/SU_16[11]
641 
CTOF_DEL    ---     0.495     R12C19D.C0 to     R12C19D.F0 cpu0/regs/SLICE_914
642 
ROUTE         1     1.476     R12C19D.F0 to     R10C19C.C1 cpu0/regs/SU_216_i1_mux
643 
C1TOFCO_DE  ---     0.889     R10C19C.C1 to    R10C19C.FCO cpu0/regs/SLICE_66
644 
ROUTE         1     0.000    R10C19C.FCO to    R10C19D.FCI cpu0/regs/SU_cry[11]
645 
FCITOFCO_D  ---     0.162    R10C19D.FCI to    R10C19D.FCO cpu0/regs/SLICE_65
646 
ROUTE         1     0.000    R10C19D.FCO to    R10C20A.FCI cpu0/regs/SU_cry[13]
647 
FCITOF0_DE  ---     0.585    R10C20A.FCI to     R10C20A.F0 cpu0/regs/SLICE_64
648 
ROUTE         1     0.000     R10C20A.F0 to    R10C20A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
649 
                  --------
650 
                   23.719   (42.3% logic, 57.7% route), 18 logic levels.
651 
 
652 
 Clock Skew Details:
653 
 
654 
      Source Clock Path clk40_i to cpu0/SLICE_232:
655 
 
656 
   Name    Fanout   Delay (ns)          Site               Resource
657 
ROUTE       290     2.399       27.PADDI to    R14C16C.CLK cpu_clkgen
658 
                  --------
659 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
660 
 
661 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
662 
 
663 
   Name    Fanout   Delay (ns)          Site               Resource
664 
ROUTE       290     2.399       27.PADDI to    R10C20A.CLK cpu_clkgen
665 
                  --------
666 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
667 
 
668 
 
669 
Passed: The following path meets requirements by 1.115ns
670 
 
671 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
672 
 
673 
   Source:         FF         Q              cpu0/k_postbyte[4]  (from cpu_clkgen +)
674 
   Destination:    FF         Data in        cpu0/k_cpu_addr[14]  (to cpu_clkgen +)
675 
 
676 
   Delay:              23.719ns  (34.8% logic, 65.2% route), 19 logic levels.
677 
 
678 
 Constraint Details:
679 
 
680 
     23.719ns physical path delay cpu0/SLICE_1133 to cpu0/SLICE_203 meets
681 
     25.000ns delay constraint less
682 
      0.000ns skew and
683 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.115ns
684 
 
685 
 Physical Path Details:
686 
 
687 
      Data path cpu0/SLICE_1133 to cpu0/SLICE_203:
688 
 
689 
   Name    Fanout   Delay (ns)          Site               Resource
690 
REG_DEL     ---     0.452    R14C26D.CLK to     R14C26D.Q0 cpu0/SLICE_1133 (from cpu_clkgen)
691 
ROUTE        21     1.473     R14C26D.Q0 to     R14C25D.B1 cpu0/k_postbyte[4]
692 
CTOF_DEL    ---     0.495     R14C25D.B1 to     R14C25D.F1 cpu0/dec_op/SLICE_1032
693 
ROUTE         1     1.525     R14C25D.F1 to     R12C26B.A1 cpu0/dec_op/mode76_0
694 
CTOF_DEL    ---     0.495     R12C26B.A1 to     R12C26B.F1 cpu0/dec_op/SLICE_743
695 
ROUTE         3     0.984     R12C26B.F1 to     R12C26B.A0 cpu0/dec_op/mode76
696 
CTOF_DEL    ---     0.495     R12C26B.A0 to     R12C26B.F0 cpu0/dec_op/SLICE_743
697 
ROUTE         1     1.022     R12C26B.F0 to     R14C26C.D0 cpu0/dec_op/mode_8_sqmuxa_1_93_2
698 
CTOF_DEL    ---     0.495     R14C26C.D0 to     R14C26C.F0 cpu0/dec_op/SLICE_739
699 
ROUTE         2     0.632     R14C26C.F0 to     R14C27B.D1 cpu0/dec_op/N_290
700 
CTOF_DEL    ---     0.495     R14C27B.D1 to     R14C27B.F1 cpu0/dec_op/SLICE_700
701 
ROUTE         3     2.174     R14C27B.F1 to     R15C27B.M0 cpu0/dec_op/un1_mode93
702 
MTOOFX_DEL  ---     0.376     R15C27B.M0 to   R15C27B.OFX0 cpu0/dec_op/un1_mode93_RNIMJAL1/SLICE_420
703 
ROUTE         5     2.393   R15C27B.OFX0 to     R14C23C.B0 cpu0/mode_7[2]
704 
CTOF_DEL    ---     0.495     R14C23C.B0 to     R14C23C.F0 cpu0/SLICE_592
705 
ROUTE        11     0.635     R14C23C.F0 to     R14C23D.D0 cpu0/state81
706 
CTOF_DEL    ---     0.495     R14C23D.D0 to     R14C23D.F0 cpu0/dec_op/SLICE_718
707 
ROUTE         3     1.153     R14C23D.F0 to     R12C24B.D0 cpu0/un1_cpu_reset_11
708 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/SLICE_593
709 
ROUTE        33     1.345     R12C24B.F0 to     R10C24B.A0 cpu0/un1_state_122
710 
C0TOFCO_DE  ---     1.023     R10C24B.A0 to    R10C24B.FCO cpu0/SLICE_195
711 
ROUTE         1     0.000    R10C24B.FCO to    R10C24C.FCI cpu0/un1_k_cpu_addr_1_cry_2
712 
FCITOFCO_D  ---     0.162    R10C24C.FCI to    R10C24C.FCO cpu0/SLICE_194
713 
ROUTE         1     0.000    R10C24C.FCO to    R10C24D.FCI cpu0/un1_k_cpu_addr_1_cry_4
714 
FCITOFCO_D  ---     0.162    R10C24D.FCI to    R10C24D.FCO cpu0/SLICE_193
715 
ROUTE         1     0.000    R10C24D.FCO to    R10C25A.FCI cpu0/un1_k_cpu_addr_1_cry_6
716 
FCITOFCO_D  ---     0.162    R10C25A.FCI to    R10C25A.FCO cpu0/SLICE_192
717 
ROUTE         1     0.000    R10C25A.FCO to    R10C25B.FCI cpu0/un1_k_cpu_addr_1_cry_8
718 
FCITOFCO_D  ---     0.162    R10C25B.FCI to    R10C25B.FCO cpu0/SLICE_191
719 
ROUTE         1     0.000    R10C25B.FCO to    R10C25C.FCI cpu0/un1_k_cpu_addr_1_cry_10
720 
FCITOFCO_D  ---     0.162    R10C25C.FCI to    R10C25C.FCO cpu0/SLICE_190
721 
ROUTE         1     0.000    R10C25C.FCO to    R10C25D.FCI cpu0/un1_k_cpu_addr_1_cry_12
722 
FCITOF1_DE  ---     0.643    R10C25D.FCI to     R10C25D.F1 cpu0/SLICE_189
723 
ROUTE         1     1.385     R10C25D.F1 to     R12C28A.D0 cpu0/un1_k_cpu_addr_1_cry_13_0_S1
724 
CTOF_DEL    ---     0.495     R12C28A.D0 to     R12C28A.F0 cpu0/SLICE_1246
725 
ROUTE         1     0.744     R12C28A.F0 to     R12C27A.C0 cpu0/alu/un1_k_cpu_addr_1_m[14]
726 
CTOF_DEL    ---     0.495     R12C27A.C0 to     R12C27A.F0 cpu0/SLICE_203
727 
ROUTE         1     0.000     R12C27A.F0 to    R12C27A.DI0 cpu0/k_cpu_addr_28[14] (to cpu_clkgen)
728 
                  --------
729 
                   23.719   (34.8% logic, 65.2% route), 19 logic levels.
730 
 
731 
 Clock Skew Details:
732 
 
733 
      Source Clock Path clk40_i to cpu0/SLICE_1133:
734 
 
735 
   Name    Fanout   Delay (ns)          Site               Resource
736 
ROUTE       290     2.399       27.PADDI to    R14C26D.CLK cpu_clkgen
737 
                  --------
738 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
739 
 
740 
      Destination Clock Path clk40_i to cpu0/SLICE_203:
741 
 
742 
   Name    Fanout   Delay (ns)          Site               Resource
743 
ROUTE       290     2.399       27.PADDI to    R12C27A.CLK cpu_clkgen
744 
                  --------
745 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
746 
 
747 
 
748 
Passed: The following path meets requirements by 1.149ns
749 
 
750 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
751 
 
752 
   Source:         FF         Q              cpu0/alu/rb_in[1]  (from cpu_clkgen +)
753 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to cpu_clkgen +)
754 
 
755 
   Delay:              23.685ns  (43.0% logic, 57.0% route), 19 logic levels.
756 
 
757 
 Constraint Details:
758 
 
759 
     23.685ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_73 meets
760 
     25.000ns delay constraint less
761 
      0.000ns skew and
762 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 1.149ns
763 
 
764 
 Physical Path Details:
765 
 
766 
      Data path cpu0/SLICE_229 to cpu0/regs/SLICE_73:
767 
 
768 
   Name    Fanout   Delay (ns)          Site               Resource
769 
REG_DEL     ---     0.452    R12C13B.CLK to     R12C13B.Q1 cpu0/SLICE_229 (from cpu_clkgen)
770 
ROUTE        26     1.735     R12C13B.Q1 to     R10C14B.A0 cpu0/alu/rb_in[1]
771 
C0TOFCO_DE  ---     1.023     R10C14B.A0 to    R10C14B.FCO cpu0/alu/alu16/a16/SLICE_98
772 
ROUTE         1     0.000    R10C14B.FCO to    R10C14C.FCI cpu0/alu/alu16/a16/un8_q_out_cry_2
773 
FCITOF1_DE  ---     0.643    R10C14C.FCI to     R10C14C.F1 cpu0/alu/alu16/a16/SLICE_97
774 
ROUTE         1     1.385     R10C14C.F1 to     R11C17C.D0 cpu0/alu/alu16/a16/un8_q_out[4]
775 
CTOF_DEL    ---     0.495     R11C17C.D0 to     R11C17C.F0 cpu0/alu/SLICE_1151
776 
ROUTE         1     1.675     R11C17C.F0 to     R11C21C.C1 cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO_0_0
777 
C1TOFCO_DE  ---     0.889     R11C21C.C1 to    R11C21C.FCO cpu0/alu/alu16/a16/SLICE_115
778 
ROUTE         1     0.000    R11C21C.FCO to    R11C21D.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
779 
FCITOF0_DE  ---     0.585    R11C21D.FCI to     R11C21D.F0 cpu0/alu/alu16/a16/SLICE_114
780 
ROUTE         1     1.705     R11C21D.F0 to      R7C15D.C0 cpu0/alu/alu16/a16/N_2261
781 
CTOF_DEL    ---     0.495      R7C15D.C0 to      R7C15D.F0 cpu0/alu/alu16/SLICE_1209
782 
ROUTE         1     0.958      R7C15D.F0 to      R9C15A.D1 cpu0/alu/alu16/arith_q[5]
783 
CTOOFX_DEL  ---     0.721      R9C15A.D1 to    R9C15A.OFX0 cpu0/alu/alu16/q_out[5]/SLICE_537
784 
ROUTE         2     1.285    R9C15A.OFX0 to      R9C22B.C1 cpu0/alu/q16_out[5]
785 
CTOOFX_DEL  ---     0.721      R9C22B.C1 to    R9C22B.OFX0 cpu0/alu/alu16/datamux_o_dest[5]/SLICE_540
786 
ROUTE         2     1.392    R9C22B.OFX0 to     R11C20D.D0 cpu0/datamux_o_dest[5]
787 
CTOF_DEL    ---     0.495     R11C20D.D0 to     R11C20D.F0 cpu0/regs/SLICE_890
788 
ROUTE         9     0.798     R11C20D.F0 to      R9C20D.C0 cpu0/regs/left_1[5]
789 
CTOF_DEL    ---     0.495      R9C20D.C0 to      R9C20D.F0 cpu0/regs/SLICE_1124
790 
ROUTE         1     0.626      R9C20D.F0 to      R9C20B.D1 cpu0/regs/N_248
791 
CTOF_DEL    ---     0.495      R9C20B.D1 to      R9C20B.F1 cpu0/regs/SLICE_908
792 
ROUTE         1     0.436      R9C20B.F1 to      R9C20B.C0 cpu0/regs/SS_16[5]
793 
CTOF_DEL    ---     0.495      R9C20B.C0 to      R9C20B.F0 cpu0/regs/SLICE_908
794 
ROUTE         1     1.506      R9C20B.F0 to     R11C18D.C1 cpu0/regs/SS_226_i1_mux
795 
C1TOFCO_DE  ---     0.889     R11C18D.C1 to    R11C18D.FCO cpu0/regs/SLICE_78
796 
ROUTE         1     0.000    R11C18D.FCO to    R11C19A.FCI cpu0/regs/SS_cry[5]
797 
FCITOFCO_D  ---     0.162    R11C19A.FCI to    R11C19A.FCO cpu0/regs/SLICE_77
798 
ROUTE         1     0.000    R11C19A.FCO to    R11C19B.FCI cpu0/regs/SS_cry[7]
799 
FCITOFCO_D  ---     0.162    R11C19B.FCI to    R11C19B.FCO cpu0/regs/SLICE_76
800 
ROUTE         1     0.000    R11C19B.FCO to    R11C19C.FCI cpu0/regs/SS_cry[9]
801 
FCITOFCO_D  ---     0.162    R11C19C.FCI to    R11C19C.FCO cpu0/regs/SLICE_75
802 
ROUTE         1     0.000    R11C19C.FCO to    R11C19D.FCI cpu0/regs/SS_cry[11]
803 
FCITOFCO_D  ---     0.162    R11C19D.FCI to    R11C19D.FCO cpu0/regs/SLICE_74
804 
ROUTE         1     0.000    R11C19D.FCO to    R11C20A.FCI cpu0/regs/SS_cry[13]
805 
FCITOF1_DE  ---     0.643    R11C20A.FCI to     R11C20A.F1 cpu0/regs/SLICE_73
806 
ROUTE         1     0.000     R11C20A.F1 to    R11C20A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
807 
                  --------
808 
                   23.685   (43.0% logic, 57.0% route), 19 logic levels.
809 
 
810 
 Clock Skew Details:
811 
 
812 
      Source Clock Path clk40_i to cpu0/SLICE_229:
813 
 
814 
   Name    Fanout   Delay (ns)          Site               Resource
815 
ROUTE       290     2.399       27.PADDI to    R12C13B.CLK cpu_clkgen
816 
                  --------
817 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
818 
 
819 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_73:
820 
 
821 
   Name    Fanout   Delay (ns)          Site               Resource
822 
ROUTE       290     2.399       27.PADDI to    R11C20A.CLK cpu_clkgen
823 
                  --------
824 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
825 
 
826 
Report:   41.761MHz is the maximum frequency for this preference.
827 
 
828 
Report Summary
829 
--------------
830 
----------------------------------------------------------------------------
831 
Preference                              |   Constraint|       Actual|Levels
832 
----------------------------------------------------------------------------
833 
                                        |             |             |
834 
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
835 
MHz ;                                   |   40.000 MHz|   41.761 MHz|  19
836 
                                        |             |             |
837 
----------------------------------------------------------------------------
838 
 
839 
 
840 
All preferences were met.
841 
 
842 
 
843 
Clock Domains Analysis
844 
------------------------
845 
 
846 
Found 1 clocks:
847 
 
848 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 290
849 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
850 
 
851 
 
852 
Timing summary (Setup):
853 
---------------
854 
 
855 
Timing errors: 0  Score: 0
856 
Cumulative negative slack: 0
857 
 
858 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
859 
 
860 
--------------------------------------------------------------------------------
861 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
862 
Mon Jan  6 06:55:04 2014
863 
 
864 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
865 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
866 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
867 
Copyright (c) 2001 Agere Systems   All rights reserved.
868 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
869 
 
870 
Report Information
871 
------------------
872 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
873 
Design file:     P6809_P6809.ncd
874 
Preference file: P6809_P6809.prf
875 
Device,speed:    LCMXO2-7000HE,m
876 
Report level:    verbose report, limited to 10 items per preference
877 
--------------------------------------------------------------------------------
878 
 
879 
BLOCK ASYNCPATHS
880 
BLOCK RESETPATHS
881 
--------------------------------------------------------------------------------
882 
 
883 
 
884 
 
885 
================================================================================
886 
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
887 
            4096 items scored, 0 timing errors detected.
888 
--------------------------------------------------------------------------------
889 
 
890 
 
891 
Passed: The following path meets requirements by 0.180ns
892 
 
893 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
894 
 
895 
   Source:         FF         Q              cpu0/k_cpu_addr[5]  (from cpu_clkgen +)
896 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_3_0(ASIC)  (to cpu_clkgen +)
897 
 
898 
   Delay:               0.304ns  (43.1% logic, 56.9% route), 1 logic levels.
899 
 
900 
 Constraint Details:
901 
 
902 
      0.304ns physical path delay cpu0/SLICE_198 to textctrl/chars/textmem4k_0_3_0 meets
903 
      0.071ns ADDR_HLD and
904 
      0.000ns delay constraint less
905 
     -0.053ns skew requirement (totaling 0.124ns) by 0.180ns
906 
 
907 
 Physical Path Details:
908 
 
909 
      Data path cpu0/SLICE_198 to textctrl/chars/textmem4k_0_3_0:
910 
 
911 
   Name    Fanout   Delay (ns)          Site               Resource
912 
REG_DEL     ---     0.131    R12C28D.CLK to     R12C28D.Q1 cpu0/SLICE_198 (from cpu_clkgen)
913 
ROUTE         8     0.173     R12C28D.Q1 to *R_R13C27.ADB6 addr_o_c[5] (to cpu_clkgen)
914 
                  --------
915 
                    0.304   (43.1% logic, 56.9% route), 1 logic levels.
916 
 
917 
 Clock Skew Details:
918 
 
919 
      Source Clock Path clk40_i to cpu0/SLICE_198:
920 
 
921 
   Name    Fanout   Delay (ns)          Site               Resource
922 
ROUTE       290     0.846       27.PADDI to    R12C28D.CLK cpu_clkgen
923 
                  --------
924 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
925 
 
926 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_3_0:
927 
 
928 
   Name    Fanout   Delay (ns)          Site               Resource
929 
ROUTE       290     0.899       27.PADDI to *R_R13C27.CLKB cpu_clkgen
930 
                  --------
931 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
932 
 
933 
 
934 
Passed: The following path meets requirements by 0.261ns
935 
 
936 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
937 
 
938 
   Source:         FF         Q              cpu0/k_cpu_addr[11]  (from cpu_clkgen +)
939 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to cpu_clkgen +)
940 
 
941 
   Delay:               0.385ns  (34.0% logic, 66.0% route), 1 logic levels.
942 
 
943 
 Constraint Details:
944 
 
945 
      0.385ns physical path delay cpu0/SLICE_201 to textctrl/chars/textmem4k_0_2_1 meets
946 
      0.071ns ADDR_HLD and
947 
      0.000ns delay constraint less
948 
     -0.053ns skew requirement (totaling 0.124ns) by 0.261ns
949 
 
950 
 Physical Path Details:
951 
 
952 
      Data path cpu0/SLICE_201 to textctrl/chars/textmem4k_0_2_1:
953 
 
954 
   Name    Fanout   Delay (ns)          Site               Resource
955 
REG_DEL     ---     0.131    R11C26A.CLK to     R11C26A.Q1 cpu0/SLICE_201 (from cpu_clkgen)
956 
ROUTE         6     0.254     R11C26A.Q1 to *_R13C24.ADB12 addr_o_c[11] (to cpu_clkgen)
957 
                  --------
958 
                    0.385   (34.0% logic, 66.0% route), 1 logic levels.
959 
 
960 
 Clock Skew Details:
961 
 
962 
      Source Clock Path clk40_i to cpu0/SLICE_201:
963 
 
964 
   Name    Fanout   Delay (ns)          Site               Resource
965 
ROUTE       290     0.846       27.PADDI to    R11C26A.CLK cpu_clkgen
966 
                  --------
967 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
968 
 
969 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
970 
 
971 
   Name    Fanout   Delay (ns)          Site               Resource
972 
ROUTE       290     0.899       27.PADDI to *R_R13C24.CLKB cpu_clkgen
973 
                  --------
974 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
975 
 
976 
 
977 
Passed: The following path meets requirements by 0.297ns
978 
 
979 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
980 
 
981 
   Source:         FF         Q              cpu0/k_cpu_addr[6]  (from cpu_clkgen +)
982 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to cpu_clkgen +)
983 
 
984 
   Delay:               0.421ns  (31.1% logic, 68.9% route), 1 logic levels.
985 
 
986 
 Constraint Details:
987 
 
988 
      0.421ns physical path delay cpu0/SLICE_199 to textctrl/chars/textmem4k_0_2_1 meets
989 
      0.071ns ADDR_HLD and
990 
      0.000ns delay constraint less
991 
     -0.053ns skew requirement (totaling 0.124ns) by 0.297ns
992 
 
993 
 Physical Path Details:
994 
 
995 
      Data path cpu0/SLICE_199 to textctrl/chars/textmem4k_0_2_1:
996 
 
997 
   Name    Fanout   Delay (ns)          Site               Resource
998 
REG_DEL     ---     0.131    R11C25D.CLK to     R11C25D.Q0 cpu0/SLICE_199 (from cpu_clkgen)
999 
ROUTE         8     0.290     R11C25D.Q0 to *R_R13C24.ADB7 addr_o_c[6] (to cpu_clkgen)
1000 
                  --------
1001 
                    0.421   (31.1% logic, 68.9% route), 1 logic levels.
1002 
 
1003 
 Clock Skew Details:
1004 
 
1005 
      Source Clock Path clk40_i to cpu0/SLICE_199:
1006 
 
1007 
   Name    Fanout   Delay (ns)          Site               Resource
1008 
ROUTE       290     0.846       27.PADDI to    R11C25D.CLK cpu_clkgen
1009 
                  --------
1010 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1011 
 
1012 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1013 
 
1014 
   Name    Fanout   Delay (ns)          Site               Resource
1015 
ROUTE       290     0.899       27.PADDI to *R_R13C24.CLKB cpu_clkgen
1016 
                  --------
1017 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1018 
 
1019 
 
1020 
Passed: The following path meets requirements by 0.301ns
1021 
 
1022 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1023 
 
1024 
   Source:         FF         Q              cpu0/alu/alu16/mulu/pipe0[0]  (from cpu_clkgen +)
1025 
   Destination:    FF         Data in        cpu0/alu/alu16/mulu/pipe1[0]  (to cpu_clkgen +)
1026 
 
1027 
   Delay:               0.282ns  (46.5% logic, 53.5% route), 1 logic levels.
1028 
 
1029 
 Constraint Details:
1030 
 
1031 
      0.282ns physical path delay cpu0/alu/alu16/mulu/SLICE_210 to cpu0/alu/alu16/mulu/SLICE_133 meets
1032 
     -0.019ns M_HLD and
1033 
      0.000ns delay constraint less
1034 
      0.000ns skew requirement (totaling -0.019ns) by 0.301ns
1035 
 
1036 
 Physical Path Details:
1037 
 
1038 
      Data path cpu0/alu/alu16/mulu/SLICE_210 to cpu0/alu/alu16/mulu/SLICE_133:
1039 
 
1040 
   Name    Fanout   Delay (ns)          Site               Resource
1041 
REG_DEL     ---     0.131     R8C12C.CLK to      R8C12C.Q0 cpu0/alu/alu16/mulu/SLICE_210 (from cpu_clkgen)
1042 
ROUTE         2     0.151      R8C12C.Q0 to      R8C12A.M1 cpu0/alu/alu16/mulu/pipe0[0] (to cpu_clkgen)
1043 
                  --------
1044 
                    0.282   (46.5% logic, 53.5% route), 1 logic levels.
1045 
 
1046 
 Clock Skew Details:
1047 
 
1048 
      Source Clock Path clk40_i to cpu0/alu/alu16/mulu/SLICE_210:
1049 
 
1050 
   Name    Fanout   Delay (ns)          Site               Resource
1051 
ROUTE       290     0.846       27.PADDI to     R8C12C.CLK cpu_clkgen
1052 
                  --------
1053 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1054 
 
1055 
      Destination Clock Path clk40_i to cpu0/alu/alu16/mulu/SLICE_133:
1056 
 
1057 
   Name    Fanout   Delay (ns)          Site               Resource
1058 
ROUTE       290     0.846       27.PADDI to     R8C12A.CLK cpu_clkgen
1059 
                  --------
1060 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1061 
 
1062 
 
1063 
Passed: The following path meets requirements by 0.364ns
1064 
 
1065 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1066 
 
1067 
   Source:         FF         Q              cpu0/k_cpu_addr[10]  (from cpu_clkgen +)
1068 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_3_0(ASIC)  (to cpu_clkgen +)
1069 
 
1070 
   Delay:               0.488ns  (26.8% logic, 73.2% route), 1 logic levels.
1071 
 
1072 
 Constraint Details:
1073 
 
1074 
      0.488ns physical path delay cpu0/SLICE_201 to textctrl/chars/textmem4k_0_3_0 meets
1075 
      0.071ns ADDR_HLD and
1076 
      0.000ns delay constraint less
1077 
     -0.053ns skew requirement (totaling 0.124ns) by 0.364ns
1078 
 
1079 
 Physical Path Details:
1080 
 
1081 
      Data path cpu0/SLICE_201 to textctrl/chars/textmem4k_0_3_0:
1082 
 
1083 
   Name    Fanout   Delay (ns)          Site               Resource
1084 
REG_DEL     ---     0.131    R11C26A.CLK to     R11C26A.Q0 cpu0/SLICE_201 (from cpu_clkgen)
1085 
ROUTE         8     0.357     R11C26A.Q0 to *_R13C27.ADB11 addr_o_c[10] (to cpu_clkgen)
1086 
                  --------
1087 
                    0.488   (26.8% logic, 73.2% route), 1 logic levels.
1088 
 
1089 
 Clock Skew Details:
1090 
 
1091 
      Source Clock Path clk40_i to cpu0/SLICE_201:
1092 
 
1093 
   Name    Fanout   Delay (ns)          Site               Resource
1094 
ROUTE       290     0.846       27.PADDI to    R11C26A.CLK cpu_clkgen
1095 
                  --------
1096 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1097 
 
1098 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_3_0:
1099 
 
1100 
   Name    Fanout   Delay (ns)          Site               Resource
1101 
ROUTE       290     0.899       27.PADDI to *R_R13C27.CLKB cpu_clkgen
1102 
                  --------
1103 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1104 
 
1105 
 
1106 
Passed: The following path meets requirements by 0.370ns
1107 
 
1108 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1109 
 
1110 
   Source:         FF         Q              textctrl/blink_cnt[0]  (from cpu_clkgen +)
1111 
   Destination:    FF         Data in        textctrl/blink_cnt[0]  (to cpu_clkgen +)
1112 
 
1113 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1114 
 
1115 
 Constraint Details:
1116 
 
1117 
      0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
1118 
     -0.013ns DIN_HLD and
1119 
      0.000ns delay constraint less
1120 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1121 
 
1122 
 Physical Path Details:
1123 
 
1124 
      Data path textctrl/SLICE_29 to textctrl/SLICE_29:
1125 
 
1126 
   Name    Fanout   Delay (ns)          Site               Resource
1127 
REG_DEL     ---     0.131    R23C32A.CLK to     R23C32A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
1128 
ROUTE         1     0.127     R23C32A.Q1 to     R23C32A.A1 textctrl/blink_cnt[0]
1129 
CTOF_DEL    ---     0.099     R23C32A.A1 to     R23C32A.F1 textctrl/SLICE_29
1130 
ROUTE         1     0.000     R23C32A.F1 to    R23C32A.DI1 textctrl/blink_cnt_s[0] (to cpu_clkgen)
1131 
                  --------
1132 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1133 
 
1134 
 Clock Skew Details:
1135 
 
1136 
      Source Clock Path clk40_i to textctrl/SLICE_29:
1137 
 
1138 
   Name    Fanout   Delay (ns)          Site               Resource
1139 
ROUTE       290     0.828       27.PADDI to    R23C32A.CLK cpu_clkgen
1140 
                  --------
1141 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1142 
 
1143 
      Destination Clock Path clk40_i to textctrl/SLICE_29:
1144 
 
1145 
   Name    Fanout   Delay (ns)          Site               Resource
1146 
ROUTE       290     0.828       27.PADDI to    R23C32A.CLK cpu_clkgen
1147 
                  --------
1148 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1149 
 
1150 
 
1151 
Passed: The following path meets requirements by 0.370ns
1152 
 
1153 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1154 
 
1155 
   Source:         FF         Q              textctrl/blink_cnt[1]  (from cpu_clkgen +)
1156 
   Destination:    FF         Data in        textctrl/blink_cnt[1]  (to cpu_clkgen +)
1157 
 
1158 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1159 
 
1160 
 Constraint Details:
1161 
 
1162 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1163 
     -0.013ns DIN_HLD and
1164 
      0.000ns delay constraint less
1165 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1166 
 
1167 
 Physical Path Details:
1168 
 
1169 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1170 
 
1171 
   Name    Fanout   Delay (ns)          Site               Resource
1172 
REG_DEL     ---     0.131    R23C32B.CLK to     R23C32B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
1173 
ROUTE         1     0.127     R23C32B.Q0 to     R23C32B.A0 textctrl/blink_cnt[1]
1174 
CTOF_DEL    ---     0.099     R23C32B.A0 to     R23C32B.F0 textctrl/SLICE_28
1175 
ROUTE         1     0.000     R23C32B.F0 to    R23C32B.DI0 textctrl/blink_cnt_s[1] (to cpu_clkgen)
1176 
                  --------
1177 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1178 
 
1179 
 Clock Skew Details:
1180 
 
1181 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1182 
 
1183 
   Name    Fanout   Delay (ns)          Site               Resource
1184 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1185 
                  --------
1186 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1187 
 
1188 
      Destination Clock Path clk40_i to textctrl/SLICE_28:
1189 
 
1190 
   Name    Fanout   Delay (ns)          Site               Resource
1191 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1192 
                  --------
1193 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1194 
 
1195 
 
1196 
Passed: The following path meets requirements by 0.370ns
1197 
 
1198 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1199 
 
1200 
   Source:         FF         Q              textctrl/blink_cnt[3]  (from cpu_clkgen +)
1201 
   Destination:    FF         Data in        textctrl/blink_cnt[3]  (to cpu_clkgen +)
1202 
 
1203 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1204 
 
1205 
 Constraint Details:
1206 
 
1207 
      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
1208 
     -0.013ns DIN_HLD and
1209 
      0.000ns delay constraint less
1210 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1211 
 
1212 
 Physical Path Details:
1213 
 
1214 
      Data path textctrl/SLICE_27 to textctrl/SLICE_27:
1215 
 
1216 
   Name    Fanout   Delay (ns)          Site               Resource
1217 
REG_DEL     ---     0.131    R23C32C.CLK to     R23C32C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
1218 
ROUTE         1     0.127     R23C32C.Q0 to     R23C32C.A0 textctrl/blink_cnt[3]
1219 
CTOF_DEL    ---     0.099     R23C32C.A0 to     R23C32C.F0 textctrl/SLICE_27
1220 
ROUTE         1     0.000     R23C32C.F0 to    R23C32C.DI0 textctrl/blink_cnt_s[3] (to cpu_clkgen)
1221 
                  --------
1222 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1223 
 
1224 
 Clock Skew Details:
1225 
 
1226 
      Source Clock Path clk40_i to textctrl/SLICE_27:
1227 
 
1228 
   Name    Fanout   Delay (ns)          Site               Resource
1229 
ROUTE       290     0.828       27.PADDI to    R23C32C.CLK cpu_clkgen
1230 
                  --------
1231 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1232 
 
1233 
      Destination Clock Path clk40_i to textctrl/SLICE_27:
1234 
 
1235 
   Name    Fanout   Delay (ns)          Site               Resource
1236 
ROUTE       290     0.828       27.PADDI to    R23C32C.CLK cpu_clkgen
1237 
                  --------
1238 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1239 
 
1240 
 
1241 
Passed: The following path meets requirements by 0.370ns
1242 
 
1243 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1244 
 
1245 
   Source:         FF         Q              textctrl/blink_cnt[2]  (from cpu_clkgen +)
1246 
   Destination:    FF         Data in        textctrl/blink_cnt[2]  (to cpu_clkgen +)
1247 
 
1248 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1249 
 
1250 
 Constraint Details:
1251 
 
1252 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1253 
     -0.013ns DIN_HLD and
1254 
      0.000ns delay constraint less
1255 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1256 
 
1257 
 Physical Path Details:
1258 
 
1259 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1260 
 
1261 
   Name    Fanout   Delay (ns)          Site               Resource
1262 
REG_DEL     ---     0.131    R23C32B.CLK to     R23C32B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
1263 
ROUTE         1     0.127     R23C32B.Q1 to     R23C32B.A1 textctrl/blink_cnt[2]
1264 
CTOF_DEL    ---     0.099     R23C32B.A1 to     R23C32B.F1 textctrl/SLICE_28
1265 
ROUTE         1     0.000     R23C32B.F1 to    R23C32B.DI1 textctrl/blink_cnt_s[2] (to cpu_clkgen)
1266 
                  --------
1267 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1268 
 
1269 
 Clock Skew Details:
1270 
 
1271 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1272 
 
1273 
   Name    Fanout   Delay (ns)          Site               Resource
1274 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1275 
                  --------
1276 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1277 
 
1278 
      Destination Clock Path clk40_i to textctrl/SLICE_28:
1279 
 
1280 
   Name    Fanout   Delay (ns)          Site               Resource
1281 
ROUTE       290     0.828       27.PADDI to    R23C32B.CLK cpu_clkgen
1282 
                  --------
1283 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1284 
 
1285 
 
1286 
Passed: The following path meets requirements by 0.370ns
1287 
 
1288 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1289 
 
1290 
   Source:         FF         Q              cpu0/k_cpu_addr[3]  (from cpu_clkgen +)
1291 
   Destination:    DP8KC      Port           textctrl/chars/textmem4k_0_2_1(ASIC)  (to cpu_clkgen +)
1292 
 
1293 
   Delay:               0.494ns  (26.5% logic, 73.5% route), 1 logic levels.
1294 
 
1295 
 Constraint Details:
1296 
 
1297 
      0.494ns physical path delay cpu0/SLICE_197 to textctrl/chars/textmem4k_0_2_1 meets
1298 
      0.071ns ADDR_HLD and
1299 
      0.000ns delay constraint less
1300 
     -0.053ns skew requirement (totaling 0.124ns) by 0.370ns
1301 
 
1302 
 Physical Path Details:
1303 
 
1304 
      Data path cpu0/SLICE_197 to textctrl/chars/textmem4k_0_2_1:
1305 
 
1306 
   Name    Fanout   Delay (ns)          Site               Resource
1307 
REG_DEL     ---     0.131    R12C25A.CLK to     R12C25A.Q1 cpu0/SLICE_197 (from cpu_clkgen)
1308 
ROUTE         8     0.363     R12C25A.Q1 to *R_R13C24.ADB4 addr_o_c[3] (to cpu_clkgen)
1309 
                  --------
1310 
                    0.494   (26.5% logic, 73.5% route), 1 logic levels.
1311 
 
1312 
 Clock Skew Details:
1313 
 
1314 
      Source Clock Path clk40_i to cpu0/SLICE_197:
1315 
 
1316 
   Name    Fanout   Delay (ns)          Site               Resource
1317 
ROUTE       290     0.846       27.PADDI to    R12C25A.CLK cpu_clkgen
1318 
                  --------
1319 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1320 
 
1321 
      Destination Clock Path clk40_i to textctrl/chars/textmem4k_0_2_1:
1322 
 
1323 
   Name    Fanout   Delay (ns)          Site               Resource
1324 
ROUTE       290     0.899       27.PADDI to *R_R13C24.CLKB cpu_clkgen
1325 
                  --------
1326 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1327 
 
1328 
Report Summary
1329 
--------------
1330 
----------------------------------------------------------------------------
1331 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
1332 
----------------------------------------------------------------------------
1333 
                                        |             |             |
1334 
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
1335 
MHz ;                                   |            -|            -|   1
1336 
                                        |             |             |
1337 
----------------------------------------------------------------------------
1338 
 
1339 
 
1340 
All preferences were met.
1341 
 
1342 
 
1343 
Clock Domains Analysis
1344 
------------------------
1345 
 
1346 
Found 1 clocks:
1347 
 
1348 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 290
1349 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
1350 
 
1351 
 
1352 
Timing summary (Hold):
1353 
---------------
1354 
 
1355 
Timing errors: 0  Score: 0
1356 
Cumulative negative slack: 0
1357 
 
1358 
Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
1359 
 
1360 
 
1361 
 
1362 
Timing summary (Setup and Hold):
1363 
---------------
1364 
 
1365 
Timing errors: 0 (setup), 0 (hold)
1366 
Score: 0 (setup), 0 (hold)
1367 
Cumulative negative slack: 0 (0+0)
1368 
--------------------------------------------------------------------------------
1369 
 
1370 
--------------------------------------------------------------------------------
1371 
 

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