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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_scck.rpt] - Blame information for rev 12

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# Synospys Constraint Checker(syntax only), version maplat, Build 800R, built Nov 18 2013
# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 
# Written on Sun Jul 06 07:46:29 2014
 
 
##### DESIGN INFO #######################################################
 
Top View:                "CC3_top"
Constraint File(s):      (none)
 
#Run constraint checker to find more issues with constraints.
#########################################################################
 
 
 
No issues found in constraint syntax.
 
 
 
Clock Summary
**************
 
Start                             Requested     Requested     Clock                              Clock
Clock                             Frequency     Period        Type                               Group
--------------------------------------------------------------------------------------------------------------------
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
CC3_top|div_derived_clock         1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
====================================================================================================================

Line No.	Rev	Author	Line
1	12	ale500	`# Synospys Constraint Checker(syntax only), version maplat, Build 800R, built Nov 18 2013`
2			`# Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.`
3
4			`# Written on Sun Jul 06 07:46:29 2014`
5
6
7			`##### DESIGN INFO #######################################################`
8
9			`Top View: "CC3_top"`
10			`Constraint File(s): (none)`
11
12			`#Run constraint checker to find more issues with constraints.`
13			`#########################################################################`
14
15
16
17			`No issues found in constraint syntax.`
18
19
20
21			`Clock Summary`
22			`**************`
23
24			`Start Requested Requested Clock Clock`
25			`Clock Frequency Period Type Group`
26			`--------------------------------------------------------------------------------------------------------------------`
27			`CC3_top\|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0`
28			`CC3_top\|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top\|clk40_i) Inferred_clkgroup_0`
29			`CC3_top\|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top\|clk40_i) Inferred_clkgroup_0`
30			`====================================================================================================================`

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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_scck.rpt] - Blame information for rev 12