OpenCores
URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_tw1.html] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 ale500 
<HTML>
2 
<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
3 
<STYLE TYPE="text/css">
4 
<!--
5 9 ale500 
 body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
6 
-->
7 
</STYLE>
8 
</HEAD>
9 
<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
10 
 
11 
Loading design for application trce from file P6809_P6809_map.ncd.
12 
Design name: CC3_top
13 
NCD version: 3.2
14 
Vendor:      LATTICE
15 
Device:      LCMXO2-7000HE
16 
Package:     TQFP144
17 
Performance: 4
18 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
19 
Package Status:                     Final          Version 1.36
20 
Performance Hardware Data Status:   Final)         Version 23.4
21 
Setup and Hold Report
22 
 
23 
--------------------------------------------------------------------------------
24 
<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
25 
Thu Feb  6 15:35:22 2014
26 
 
27 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
28 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
29 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
30 
Copyright (c) 2001 Agere Systems   All rights reserved.
31 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
32 
 
33 
<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
34 
------------------
35 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
36 
Design file:     P6809_P6809_map.ncd
37 
Preference file: P6809_P6809.prf
38 
Device,speed:    LCMXO2-7000HE,4
39 
Report level:    verbose report, limited to 1 item per preference
40 
--------------------------------------------------------------------------------
41 
 
42 
<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
43 
 
44 
<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (198 errors)</FONT></A></LI>
45 
</FONT>            4096 items scored, 198 timing errors detected.
46 
Warning:  39.118MHz is the maximum frequency for this preference.
47 
 
48 
BLOCK ASYNCPATHS
49 
BLOCK RESETPATHS
50 
--------------------------------------------------------------------------------
51 
 
52 
 
53 
 
54 
================================================================================
55 
<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
56 
            4096 items scored, 198 timing errors detected.
57 
--------------------------------------------------------------------------------
58 
 
59 
 
60 
Error: The following path exceeds requirements by 0.564ns
61 
 
62 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
63 
 
64 
   Source:         FF         Q              cpu0/alu/rb_in[0]  (from cpu_clkgen +)
65 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
66 
 
67 
 
68 
 
69 
 Constraint Details:
70 
 
71 
 
72 
     25.000ns delay constraint less
73 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.564ns
74 
 
75 
 Physical Path Details:
76 
 
77 
      Data path cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55:
78 
 
79 
   Name    Fanout   Delay (ns)          Site               Resource
80 
REG_DEL     ---     0.452 *SLICE_215.CLK to */SLICE_215.Q0 cpu0/alu/SLICE_215 (from cpu_clkgen)
81 
ROUTE        24   e 1.234 */SLICE_215.Q0 to */SLICE_199.A1 cpu0/alu/rb_in[0]
82 
CTOF_DEL    ---     0.495 */SLICE_199.A1 to */SLICE_199.F1 cpu0/alu/alu16/SLICE_199
83 
ROUTE         1   e 1.234 */SLICE_199.F1 to *6/SLICE_99.A1 cpu0/alu/alu16/a16/rb_in_i[0]
84 
C1TOFCO_DE  ---     0.889 *6/SLICE_99.A1 to */SLICE_99.FCO cpu0/alu/alu16/a16/SLICE_99
85 
ROUTE         1   e 0.001 */SLICE_99.FCO to */SLICE_98.FCI cpu0/alu/alu16/a16/un8_q_out_cry_0
86 
FCITOF0_DE  ---     0.585 */SLICE_98.FCI to *6/SLICE_98.F0 cpu0/alu/alu16/a16/SLICE_98
87 
ROUTE         1   e 1.234 *6/SLICE_98.F0 to *SLICE_1214.A0 cpu0/alu/alu16/a16/un8_q_out[1]
88 12 ale500 
CTOF_DEL    ---     0.495 *SLICE_1214.A0 to *SLICE_1214.F0 cpu0/alu/SLICE_1214
89 
 
90 
C0TOFCO_DE  ---     1.023 */SLICE_116.C0 to *SLICE_116.FCO cpu0/alu/alu16/a16/SLICE_116
91 
ROUTE         1   e 0.001 *SLICE_116.FCO to *SLICE_115.FCI cpu0/alu/alu16/a16/q_out_2_cry_2
92 
FCITOFCO_D  ---     0.162 *SLICE_115.FCI to *SLICE_115.FCO cpu0/alu/alu16/a16/SLICE_115
93 
ROUTE         1   e 0.001 *SLICE_115.FCO to *SLICE_114.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
94 
 
95 
ROUTE         1   e 0.001 *SLICE_114.FCO to *SLICE_113.FCI cpu0/alu/alu16/a16/q_out_2_cry_6
96 
FCITOFCO_D  ---     0.162 *SLICE_113.FCI to *SLICE_113.FCO cpu0/alu/alu16/a16/SLICE_113
97 
ROUTE         1   e 0.001 *SLICE_113.FCO to *SLICE_112.FCI cpu0/alu/alu16/a16/q_out_2_cry_8
98 
FCITOFCO_D  ---     0.162 *SLICE_112.FCI to *SLICE_112.FCO cpu0/alu/alu16/a16/SLICE_112
99 
ROUTE         1   e 0.001 *SLICE_112.FCO to *SLICE_111.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
100 
FCITOF1_DE  ---     0.643 *SLICE_111.FCI to */SLICE_111.F1 cpu0/alu/alu16/a16/SLICE_111
101 
ROUTE         1   e 1.234 */SLICE_111.F1 to *SLICE_1048.B0 cpu0/alu/alu16/a16/N_2375
102 
CTOF_DEL    ---     0.495 *SLICE_1048.B0 to *SLICE_1048.F0 cpu0/alu/alu16/SLICE_1048
103 
ROUTE         1   e 0.480 *SLICE_1048.F0 to *SLICE_1048.A1 cpu0/alu/alu16/arith_q[12]
104 
CTOF_DEL    ---     0.495 *SLICE_1048.A1 to *SLICE_1048.F1 cpu0/alu/alu16/SLICE_1048
105 
ROUTE         1   e 1.234 *SLICE_1048.F1 to *SLICE_1066.A1 cpu0/alu/alu16/N_2342
106 
 
107 
ROUTE         2   e 1.234 *SLICE_1066.F1 to *SLICE_1082.B0 cpu0/alu/q16_out[12]
108 
CTOF_DEL    ---     0.495 *SLICE_1082.B0 to *SLICE_1082.F0 cpu0/alu/SLICE_1082
109 
ROUTE         2   e 1.234 *SLICE_1082.F0 to */SLICE_363.A0 cpu0/datamux_o_dest[12]
110 
 
111 
ROUTE         6   e 1.234 */SLICE_363.F0 to *SLICE_1193.B0 cpu0/regs/left_1[12]
112 
CTOF_DEL    ---     0.495 *SLICE_1193.B0 to *SLICE_1193.F0 cpu0/regs/SLICE_1193
113 
ROUTE         1   e 1.234 *SLICE_1193.F0 to */SLICE_951.A1 cpu0/regs/N_291
114 
CTOF_DEL    ---     0.495 */SLICE_951.A1 to */SLICE_951.F1 cpu0/regs/SLICE_951
115 
ROUTE         1   e 0.480 */SLICE_951.F1 to */SLICE_951.B0 cpu0/regs/SU_16[12]
116 
 
117 
ROUTE         1   e 1.234 */SLICE_951.F0 to *s/SLICE_56.C0 cpu0/regs/SU_219_i1_mux
118 
C0TOFCO_DE  ---     1.023 *s/SLICE_56.C0 to */SLICE_56.FCO cpu0/regs/SLICE_56
119 
ROUTE         1   e 0.001 */SLICE_56.FCO to */SLICE_55.FCI cpu0/regs/SU_cry[13]
120 
FCITOF1_DE  ---     0.643 */SLICE_55.FCI to *s/SLICE_55.F1 cpu0/regs/SLICE_55
121 
ROUTE         1   e 0.001 *s/SLICE_55.F1 to */SLICE_55.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
122 
                  --------
123 
                   25.398   (42.7% logic, 57.3% route), 21 logic levels.
124 
 
125 
 
126 
 
127 
 
128 
--------------
129 
----------------------------------------------------------------------------
130 
Preference                              |   Constraint|       Actual|Levels
131 
 
132 
                                        |             |             |
133 
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
134 
MHz ;                                   |   40.000 MHz|   39.118 MHz|  21 *
135 
 
136 
 
137 
 
138 
 
139 
1 preference(marked by "*" above) not met.
140 
 
141 
----------------------------------------------------------------------------
142 
 
143 
 
144 
cpu0/alu/alu16/N_2342                   |       1|     178|     89.90%
145 
 
146 
cpu0/alu/q16_out[12]                    |       2|     178|     89.90%
147 
 
148 
cpu0/alu/alu16/a16/q_out_2_cry_10       |       1|     178|     89.90%
149 
                                        |        |        |
150 
 
151 
                                        |        |        |
152 
 
153 
                                        |        |        |
154 
 
155 
                                        |        |        |
156 
cpu0/regs/left_1[12]                    |       6|     178|     89.90%
157 
                                        |        |        |
158 
 
159 
                                        |        |        |
160 
 
161 
                                        |        |        |
162 
 
163 
                                        |        |        |
164 
cpu0/alu/alu16/a16/un8_q_out_cry_6      |       1|     104|     52.53%
165 
                                        |        |        |
166 
cpu0/regs/SS_cry[13]                    |       1|      99|     50.00%
167 
                                        |        |        |
168 
cpu0/regs/SU_cry[13]                    |       1|      99|     50.00%
169 
                                        |        |        |
170 
cpu0/regs/N_255                         |       1|      89|     44.95%
171 
                                        |        |        |
172 
cpu0/regs/N_291                         |       1|      89|     44.95%
173 
                                        |        |        |
174 
cpu0/regs/SS_235_i1_mux                 |       1|      89|     44.95%
175 
                                        |        |        |
176 
cpu0/regs/SS_16[12]                     |       1|      89|     44.95%
177 
                                        |        |        |
178 
cpu0/regs/SU_219_i1_mux                 |       1|      89|     44.95%
179 
                                        |        |        |
180 
cpu0/regs/SU_16[12]                     |       1|      89|     44.95%
181 
                                        |        |        |
182 
cpu0/alu/alu16/a16/q_out_2_cry_6        |       1|      78|     39.39%
183 
                                        |        |        |
184 
cpu0/alu/alu16/a16/rb_in_i[0]           |       1|      58|     29.29%
185 
                                        |        |        |
186 
cpu0/alu/alu16/a16/un8_q_out_cry_0      |       1|      58|     29.29%
187 
                                        |        |        |
188 
cpu0/alu/rb_in[0]                       |      24|      58|     29.29%
189 
                                        |        |        |
190 
cpu0/regs/SS_s[15]                      |       1|      55|     27.78%
191 
                                        |        |        |
192 
cpu0/regs/SU_s[15]                      |       1|      55|     27.78%
193 
                                        |        |        |
194 
cpu0/alu/alu16/a16/un8_q_out_cry_8      |       1|      54|     27.27%
195 
                                        |        |        |
196 
cpu0/alu/alu16/a16/q_out_2_cry_4        |       1|      46|     23.23%
197 
                                        |        |        |
198 
cpu0/regs/SS_s[14]                      |       1|      44|     22.22%
199 
                                        |        |        |
200 
cpu0/regs/SU_s[14]                      |       1|      44|     22.22%
201 
                                        |        |        |
202 
cpu0/alu/alu16/a16/rb_in_i[1]           |       1|      34|     17.17%
203 
                                        |        |        |
204 
cpu0/alu/rb_in[1]                       |      24|      34|     17.17%
205 
                                        |        |        |
206 
cpu0/alu/alu16/a16/rb_in_i[2]           |       1|      32|     16.16%
207 
                                        |        |        |
208 
 
209 
                                        |        |        |
210 
 
211 
                                        |        |        |
212 
cpu0/alu/alu16/a16/un8_q_out[9]         |       1|      30|     15.15%
213 
                                        |        |        |
214 
cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO  |       1|      28|     14.14%
215 
                                        |        |        |
216 
cpu0/alu/alu16/a16/un8_q_out[7]         |       1|      28|     14.14%
217 
                                        |        |        |
218 
cpu0/alu/alu16/a16/rb_in_i[4]           |       1|      24|     12.12%
219 
                                        |        |        |
220 
cpu0/alu/alu16/a16/rb_in_i[3]           |       1|      24|     12.12%
221 
 
222 
 
223 
                                        |        |        |
224 
 
225 
                                        |        |        |
226 
cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO_0|       1|      24|     12.12%
227 
                                        |        |        |
228 
cpu0/alu/alu16/a16/un8_q_out[8]         |       1|      24|     12.12%
229 
                                        |        |        |
230 
cpu0/alu/rb_in[4]                       |      21|      24|     12.12%
231 
                                        |        |        |
232 
cpu0/alu/rb_in[3]                       |      22|      24|     12.12%
233 
                                        |        |        |
234 
cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO  |       1|      22|     11.11%
235 
                                        |        |        |
236 
cpu0/alu/alu16/a16/un8_q_out[5]         |       1|      22|     11.11%
237 
                                        |        |        |
238 
cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO_0|       1|      20|     10.10%
239 
                                        |        |        |
240 
cpu0/alu/alu16/a16/un8_q_out[6]         |       1|      20|     10.10%
241 
                                        |        |        |
242 
cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO  |       1|      20|     10.10%
243 
                                        |        |        |
244 
cpu0/alu/alu16/a16/un8_q_out[3]         |       1|      20|     10.10%
245 
                                        |        |        |
246 
----------------------------------------------------------------------------
247 
 
248 
 
249 
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
250 
------------------------
251 
 
252 
Found 1 clocks:
253 
 
254 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
255 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
256 
 
257 
 
258 
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
259 
---------------
260 
 
261 
Timing errors: 198  Score: 60114
262 
Cumulative negative slack: 60114
263 
 
264 
Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)
265 
 
266 
--------------------------------------------------------------------------------
267 
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
268 
Thu Feb  6 15:35:22 2014
269 
 
270 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
271 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
272 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
273 
Copyright (c) 2001 Agere Systems   All rights reserved.
274 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
275 
 
276 
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
277 
------------------
278 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
279 
Design file:     P6809_P6809_map.ncd
280 
Preference file: P6809_P6809.prf
281 
Device,speed:    LCMXO2-7000HE,M
282 
Report level:    verbose report, limited to 1 item per preference
283 
--------------------------------------------------------------------------------
284 
 
285 
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
286 
 
287 
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
288 
 
289 
BLOCK ASYNCPATHS
290 
BLOCK RESETPATHS
291 
--------------------------------------------------------------------------------
292 
 
293 
 
294 
 
295 
================================================================================
296 
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
297 
            4096 items scored, 0 timing errors detected.
298 
--------------------------------------------------------------------------------
299 
 
300 
 
301 
Passed: The following path meets requirements by 0.386ns
302 
 
303 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
304 
 
305 
   Source:         FF         Q              reset_cnt[0]  (from cpu_clkgen +)
306 
   Destination:    FF         Data in        reset_cnt[0]  (to cpu_clkgen +)
307 
 
308 
   Delay:               0.330ns  (39.7% logic, 60.3% route), 1 logic levels.
309 
 
310 
 Constraint Details:
311 
 
312 
      0.330ns physical path delay SLICE_444 to SLICE_444 meets
313 
     -0.056ns LSR_HLD and
314 
      0.000ns delay constraint requirement (totaling -0.056ns) by 0.386ns
315 
 
316 
 Physical Path Details:
317 
 
318 
      Data path SLICE_444 to SLICE_444:
319 
 
320 
   Name    Fanout   Delay (ns)          Site               Resource
321 
REG_DEL     ---     0.131  SLICE_444.CLK to   SLICE_444.Q0 SLICE_444 (from cpu_clkgen)
322 
ROUTE         5   e 0.199   SLICE_444.Q0 to  SLICE_444.LSR reset_cnt[0] (to cpu_clkgen)
323 
                  --------
324 
                    0.330   (39.7% logic, 60.3% route), 1 logic levels.
325 
 
326 
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
327 
--------------
328 
----------------------------------------------------------------------------
329 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
330 
----------------------------------------------------------------------------
331 
 
332 
 
333 
MHz ;                                   |            -|            -|   1
334 
                                        |             |             |
335 
 
336 
 
337 
 
338 
All preferences were met.
339 
 
340 
 
341 
 
342 
------------------------
343 
 
344 
 
345 
 
346 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
347 
 
348 
 
349 
 
350 
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
351 
---------------
352 
 
353 
 
354 
Cumulative negative slack: 0
355 
 
356 
Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)
357 
 
358 
 
359 
 
360 
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
361 
---------------
362 
 
363 
Timing errors: 198 (setup), 0 (hold)
364 
Score: 60114 (setup), 0 (hold)
365 
Cumulative negative slack: 60114 (60114+0)
366 
--------------------------------------------------------------------------------
367 
 
368 
 
369 
 
370 
 
371 
 
372 
 
373 
<BR>
374 
<BR>
375 
<BR>
376 
 
377 
 
378 
 
379 
<BR>
380 
<BR>
381 
<BR>
382 
<BR>
383 
 
384 
 
385 
<BR>
386 
 
387 
<BR>
388 
 
389 
<BR>
390 
<BR>
391 
 
392 
<BR>
393 
 
394 
<BR>
395 
 
396 
<BR>
397 
<BR>
398 
<BR>
399 
 
400 
<BR>
401 
 
402 
<BR>
403 
 
404 
<BR>
405 
<BR>
406 
<BR>
407 
<BR>
408 
<BR>
409 
 
410 
<BR>
411 
<BR>
412 
<BR>
413 
<BR>
414 
<BR>
415 
<BR>
416 
<BR>
417 
<BR>
418 
<BR>
419 
<BR>
420 
 
421 
 
422 
<BR>
423 
 
424 
 
425 
</HTML>
426 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.