URL
https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
8 |
ale500 |
SCUBA, Version Diamond_2.2_Production (99)
|
2 |
|
|
Wed Jan 1 20:10:25 2014
|
3 |
|
|
|
4 |
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
5 |
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
6 |
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
7 |
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
8 |
|
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
9 |
|
|
|
10 |
|
|
Issued command : /usr/local/diamond/2.2_x64/ispfpga/bin/lin64/scuba -w -n fontrom -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-7000HE -addr_width 12 -data_width 8 -num_words 4096 -cascade -1 -memfile font256x16l.mem -memformat orca -e
|
11 |
|
|
Circuit name : fontrom
|
12 |
|
|
Module type : EBR_ROM
|
13 |
|
|
Module Version : 5.1
|
14 |
|
|
Ports :
|
15 |
|
|
Inputs : Address[11:0], OutClock, OutClockEn, Reset
|
16 |
|
|
Outputs : Q[7:0]
|
17 |
|
|
I/O buffer : not inserted
|
18 |
|
|
Memory file : font256x16l.mem
|
19 |
|
|
EDIF output : suppressed
|
20 |
|
|
Verilog output : fontrom.v
|
21 |
|
|
Verilog template : fontrom_tmpl.v
|
22 |
|
|
Verilog testbench: tb_fontrom_tmpl.v
|
23 |
|
|
Verilog purpose : for synthesis and simulation
|
24 |
|
|
Bus notation : big endian
|
25 |
|
|
Report output : fontrom.srp
|
26 |
|
|
Element Usage :
|
27 |
|
|
DP8KC : 4
|
28 |
|
|
Estimated Resource Usage:
|
29 |
|
|
EBR : 4
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.