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1 2 kboyette
-------------------------------------------------------------------------------
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--
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-- Title        : 8b/10b Decoder
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-- Design       : 10-bit to 8-bit Decoder
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-- Project      : 8000 - 8b10b_encdec
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-- Author       : Ken Boyette
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-- Company      : Critia Computer, Inc.
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--
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-------------------------------------------------------------------------------
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--
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-- File                 : 8b10b_dec.vhd
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-- Version              : 1.0
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-- Generated    : 09.27.2006
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-- By                   : Itf2Vhdl ver. 1.20
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--
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-------------------------------------------------------------------------------
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--
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-- Description :
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--      This module provides 10-bit to 9-bit encoding.
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--      It accepts 10-bit encoded parallel data input and generates 8-bit decoded 
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--      data output in accordance with the 8b/10b standard method.  This method was
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--      described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block, 
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--      8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek.  The method
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--      WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
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--
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--              The parallel 10-bit Binary input represent 1024 possible values, called
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--              characters - only 268 of which are valid.
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--
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--              The     input is a 10-bit encoded character whose bits are identified as:
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--                      AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
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--
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--              In addition to 256 data output characters, there are 12 special control
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--              or K, characters defined for command and synchronization use.
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--
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--              The eight data output bits are identified as:
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--                      HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
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--
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--              The output, KO, is used to indicate the output value is one of the
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--              control characters.
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--
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--              All inputs and outputs are synchronous with an externally supplied
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--              byte rate clock BYTECLK.
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--              The encoded output is valid one clock after the input.
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--              There is a reset input, RESET, to reset the logic.  The next rising
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--              BYTECLK after RESET is deasserted latches valid input data.
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--
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--              Note: This VHDL structure closely follows the discrete logic defined
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--              in the original article and the subsequent patent.  The Figures 
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--              referenced are those in the patent.
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-------------------------------------------------------------------------------
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--      This program is licensed under the GPL
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity dec_8b10b is
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    port(
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                RESET : in std_logic ;  -- Global asynchronous reset (AH) 
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                RBYTECLK : in std_logic ;       -- Master synchronous receive byte clock
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                AI, BI, CI, DI, EI, II : in std_logic ;
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                FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)               
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                KO : out std_logic ;    -- Control (K) character indicator (AH)
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                HO, GO, FO, EO, DO, CO, BO, AO : out std_logic  -- Decoded out (MS..LS)
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            );
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end dec_8b10b;
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architecture behavioral of dec_8b10b is
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-- Signals to tie things together
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        signal ANEB, CNED, EEI, P13, P22, P31 : std_logic ;     -- Figure 10 Signals
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        signal IKA, IKB, IKC : std_logic ;      -- Figure 11 Signals
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        signal XA, XB, XC, XD, XE : std_logic ; -- Figure 12 Signals    
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        signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic ;
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        signal XF, XG, XH : std_logic ; -- Figure 13 Signals
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        signal OR131, OR132, OR133, OR134, IOR134 : std_logic ;
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begin
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        --
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        -- 6b Input Function (Reference: Figure 10)
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        --
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        -- One 1 and three 0's
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        P13 <=  (ANEB and (not CI and not DI))
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                        or (CNED and (not AI and not BI)) ;
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        -- Three 1's and one 0          
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        P31 <=  (ANEB and CI and DI)
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                        or (CNED and AI and BI) ;
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        -- Two 1's and two 0's
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        P22 <=  (AI and BI and (not CI and not DI))
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                        or (CI and DI and (not AI and not BI))
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                        or (ANEB and CNED) ;
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        -- Intermediate term for "AI is Not Equal to BI"
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        ANEB <=  AI xor BI ;
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        -- Intermediate term for "CI is Not Equal to DI"
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        CNED <=  CI xor DI ;
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        -- Intermediate term for "E is Equal to I"
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        EEI <= EI xnor II ;
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        --
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        -- K Decoder - Figure 11
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        --
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        -- Intermediate terms
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        IKA     <= (CI and DI and EI and II)
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                or (not CI and not DI and not EI and not II) ;
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        IKB <= P13 and (not EI and II and GI and HI and JI) ;
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        IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
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        -- PROCESS: KFN; Determine K output
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        KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
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        begin
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                if RESET = '1' then
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                        KO <= '0';
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                elsif RBYTECLK'event and RBYTECLK = '0' then
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                        KO <= IKA or IKB or IKC;
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                end if;
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        end process KFN;
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        --
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        -- 5b Decoder Figure 12
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        --
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        -- Logic to determine complimenting A,B,C,D,E,I inputs
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        OR121 <= (P22 and (not AI and not CI and EEI))
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                or (P13 and not EI) ;
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        OR122 <= (AI and BI and EI and II)
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                or (not CI and not DI and not EI and not II)
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                or (P31 and II) ;
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        OR123 <= (P31 and II)
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                or (P22 and BI and CI and EEI)
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                or (P13 and DI and EI and II) ;
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        OR124 <= (P22 and AI and CI and EEI)
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                or (P13 and not EI) ;
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        OR125 <= (P13 and not EI)
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                or (not CI and not DI and not EI and not II)
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                or (not AI and not BI and not EI and not II) ;
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        OR126 <= (P22 and not AI and not CI and EEI)
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                or (P13 and not II) ;
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        OR127 <= (P13 and DI and EI and II)
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                or (P22 and not BI and not CI and EEI) ;
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        XA <= OR127
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                or OR121
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                or OR122 ;
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        XB <= OR122
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                or OR123
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                or OR124 ;
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        XC <= OR121
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                or OR123
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                or OR125 ;
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        XD <= OR122
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                or OR124
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                or OR127 ;
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        XE <= OR125
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                or OR126
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                or OR127 ;
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        -- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
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        DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
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        begin
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                if RESET = '1' then
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                        AO <= '0' ;
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                        BO <= '0' ;
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                        CO <= '0' ;
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                        DO <= '0' ;
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                        EO <= '0' ;
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                elsif RBYTECLK'event and RBYTECLK = '0' then
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                        AO <= XA XOR AI ;       -- Least significant bit 0
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                        BO <= XB XOR BI ;
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                        CO <= XC XOR CI ;
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                        DO <= XD XOR DI ;
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                        EO <= XE XOR EI ;       -- Most significant bit 6
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                end if;
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        end process DEC5B;
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        --
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        -- 3b Decoder - Figure 13
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        --
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        -- Logic for complimenting F,G,H outputs
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        OR131 <= (GI and HI and JI)
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                or (FI and HI and JI)
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                or (IOR134);
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        OR132 <= (FI and GI and JI)
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                or (not FI and not GI and not HI)
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                or (not FI and not GI and HI and JI);
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        OR133 <= (not FI and not HI and not JI)
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                or (IOR134)
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                or (not GI and not HI and not JI) ;
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        OR134 <= (not GI and not HI and not JI)
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                or (FI and HI and JI)
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                or (IOR134) ;
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        IOR134 <= (not (HI and JI))
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                and (not (not HI and not JI))
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                and (not CI and not DI and not EI and not II) ;
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        XF <= OR131
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                or OR132 ;
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        XG <= OR132
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                or OR133 ;
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        XH <= OR132
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                or OR134 ;
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        -- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
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        DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
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        begin
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                if RESET = '1' then
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                        FO <= '0' ;
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                        GO <= '0' ;
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                        HO <= '0' ;
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                elsif RBYTECLK'event and RBYTECLK ='0' then
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                        FO <= XF XOR FI ;       -- Least significant bit 7
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                        GO <= XG XOR GI ;
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                        HO <= XH XOR HI ;       -- Most significant bit 10
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                end if;
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        end process DEC3B ;
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end behavioral;
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