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[/] [System09/] [rev_86/] [rtl/] [System09_Digilent_3S500E/] [System09_Digilent_3S500E.vhd] - Blame information for rev 151

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Line No. Rev Author Line
1 59 davidgb 
-- $Id: System09_Digilent_3S500E.vhd,v 1.4 2008-08-20 06:00:55 davidgb Exp $
2 19 dilbert57 
--===========================================================================----
3 
--
4 
--  S Y N T H E Z I A B L E    System09 - SOC.
5 
--
6 
--  This core adheres to the GNU public license
7 
--
8 
-- File name      : System09.vhd
9 
--
10 
-- Purpose        : Top level file for 6809 compatible system on a chip
11 
--                  Designed with Xilinx XC3S500E Spartan 3E FPGA.
12 
--                  Implemented With Digilent Xilinx Starter FPGA board,
13 
--
14 
-- Dependencies   : ieee.Std_Logic_1164
15 
--                  ieee.std_logic_unsigned
16 
--                  ieee.std_logic_arith
17 
--                  ieee.numeric_std
18 
--
19 
-- Uses           : mon_rom  (kbug_rom2k.vhd)       Monitor ROM
20 
--                  cpu09    (cpu09.vhd)      CPU core
21 
--                  miniuart (minitUART3.vhd) ACIA / MiniUART
22 
--                           (rxunit3.vhd)
23 
--                           (tx_unit3.vhd)
24 
--
25 
-- Author         : John E. Kent
26 
--                  dilbert57@opencores.org
27 
--
28 
--===========================================================================----
29 
--
30 
-- Revision History:
31 
--===========================================================================--
32 
-- Version 0.1 - 20 March 2003
33 
-- Version 0.2 - 30 March 2003
34 
-- Version 0.3 - 29 April 2003
35 
-- Version 0.4 - 29 June 2003
36 
--
37 
-- Version 0.5 - 19 July 2003
38 
-- prints out "Hello World"
39 
--
40 
-- Version 0.6 - 5 September 2003
41 
-- Runs SBUG
42 
--
43 
-- Version 1.0- 6 Sep 2003 - John Kent
44 
-- Inverted CLK_50MHZ
45 
-- Initial release to Open Cores
46 
--
47 
-- Version 1.1 - 17 Jan 2004 - John Kent
48 
-- Updated miniUart.
49 
--
50 
-- Version 1.2 - 25 Jan 2004 - John Kent
51 
-- removed signals "test_alu" and "test_cc"
52 
-- Trap hardware re-instated.
53 
--
54 
-- Version 1.3 - 11 Feb 2004 - John Kent
55 
-- Designed forked off to produce System09_VDU
56 
-- Added VDU component
57 
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
58 
-- UART Runs at 57.6 Kbps
59 
--
60 
-- Version 2.0 - 2 September 2004 - John Kent
61 
-- ported to Digilent Xilinx Spartan3 starter board
62 
--      removed Compaact Flash and Trap Logic.
63 
-- Replaced SBUG with KBug9s
64 
--
65 
-- Version 3.0 - 22 April 2006 - John Kent
66 
-- Port to Digilent Spartan 3E Starter board
67 
-- Removed keyboard, vdu, timer, and trap logic
68 
-- added PIA with counters attached.
69 
-- Uses 32Kbytes of internal Block RAM
70 20 dilbert57 
--
71 
-- Version 4.0 - 8th April 2007 - John kent
72 
-- Added VDU and PS/2 keyboard
73 
-- Updated miniUART to ACIA6850
74 
-- Reduce monitor ROM to 2KB
75 
-- Re-assigned I/O port assignments so it is possible to run KBUG9
76 
-- $E000 - ACIA
77 
-- $E020 - Keyboard
78 
-- $E030 - VDU
79 
-- $E040 - Compact Flash (not implemented)
80 
-- $E050 - Timer
81 
-- $E060 - Bus trap
82 
-- $E070 - Parallel I/O
83 
--
84 19 dilbert57 
--===========================================================================--
85 
library ieee;
86 
   use ieee.std_logic_1164.all;
87 
   use IEEE.STD_LOGIC_ARITH.ALL;
88 
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
89 
   use ieee.numeric_std.all;
90 
 
91 59 davidgb 
entity my_system09 is
92 19 dilbert57 
  port(
93 
    CLK_50MHZ     : in  Std_Logic;  -- System Clock input
94 
    BTN_SOUTH     : in  Std_Logic;
95 
 
96 20 dilbert57 
         -- PS/2 Keyboard
97 
         PS2_CLK      : inout Std_logic;
98 
         PS2_DATA     : inout Std_Logic;
99 
 
100 
         -- CRTC output signals
101 
         VGA_VSYNC     : out Std_Logic;
102 
    VGA_HSYNC     : out Std_Logic;
103 
    VGA_BLUE      : out std_logic;
104 
    VGA_GREEN     : out std_logic;
105 
    VGA_RED       : out std_logic;
106 
 
107 19 dilbert57 
         -- Uart Interface
108 
         RS232_DCE_RXD : in  std_logic;
109 
    RS232_DCE_TXD : out std_logic;
110 
 
111 
         -- LEDS & Switches
112 
         LED           : out std_logic_vector(7 downto 0)
113 
         );
114 59 davidgb 
end my_system09;
115 19 dilbert57 
 
116 
-------------------------------------------------------------------------------
117 
-- Architecture for System09
118 
-------------------------------------------------------------------------------
119 59 davidgb 
architecture my_computer of my_system09 is
120 19 dilbert57 
  -----------------------------------------------------------------------------
121 20 dilbert57 
  -- constants
122 
  -----------------------------------------------------------------------------
123 
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
124 
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
125 
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
126 
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
127 
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
128 
 
129 
  -----------------------------------------------------------------------------
130 19 dilbert57 
  -- Signals
131 
  -----------------------------------------------------------------------------
132 
  -- BOOT ROM
133 20 dilbert57 
  signal rom_cs         : Std_logic;
134 
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
135 19 dilbert57 
 
136 
  -- UART Interface signals
137 20 dilbert57 
  signal uart_data_out  : Std_Logic_Vector(7 downto 0);
138 
  signal uart_cs        : Std_Logic;
139 
  signal uart_irq       : Std_Logic;
140 
  signal uart_clk       : Std_Logic;
141 
  signal rxbit          : Std_Logic;
142 
  signal txbit          : Std_Logic;
143 
  signal DCD_n          : Std_Logic;
144 
  signal RTS_n          : Std_Logic;
145 
  signal CTS_n          : Std_Logic;
146 19 dilbert57 
 
147 20 dilbert57 
  -- timer
148 
  signal timer_data_out : std_logic_vector(7 downto 0);
149 
  signal timer_cs       : std_logic;
150 
  signal timer_irq      : std_logic;
151 
 
152 
  -- trap
153 
  signal trap_cs        : std_logic;
154 
  signal trap_data_out  : std_logic_vector(7 downto 0);
155 
  signal trap_irq       : std_logic;
156 
 
157 19 dilbert57 
  -- PIA Interface signals
158 20 dilbert57 
  signal pia_data_out   : Std_Logic_Vector(7 downto 0);
159 
  signal pia_cs         : Std_Logic;
160 
  signal pia_irq_a      : Std_Logic;
161 
  signal pia_irq_b      : Std_Logic;
162 19 dilbert57 
 
163 20 dilbert57 
  -- keyboard port
164 
  signal keyboard_data_out : std_logic_vector(7 downto 0);
165 
  signal keyboard_cs       : std_logic;
166 
  signal keyboard_irq      : std_logic;
167 
 
168 
  -- Video Display Unit
169 
  signal pix_clk      : std_logic;
170 
  signal vdu_cs       : std_logic;
171 
  signal vdu_data_out : std_logic_vector(7 downto 0);
172 
 
173 19 dilbert57 
  -- RAM
174 
  signal ram_cs       : std_logic; -- memory chip select
175 
  signal ram_data_out : std_logic_vector(7 downto 0);
176 
 
177 
  -- CPU Interface signals
178 
  signal cpu_reset    : Std_Logic;
179 
  signal cpu_clk      : Std_Logic;
180 
  signal cpu_rw       : std_logic;
181 
  signal cpu_vma      : std_logic;
182 
  signal cpu_halt     : std_logic;
183 
  signal cpu_hold     : std_logic;
184 
  signal cpu_firq     : std_logic;
185 
  signal cpu_irq      : std_logic;
186 
  signal cpu_nmi      : std_logic;
187 
  signal cpu_addr     : std_logic_vector(15 downto 0);
188 
  signal cpu_data_in  : std_logic_vector(7 downto 0);
189 
  signal cpu_data_out : std_logic_vector(7 downto 0);
190 
 
191 20 dilbert57 
  -- CLK_50MHZ clock divide by 2
192 
  signal clock_div    : std_logic_vector(1 downto 0);
193 
  signal SysClk       : std_logic;
194 
  signal Reset_n      : std_logic;
195 19 dilbert57 
  signal CountL       : std_logic_vector(23 downto 0);
196 
 
197 
-----------------------------------------------------------------
198 
--
199 
-- CPU09 CPU core
200 
--
201 
-----------------------------------------------------------------
202 
 
203 
component cpu09
204 
  port (
205 
         clk:        in std_logic;
206 
    rst:      in        std_logic;
207 
    rw:      out        std_logic;              -- Asynchronous memory interface
208 
    vma:             out        std_logic;
209 
    address:  out       std_logic_vector(15 downto 0);
210 
    data_in:  in        std_logic_vector(7 downto 0);
211 
         data_out: out std_logic_vector(7 downto 0);
212 
         halt:     in  std_logic;
213 
         hold:     in  std_logic;
214 
         irq:      in  std_logic;
215 
         nmi:      in  std_logic;
216 
         firq:     in  std_logic
217 
  );
218 
end component;
219 
 
220 
 
221 
----------------------------------------
222 
--
223 
-- Block RAM Monitor ROM
224 
--
225 
----------------------------------------
226 20 dilbert57 
component mon_rom
227 19 dilbert57 
    Port (
228 
       clk   : in  std_logic;
229 
                 rst   : in  std_logic;
230 
                 cs    : in  std_logic;
231 
                 rw    : in  std_logic;
232 20 dilbert57 
       addr  : in  std_logic_vector (10 downto 0);
233 19 dilbert57 
       rdata : out std_logic_vector (7 downto 0);
234 
       wdata : in  std_logic_vector (7 downto 0)
235 
    );
236 
end component;
237 
 
238 
----------------------------------------
239 
--
240 
-- Block RAM Monitor
241 
--
242 
----------------------------------------
243 
component ram_32k
244 
    Port (
245 
       clk   : in  std_logic;
246 
                 rst   : in  std_logic;
247 
                 cs    : in  std_logic;
248 
                 rw    : in  std_logic;
249 
       addr  : in  std_logic_vector (14 downto 0);
250 
       rdata : out std_logic_vector (7 downto 0);
251 
       wdata : in  std_logic_vector (7 downto 0)
252 
    );
253 
end component;
254 
 
255 
-----------------------------------------------------------------
256 
--
257 
-- 6822 compatible PIA with counters
258 
--
259 
-----------------------------------------------------------------
260 
 
261 
component pia_timer
262 
        port (
263 
         clk       : in    std_logic;
264 
    rst       : in    std_logic;
265 
    cs        : in    std_logic;
266 
    rw        : in    std_logic;
267 
    addr      : in    std_logic_vector(1 downto 0);
268 
    data_in   : in    std_logic_vector(7 downto 0);
269 
         data_out  : out   std_logic_vector(7 downto 0);
270 
         irqa      : out   std_logic;
271 
         irqb      : out   std_logic
272 
         );
273 
end component;
274 
 
275 20 dilbert57 
 
276 19 dilbert57 
-----------------------------------------------------------------
277 
--
278 20 dilbert57 
-- 6850 ACIA/UART
279 19 dilbert57 
--
280 
-----------------------------------------------------------------
281 
 
282 20 dilbert57 
component ACIA_6850
283 19 dilbert57 
  port (
284 
     clk      : in  Std_Logic;  -- System Clock
285 
     rst      : in  Std_Logic;  -- Reset input (active high)
286 
     cs       : in  Std_Logic;  -- miniUART Chip Select
287 
     rw       : in  Std_Logic;  -- Read / Not Write
288 
     irq      : out Std_Logic;  -- Interrupt
289 
     Addr     : in  Std_Logic;  -- Register Select
290 
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In
291 
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
292 
     RxC      : in  Std_Logic;  -- Receive Baud Clock
293 
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
294 
     RxD      : in  Std_Logic;  -- Receive Data
295 
     TxD      : out Std_Logic;  -- Transmit Data
296 
          DCD_n    : in  Std_Logic;  -- Data Carrier Detect
297 
     CTS_n    : in  Std_Logic;  -- Clear To Send
298 
     RTS_n    : out Std_Logic );  -- Request To send
299 
end component;
300 
 
301 20 dilbert57 
-----------------------------------------------------------------
302 
--
303 
-- ACIA Clock divider
304 
--
305 
-----------------------------------------------------------------
306 19 dilbert57 
 
307 20 dilbert57 
component ACIA_Clock
308 
  generic (
309 
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
310 
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
311 
  );
312 
  port (
313 
     clk      : in  Std_Logic;  -- System Clock Input
314 
          ACIA_clk : out Std_logic   -- ACIA Clock output
315 
  );
316 
end component;
317 
 
318 
----------------------------------------
319 
--
320 
-- Timer module
321 
--
322 
----------------------------------------
323 
 
324 
component timer
325 
  port (
326 
     clk       : in std_logic;
327 
     rst       : in std_logic;
328 
     cs        : in std_logic;
329 
     rw        : in std_logic;
330 
     addr      : in std_logic;
331 
     data_in   : in std_logic_vector(7 downto 0);
332 
          data_out  : out std_logic_vector(7 downto 0);
333 59 davidgb 
          irq       : out std_logic
334 
          -- ;
335 
     -- timer_in  : in std_logic;
336 
          -- timer_out : out std_logic
337 20 dilbert57 
          );
338 
end component;
339 
 
340 
------------------------------------------------------------
341 
--
342 
-- Bus Trap logic
343 
--
344 
------------------------------------------------------------
345 
 
346 
component trap
347 
        port (
348 
         clk        : in  std_logic;
349 
    rst        : in  std_logic;
350 
    cs         : in  std_logic;
351 
    rw         : in  std_logic;
352 
    vma        : in  std_logic;
353 
    addr       : in  std_logic_vector(15 downto 0);
354 
    data_in    : in  std_logic_vector(7 downto 0);
355 
         data_out   : out std_logic_vector(7 downto 0);
356 
         irq        : out std_logic
357 
  );
358 
end component;
359 
 
360 
----------------------------------------
361 
--
362 
-- PS/2 Keyboard
363 
--
364 
----------------------------------------
365 
 
366 
component keyboard
367 
  generic(
368 
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
369 
  );
370 
  port(
371 
  clk             : in    std_logic;
372 
  rst             : in    std_logic;
373 
  cs              : in    std_logic;
374 
  rw              : in    std_logic;
375 
  addr            : in    std_logic;
376 
  data_in         : in    std_logic_vector(7 downto 0);
377 
  data_out        : out   std_logic_vector(7 downto 0);
378 
  irq             : out   std_logic;
379 
  kbd_clk         : inout std_logic;
380 
  kbd_data        : inout std_logic
381 
  );
382 
end component;
383 
 
384 
----------------------------------------
385 
--
386 
-- Video Display Unit.
387 
--
388 
----------------------------------------
389 
component vdu8
390 
      generic(
391 
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
392 
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
393 
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
394 
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
395 
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
396 
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
397 
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
398 
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
399 
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
400 
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
401 
             VGA_VER_SYNC           : integer := 1;  -- LINES
402 
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
403 
      );
404 
      port(
405 
                -- control register interface
406 
      vdu_clk      : in  std_logic;      -- CPU Clock - 12.5MHz
407 
      vdu_rst      : in  std_logic;
408 
                vdu_cs       : in  std_logic;
409 
                vdu_rw       : in  std_logic;
410 
                vdu_addr     : in  std_logic_vector(2 downto 0);
411 
      vdu_data_in  : in  std_logic_vector(7 downto 0);
412 
      vdu_data_out : out std_logic_vector(7 downto 0);
413 
 
414 
      -- vga port connections
415 
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
416 
      vga_red_o    : out std_logic;
417 
      vga_green_o  : out std_logic;
418 
      vga_blue_o   : out std_logic;
419 
      vga_hsync_o  : out std_logic;
420 
      vga_vsync_o  : out std_logic
421 
   );
422 
end component;
423 
 
424 
 
425 19 dilbert57 
component BUFG
426 
port (
427 
     i: in std_logic;
428 
          o: out std_logic
429 
  );
430 
end component;
431 
 
432 
begin
433 
  -----------------------------------------------------------------------------
434 
  -- Instantiation of internal components
435 
  -----------------------------------------------------------------------------
436 
 
437 
my_cpu : cpu09  port map (
438 
         clk         => cpu_clk,
439 
    rst       => cpu_reset,
440 
    rw       => cpu_rw,
441 
    vma       => cpu_vma,
442 
    address   => cpu_addr(15 downto 0),
443 
    data_in   => cpu_data_in,
444 
         data_out  => cpu_data_out,
445 
         halt      => cpu_halt,
446 
         hold      => cpu_hold,
447 
         irq       => cpu_irq,
448 
         nmi       => cpu_nmi,
449 
         firq      => cpu_firq
450 
  );
451 
 
452 20 dilbert57 
my_rom : mon_rom port map (
453 19 dilbert57 
       clk   => cpu_clk,
454 
                 rst   => cpu_reset,
455 
                 cs    => rom_cs,
456 
                 rw    => '1',
457 20 dilbert57 
       addr  => cpu_addr(10 downto 0),
458 19 dilbert57 
       rdata => rom_data_out,
459 
       wdata => cpu_data_out
460 
    );
461 
 
462 
my_ram : ram_32k port map (
463 
       clk   => cpu_clk,
464 
                 rst   => cpu_reset,
465 
                 cs    => ram_cs,
466 
                 rw    => cpu_rw,
467 
       addr  => cpu_addr(14 downto 0),
468 
       rdata => ram_data_out,
469 
       wdata => cpu_data_out
470 
    );
471 
 
472 
my_pia  : pia_timer port map (
473 
         clk         => cpu_clk,
474 
         rst       => cpu_reset,
475 
    cs        => pia_cs,
476 
         rw        => cpu_rw,
477 
    addr      => cpu_addr(1 downto 0),
478 
         data_in   => cpu_data_out,
479 
         data_out  => pia_data_out,
480 
    irqa      => pia_irq_a,
481 
    irqb      => pia_irq_b
482 
         );
483 
 
484 20 dilbert57 
 
485 
----------------------------------------
486 
--
487 
-- ACIA/UART Serial interface
488 
--
489 
----------------------------------------
490 
my_ACIA  : ACIA_6850 port map (
491 19 dilbert57 
         clk         => cpu_clk,
492 
         rst       => cpu_reset,
493 
    cs        => uart_cs,
494 
         rw        => cpu_rw,
495 
    irq       => uart_irq,
496 
    Addr      => cpu_addr(0),
497 
         Datain    => cpu_data_out,
498 
         DataOut   => uart_data_out,
499 20 dilbert57 
         RxC       => uart_clk,
500 
         TxC       => uart_clk,
501 
         RxD       => rxbit,
502 
         TxD       => txbit,
503 19 dilbert57 
         DCD_n     => dcd_n,
504 
         CTS_n     => cts_n,
505 
         RTS_n     => rts_n
506 
         );
507 
 
508 20 dilbert57 
----------------------------------------
509 
--
510 
-- ACIA Clock
511 
--
512 
----------------------------------------
513 
my_ACIA_Clock : ACIA_Clock
514 
  generic map(
515 
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
516 
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
517 
  )
518 
  port map(
519 
    clk        => SysClk,
520 
    acia_clk   => uart_clk
521 
  );
522 19 dilbert57 
 
523 20 dilbert57 
 
524 
 
525 
----------------------------------------
526 
--
527 
-- PS/2 Keyboard Interface
528 
--
529 
----------------------------------------
530 
my_keyboard : keyboard
531 
   generic map (
532 
        KBD_Clock_Frequency => CPU_Clock_frequency
533 
        )
534 
   port map(
535 
        clk          => cpu_clk,
536 
        rst          => cpu_reset,
537 
        cs           => keyboard_cs,
538 
        rw           => cpu_rw,
539 
        addr         => cpu_addr(0),
540 
        data_in      => cpu_data_out(7 downto 0),
541 
        data_out     => keyboard_data_out(7 downto 0),
542 
        irq          => keyboard_irq,
543 
        kbd_clk      => PS2_CLK,
544 
        kbd_data     => PS2_DATA
545 
        );
546 
 
547 
----------------------------------------
548 
--
549 
-- Video Display Unit instantiation
550 
--
551 
----------------------------------------
552 
my_vdu : vdu8
553 
  generic map(
554 
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
555 
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
556 
           VGA_HOR_CHARS          => 80, -- CHARACTERS
557 
           VGA_VER_CHARS          => 25, -- CHARACTERS
558 
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
559 
           VGA_LINES_PER_CHAR     => 16, -- LINES
560 
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
561 
           VGA_HOR_SYNC           => 96, -- PIXELS
562 
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
563 
           VGA_VER_BACK_PORCH     => 13, -- LINES
564 
           VGA_VER_SYNC           => 1,  -- LINES
565 
           VGA_VER_FRONT_PORCH    => 36  -- LINES
566 
  )
567 
  port map(
568 
 
569 
                -- Control Registers
570 
                vdu_clk       => cpu_clk,                                        -- 25 MHz System Clock in
571 
      vdu_rst       => cpu_reset,
572 
                vdu_cs        => vdu_cs,
573 
                vdu_rw        => cpu_rw,
574 
                vdu_addr      => cpu_addr(2 downto 0),
575 
                vdu_data_in   => cpu_data_out,
576 
                vdu_data_out  => vdu_data_out,
577 
 
578 
      -- vga port connections
579 
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
580 
      vga_red_o     => vga_red,
581 
      vga_green_o   => vga_green,
582 
      vga_blue_o    => vga_blue,
583 
      vga_hsync_o   => vga_hsync,
584 
      vga_vsync_o   => vga_vsync
585 
   );
586 
 
587 
 
588 
----------------------------------------
589 
--
590 
-- Timer Module
591 
--
592 
----------------------------------------
593 
my_timer  : timer port map (
594 
    clk       => cpu_clk,
595 
         rst       => cpu_reset,
596 
    cs        => timer_cs,
597 
         rw        => cpu_rw,
598 
    addr      => cpu_addr(0),
599 
         data_in   => cpu_data_out,
600 
         data_out  => timer_data_out,
601 59 davidgb 
    irq       => timer_irq
602 
         -- ,
603 
         -- timer_in  => CountL(5)
604 20 dilbert57 
--       timer_out => timer_out
605 
    );
606 
 
607 
----------------------------------------
608 
--
609 
-- Bus Trap Interrupt logic
610 
--
611 
----------------------------------------
612 
my_trap : trap port map (
613 
         clk        => cpu_clk,
614 
    rst        => cpu_reset,
615 
    cs         => trap_cs,
616 
    rw         => cpu_rw,
617 
         vma        => cpu_vma,
618 
    addr       => cpu_addr,
619 
    data_in    => cpu_data_out,
620 
         data_out   => trap_data_out,
621 
         irq        => trap_irq
622 
    );
623 
 
624 
--
625 
-- 25 MHz CPU clock
626 
--
627 
cpu_clk_buffer : BUFG port map(
628 
    i => clock_div(0),
629 19 dilbert57 
         o => cpu_clk
630 20 dilbert57 
    );
631 
 
632 
--
633 
-- 25 MHz VGA Pixel clock
634 
--
635 
vga_clk_buffer : BUFG port map(
636 
    i => clock_div(0),
637 
         o => pix_clk
638 19 dilbert57 
    );
639 
 
640 
----------------------------------------------------------------------
641 
--
642 
-- Process to decode memory map
643 
--
644 
----------------------------------------------------------------------
645 
 
646 20 dilbert57 
mem_decode: process( cpu_clk, Reset_n,
647 19 dilbert57 
                     cpu_addr, cpu_rw, cpu_vma,
648 20 dilbert57 
                                              rom_data_out,
649 19 dilbert57 
                                                        ram_data_out,
650 20 dilbert57 
                                                   timer_data_out,
651 
                                                        trap_data_out,
652 
                                                        pia_data_out,
653 19 dilbert57 
                                                   uart_data_out,
654 20 dilbert57 
                                                        keyboard_data_out,
655 
                                                        vdu_data_out )
656 
variable decode_addr : std_logic_vector(3 downto 0);
657 19 dilbert57 
begin
658 20 dilbert57 
--    decode_addr := dat_addr(3 downto 0) & cpu_addr(11);
659 
    decode_addr := cpu_addr(15 downto 12);
660 
 
661 
      case decode_addr is
662 19 dilbert57 
           --
663 20 dilbert57 
                -- SBUG/KBUG/SYS09BUG Monitor ROM $F800 - $FFFF
664 19 dilbert57 
                --
665 20 dilbert57 
                when "1111" => -- $F000 - $FFFF
666 19 dilbert57 
                   cpu_data_in <= rom_data_out;
667 20 dilbert57 
                        rom_cs      <= cpu_vma;              -- read ROM
668 19 dilbert57 
                        ram_cs      <= '0';
669 
                        uart_cs     <= '0';
670 20 dilbert57 
                        timer_cs    <= '0';
671 
                        trap_cs     <= '0';
672 19 dilbert57 
                        pia_cs      <= '0';
673 20 dilbert57 
                        keyboard_cs <= '0';
674 
                        vdu_cs      <= '0';
675 
 
676 19 dilbert57 
      --
677 20 dilbert57 
                -- IO Devices $E000 - $EFFF
678 19 dilbert57 
                --
679 20 dilbert57 
                when "1110" => -- $E000 - $E7FF
680 19 dilbert57 
                        rom_cs    <= '0';
681 
                        ram_cs    <= '0';
682 20 dilbert57 
                   case cpu_addr(7 downto 4) is
683 19 dilbert57 
                        --
684 20 dilbert57 
                        -- UART / ACIA $E000
685 19 dilbert57 
                        --
686 20 dilbert57 
                        when "0000" => -- $E000
687 
                     cpu_data_in <= uart_data_out;
688 
                          uart_cs     <= cpu_vma;
689 
                          timer_cs    <= '0';
690 
                          trap_cs     <= '0';
691 
                          pia_cs      <= '0';
692 
                          keyboard_cs <= '0';
693 
                          vdu_cs      <= '0';
694 
 
695 
                        --
696 
                        -- WD1771 FDC sites at $E010-$E01F
697 
                        --
698 
                        when "0001" => -- $E010
699 
           cpu_data_in <= (others => '0');
700 19 dilbert57 
                          uart_cs     <= '0';
701 20 dilbert57 
                          timer_cs    <= '0';
702 
                          trap_cs     <= '0';
703 
                          pia_cs      <= '0';
704 
                          keyboard_cs <= '0';
705 
                          vdu_cs      <= '0';
706 
 
707 
         --
708 
         -- Keyboard port $E020 - $E02F
709 19 dilbert57 
                        --
710 20 dilbert57 
                        when "0010" => -- $E020
711 
           cpu_data_in <= keyboard_data_out;
712 
                          uart_cs     <= '0';
713 
           timer_cs    <= '0';
714 
                          trap_cs     <= '0';
715 
                          pia_cs      <= '0';
716 
                          keyboard_cs <= cpu_vma;
717 
                          vdu_cs      <= '0';
718 
 
719 
         --
720 
         -- VDU port $E030 - $E03F
721 19 dilbert57 
                        --
722 20 dilbert57 
                        when "0011" => -- $E030
723 
           cpu_data_in <= vdu_data_out;
724 
                          uart_cs     <= '0';
725 
           timer_cs    <= '0';
726 
                          trap_cs     <= '0';
727 
                          pia_cs      <= '0';
728 
                          keyboard_cs <= '0';
729 
                          vdu_cs      <= cpu_vma;
730 19 dilbert57 
 
731 20 dilbert57 
         --
732 
                        -- Compact Flash $E040 - $E04F
733 
                        --
734 
                        when "0100" => -- $E040
735 
           cpu_data_in <= (others => '0');
736 19 dilbert57 
                          uart_cs     <= '0';
737 20 dilbert57 
                          timer_cs    <= '0';
738 
                          trap_cs     <= '0';
739 
                          pia_cs      <= '0';
740 
                          keyboard_cs <= '0';
741 
                          vdu_cs      <= '0';
742 
 
743 
         --
744 
         -- Timer $E050 - $E05F
745 
                        --
746 
                        when "0101" => -- $E050
747 
           cpu_data_in <= timer_data_out;
748 
                          uart_cs     <= '0';
749 
           timer_cs    <= cpu_vma;
750 
                          trap_cs     <= '0';
751 
                          pia_cs      <= '0';
752 
                          keyboard_cs <= '0';
753 
                          vdu_cs      <= '0';
754 
 
755 
         --
756 
         -- Bus Trap Logic $E060 - $E06F
757 
                        --
758 
                        when "0110" => -- $E060
759 
           cpu_data_in <= trap_data_out;
760 
                          uart_cs     <= '0';
761 
           timer_cs    <= '0';
762 
                          trap_cs     <= cpu_vma;
763 
                          pia_cs      <= '0';
764 
                          keyboard_cs <= '0';
765 
                          vdu_cs      <= '0';
766 
 
767 
         --
768 
         -- I/O port $E070 - $E07F
769 
                        --
770 
                        when "0111" => -- $E070
771 
           cpu_data_in <= pia_data_out;
772 
                          uart_cs     <= '0';
773 
           timer_cs    <= '0';
774 
                          trap_cs     <= '0';
775 
                          pia_cs      <= cpu_vma;
776 
                          keyboard_cs <= '0';
777 
                          vdu_cs      <= '0';
778 
 
779 
                        when others => -- $E080 to $E7FF
780 
           cpu_data_in <= (others => '0');
781 
                          uart_cs     <= '0';
782 
                          timer_cs    <= '0';
783 
                          trap_cs     <= '0';
784 
                          pia_cs      <= '0';
785 
                          keyboard_cs <= '0';
786 
                          vdu_cs      <= '0';
787 19 dilbert57 
                   end case;
788 20 dilbert57 
 
789 19 dilbert57 
                --
790 20 dilbert57 
                -- $8000 to $DFFF = null
791 
                --
792 
      when "1101" | "1100" | "1011" | "1010" |
793 
                     "1001" | "1000" =>
794 
                  cpu_data_in <= (others => '0');
795 
                  rom_cs      <= '0';
796 
                  ram_cs      <= '0';
797 
                  uart_cs     <= '0';
798 
                  timer_cs    <= '0';
799 
                  trap_cs     <= '0';
800 
                  pia_cs      <= '0';
801 
                  keyboard_cs <= '0';
802 
                  vdu_cs      <= '0';
803 
                --
804 19 dilbert57 
                -- Everything else is RAM
805 
                --
806 
                when others =>
807 
                  cpu_data_in <= ram_data_out;
808 
                  rom_cs      <= '0';
809 
                  ram_cs      <= cpu_vma;
810 
                  uart_cs     <= '0';
811 20 dilbert57 
                  timer_cs    <= '0';
812 
                  trap_cs     <= '0';
813 
                  pia_cs      <= '0';
814 
                  keyboard_cs <= '0';
815 
                  vdu_cs      <= '0';
816 
                end case;
817 19 dilbert57 
end process;
818 
 
819 
--
820 
-- Interrupts and other bus control signals
821 
--
822 20 dilbert57 
interrupts : process( Reset_n,
823 
                      pia_irq_a, pia_irq_b, uart_irq, trap_irq, timer_irq, keyboard_irq
824 19 dilbert57 
                                                         )
825 
begin
826 20 dilbert57 
         cpu_reset <= not Reset_n; -- CPU reset is active high
827 
    cpu_irq   <= uart_irq or keyboard_irq;
828 
         cpu_nmi   <= pia_irq_a or trap_irq;
829 
         cpu_firq  <= pia_irq_b or timer_irq;
830 19 dilbert57 
         cpu_halt  <= '0';
831 
    cpu_hold  <= '0';
832 
end process;
833 
 
834 
--
835 
--
836 20 dilbert57 
my_led_flasher: process( SysClk, Reset_n, CountL )
837 19 dilbert57 
begin
838 20 dilbert57 
    if Reset_n = '0' then
839 
                   CountL <= "000000000000000000000000";
840 
    elsif(SysClk'event and SysClk = '0') then
841 
                   CountL <= CountL + 1;
842 19 dilbert57 
    end if;
843 20 dilbert57 
         LED(7 downto 0) <= CountL(23 downto 16);
844 19 dilbert57 
end process;
845 
 
846 
--
847 20 dilbert57 
-- Clock divider
848 19 dilbert57 
--
849 20 dilbert57 
my_clock_divider: process( SysClk )
850 19 dilbert57 
begin
851 20 dilbert57 
        if SysClk'event and SysClk='0' then
852 
                clock_div <= clock_div + "01";
853 
        end if;
854 19 dilbert57 
end process;
855 
 
856 
DCD_n <= '0';
857 
CTS_n <= '0';
858 20 dilbert57 
Reset_n <= not BTN_SOUTH; -- CPU reset is active high
859 
SysClk <= CLK_50MHZ;
860 
rxbit <= RS232_DCE_RXD;
861 
RS232_DCE_TXD <= txbit;
862 19 dilbert57 
 
863 
end my_computer; --===================== End of architecture =======================--
864 
 

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