OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [rev_86/] [rtl/] [VHDL/] [mul32.vhd] - Blame information for rev 158

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 65 davidgb
--===========================================================================--
2
--
3
--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
4
--
5
--===========================================================================--
6
--
7
--  This core adheres to the GNU public license  
8
--
9
-- File name      : mul32.vhd
10
--
11
-- entity name    : mul32
12
--
13
-- Purpose        : Implements a 32 bit x 32 bit hardware multiplier
14
--                  with 64 bit reset
15
--                  R/W Registers 0 to 3 are the left input MSB first
16
--                  R/W Registers 4 to 7 are the right input MSB first
17
--                  RO Registers 8 to 15 are the 64 bit result 
18
--                  
19
-- Dependencies   : ieee.Std_Logic_1164
20
--                  ieee.std_logic_unsigned
21
--
22
-- Author         : John E. Kent      
23
--
24
--===========================================================================----
25
--
26
-- Revision History:
27
--
28
-- Date          Revision  Author 
29
-- 7th Sep 2008   0.1       John Kent
30
--
31
--
32
--
33
 
34
library ieee;
35
  use ieee.std_logic_1164.all;
36
  use ieee.std_logic_unsigned.all;
37
library unisim;
38
  use unisim.vcomponents.all;
39
 
40
entity mul32 is
41
        port (
42
         clk       : in  std_logic;
43
    rst       : in  std_logic;
44
    cs        : in  std_logic;
45
    rw        : in  std_logic;
46
    addr      : in  std_logic_vector(3 downto 0);
47
    dati      : in  std_logic_vector(7 downto 0);
48
         dato      : out std_logic_vector(7 downto 0));
49
end entity;
50
 
51
architecture rtl of mul32 is
52
--
53
-- registers
54
--
55
signal mul_reg0 : std_logic_vector(7 downto 0);
56
signal mul_reg1 : std_logic_vector(7 downto 0);
57
signal mul_reg2 : std_logic_vector(7 downto 0);
58
signal mul_reg3 : std_logic_vector(7 downto 0);
59
signal mul_reg4 : std_logic_vector(7 downto 0);
60
signal mul_reg5 : std_logic_vector(7 downto 0);
61
signal mul_reg6 : std_logic_vector(7 downto 0);
62
signal mul_reg7 : std_logic_vector(7 downto 0);
63
signal mul_reg8 : std_logic_vector(7 downto 0);
64
signal mul_reg9 : std_logic_vector(7 downto 0);
65
signal mul_reg10 : std_logic_vector(7 downto 0);
66
signal mul_reg11 : std_logic_vector(7 downto 0);
67
signal mul_reg12 : std_logic_vector(7 downto 0);
68
signal mul_reg13 : std_logic_vector(7 downto 0);
69
signal mul_reg14 : std_logic_vector(7 downto 0);
70
signal mul_reg15 : std_logic_vector(7 downto 0);
71
 
72
begin
73
 
74
---------------------------------
75
--
76
-- Write Multiplier Registers
77
--
78
---------------------------------
79
 
80
mul_write : process( clk )
81
begin
82
  if clk'event and clk = '0' then
83
    if rst = '1' then
84
      mul_reg0  <= "00000000";
85
      mul_reg1  <= "00000000";
86
      mul_reg2  <= "00000000";
87
      mul_reg3  <= "00000000";
88
      mul_reg4  <= "00000000";
89
      mul_reg5  <= "00000000";
90
      mul_reg6  <= "00000000";
91
      mul_reg7  <= "00000000";
92
    else
93
           if cs = '1' and rw = '0' then
94
        case addr is
95
             when "0000" =>
96
                    mul_reg0 <= dati;
97
             when "0001" =>
98
                    mul_reg1 <= dati;
99
             when "0010" =>
100
                    mul_reg2 <= dati;
101
             when "0011" =>
102
                    mul_reg3 <= dati;
103
             when "0100" =>
104
                    mul_reg4 <= dati;
105
             when "0101" =>
106
                    mul_reg5 <= dati;
107
             when "0110" =>
108
                    mul_reg6 <= dati;
109
             when "0111" =>
110
                    mul_reg7 <= dati;
111
        when others =>
112
                    null;
113
                  end case;
114
           end if;
115
         end if;
116
  end if;
117
end process;
118
 
119
---------------------------------
120
--
121
-- Read Multiplier Registers
122
--
123
---------------------------------
124
 
125
mul_read : process(  addr,
126
                     mul_reg0, mul_reg1, mul_reg2, mul_reg3,
127
                     mul_reg4, mul_reg5, mul_reg6, mul_reg7,
128
                     mul_reg8, mul_reg9, mul_reg10, mul_reg11,
129
                     mul_reg12, mul_reg13, mul_reg14, mul_reg15 )
130
begin
131
      case addr is
132
             when "0000" =>
133
                    dato <= mul_reg0;
134
             when "0001" =>
135
                    dato <= mul_reg1;
136
             when "0010" =>
137
                    dato <= mul_reg2;
138
             when "0011" =>
139
                    dato <= mul_reg3;
140
             when "0100" =>
141
                    dato <= mul_reg4;
142
             when "0101" =>
143
                    dato <= mul_reg5;
144
             when "0110" =>
145
                    dato <= mul_reg6;
146
             when "0111" =>
147
                    dato <= mul_reg7;
148
             when "1000" =>
149
                    dato <= mul_reg8;
150
             when "1001" =>
151
                    dato <= mul_reg9;
152
             when "1010" =>
153
                    dato <= mul_reg10;
154
             when "1011" =>
155
                    dato <= mul_reg11;
156
             when "1100" =>
157
                    dato <= mul_reg12;
158
             when "1101" =>
159
                    dato <= mul_reg13;
160
             when "1110" =>
161
                    dato <= mul_reg14;
162
             when "1111" =>
163
                    dato <= mul_reg15;
164
        when others =>
165
                    null;
166
                end case;
167
 
168
end process;
169
 
170
---------------------------------
171
--
172
-- Perform 32 x 32 multiply
173
--
174
---------------------------------
175
 
176
my_mul32 : process(
177
                     mul_reg0, mul_reg1, mul_reg2, mul_reg3,
178
                     mul_reg4, mul_reg5, mul_reg6, mul_reg7
179
                                                         )
180
variable mul_left_hi  : std_logic_vector(17 downto 0);
181
variable mul_left_lo  : std_logic_vector(17 downto 0);
182
variable mul_right_hi : std_logic_vector(17 downto 0);
183
variable mul_right_lo : std_logic_vector(17 downto 0);
184
variable mul_out_0    : std_logic_vector(35 downto 0);
185
variable mul_out_1    : std_logic_vector(35 downto 0);
186
variable mul_out_2    : std_logic_vector(35 downto 0);
187
variable mul_out_3    : std_logic_vector(35 downto 0);
188
variable mul_out      : std_logic_vector(63 downto 0);
189
begin
190
  mul_left_hi  := "00" & mul_reg0 & mul_reg1;
191
  mul_left_lo  := "00" & mul_reg2 & mul_reg3;
192
  mul_right_hi := "00" & mul_reg4 & mul_reg5;
193
  mul_right_lo := "00" &mul_reg6 & mul_reg7;
194
  mul_out_0    := mul_left_hi * mul_right_hi;
195
  mul_out_1    := mul_left_hi * mul_right_lo;
196
  mul_out_2    := mul_left_lo * mul_right_hi;
197
  mul_out_3    := mul_left_lo * mul_right_lo;
198
  mul_out      := (mul_out_0( 31 downto 0) & "0000000000000000" & "0000000000000000") +
199
                  ("0000000000000000" & mul_out_1( 31 downto 0) & "0000000000000000") +
200
                  ("0000000000000000" & mul_out_2( 31 downto 0) & "0000000000000000") +
201
                  ("0000000000000000" & "0000000000000000" & mul_out_3( 31 downto 0));
202
  mul_reg8  <= mul_out(63 downto 56);
203
  mul_reg9  <= mul_out(55 downto 48);
204
  mul_reg10 <= mul_out(47 downto 40);
205
  mul_reg11 <= mul_out(39 downto 32);
206
  mul_reg12 <= mul_out(31 downto 24);
207
  mul_reg13 <= mul_out(23 downto 16);
208
  mul_reg14 <= mul_out(15 downto  8);
209
  mul_reg15 <= mul_out( 7 downto  0);
210
end process;
211
 
212
end rtl;
213
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.